JPH06124260A - Method and apparatus for providing high-performance interconnection between data buses - Google Patents

Abstract

PURPOSE: To provide a method and a device for interconnecting the 1st and 2nd information buses having plural data lines respectively. CONSTITUTION: A system 20 includes 1st and 2nd subsystems 22 and 24 and also includes an interconnection device 40 consisting of 1st and 2nd adapter modules 42 and 44 which are connected to each other by an interconnection bus 46. The interconnection bus 46 of this device 40 includes 1st and 2nd multiple conductor unidirectional information paths having plural data signals, and a couple of unidirectional information paths consisting of twisted pair cables are provided together with a 25MHz strobe. Information is transferred by using dummy ECL signal level. A couple of clock differential receiver circuits are provided, and data are transferred through the interconnection bus 46 by using both the upstream and downstream ends of a transfer clock signal and transferred from one bus to the other bus at a speed of 50MHz.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to data processing systems, and more particularly to data processing systems employing multiple buses.

[0002]

In computer and data processing systems, buses are typically used to interconnect various components of the system. For example, the central processing unit is typically connected to memory elements, input / output (I / O) devices, etc. via a bus. This bus carries signals related to the operation of each element. These signals include, for example, data signals, clock signals, and control signals.
The bus must send such signals to all elements that connect to the bus so that the desired operation is accomplished by the computer system.

As computer systems increasingly achieve higher levels of functionality, it is sometimes desirable to have more than one bus in a computer system. For example, a high-speed main system bus interconnecting a processor and a high-speed memory element is provided, and I / O devices such as a disk drive and a tape drive are connected to an I / O device.
It may be desirable to provide a separate bus that interconnects the O-control.

Initially, computer system manufacturers provided their own buses for interconnecting system components. Currently, there is an increasing trend towards the use of standard buses. In this case, the bus specifications have been published for use by all manufacturers. That allows many manufacturers to supply components specifically used in standard buses. A number of different multi-standard buses are currently available, each bus being a different collection with its own characteristics.
However, there is a growing need to be able to build computer systems that employ elements connected to a variety of different forms of standard buses. Devices and methods for providing such interconnections are known in the art. Known interconnection systems employ serial cables, ribbon cables and optical fibers. For example, a method and apparatus for interconnecting computer buses using the interconnect known as IBUS is provided by Davi.
d W. Hartwell et al. and assigned to the applicant 1
U.S. Pat. No. 4,858,23 issued Aug. 15, 989.
No. 4 is described.

As a result of these trends, the importance of different characteristics of interconnect systems will become apparent. For example, it is desirable that the interconnect system provide high transfer rates between the buses and that the functionality of the high performance bus is not compromised by the inefficient interconnect system. It would be further desirable to provide a method and apparatus for interconnecting information buses of different sizes, and for interconnecting information buses of different cabinets without a back connection between the buses. The connections between cabinets need to have high noise immunity and low noise radiation. It is also desirable to provide a method and apparatus for interconnecting buses that utilizes a minimum number of interconnect lines.

With the increasing number of standard buses, it is important for manufacturers to be able to interconnect manufactured products with as many standard buses as possible. Implementing conventional interconnection methods and devices for each bus pair results in high design and manufacturing costs. Therefore, it is desirable to provide an apparatus and method for interconnecting particularly flexible information buses and to achieve multiple connections at a minimum cost using a large number of common components.

There are no known methods and devices for interconnecting information buses which fully meet the above requirements.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and a device for connecting an information bus which fulfills the above-mentioned requirements more completely than currently known methods and devices. Other objects and features of the invention are set forth in the following description, which will be apparent from the description or can be learned by practice of the invention. The objects and features of the invention will be realized and attained by means of the instruments and combinations particularly pointed out in the appended claims.

To achieve the objects of the present invention and in accordance with the objects of the present invention, as embodied and broadly described herein, the present invention, in one form, has a plurality of data lines each. It comprises a device for interconnecting the first and second information buses. The device includes first and second multi-conductor unidirectional information paths each having a plurality of data signals. The number of data signals on each information path is less than the number of at least one data line on the information bus. This device is also the first
A first interconnect module comprising a first pair of registers for respectively receiving a first pair of sets of information appearing on the first pair of sets of data lines of the information bus of A first multiplexer for sequentially transferring each set of the first set of information from the first pair of registers across the data lines of the first information path, and
A first connector coupled to the MUX multiplexer.

The apparatus further includes a second pair of registers for respectively supplying the first pair of sets of information sets to the second pair of sets of data lines of the second information bus.
A second interconnect module comprising a pair of, a second connector removably connected to the first connector, and a first pair of sets of information sequentially transferred by the multiplexer, the set of information being received. To the second pair of registers and includes a first demultiplexer connected to the second connector. Further, the apparatus includes a third interconnect module comprising a third pair of registers each receiving a second pair of sets of information appearing on the second pair of sets of data lines of the second information bus. , A second pair of sets of information, each set of thirds via a data line of a second information path.
A second multiplexer connected to the second connector sequentially to the first pair set of sets of data lines of the first information bus to the second pair set of sets of information A fourth interconnection module comprising a fourth register for respectively supplying a second pair of information sequentially transferred by the second multiplexer, and a second pair of the information set. To a fourth register and includes a second demultiplexer connected to the first connector.

In another form, the present invention spans first and second buses, each having a plurality of data lines, over first and second multi-conductor unidirectional information paths, each having a plurality of data signals. And the number of data signals in each information path is less than the number of data lines in at least one of the information buses.
The method receives a first pair of information sets from a first pair of data line sets of a first information bus, respectively.
Actuating the first multiplexer to sequentially transfer each set of the first pair of sets of information from the first pair of registers over the data lines of the first information path, and in the second pair of registers, A first pair of information sets each receiving a first pair of information sets sequentially transferred by a first multiplexer.
Respectively from the second pair of registers to the second pair of data lines of the second information simultaneously, respectively, and from the second pair of data lines of the second information bus to the second pair of information. The two pairs are received by the third pair of registers, respectively, and the second multiplexer is actuated to drive the second pair of information from the third pair of registers across the data lines of the second information path.
Each of the sets of pairs of information is sequentially transferred, and the second pair of sets of information sequentially transferred by the second multiplexer is received at a fourth pair of registers, and the second pair of sets of information is registered by the registers. From the fourth pair to the first pair of data lines of the first information bus simultaneously.

The accompanying drawings, which are incorporated as part of this specification, illustrate only one embodiment of the invention and, together with the description, serve to explain the principles of the invention.

[0013]

The presently preferred embodiment of the invention will now be described in detail. This embodiment is illustrated in the accompanying drawings. Like letters are used throughout the drawings to refer to like components. FIG. 1 is an example of a data processing system 20 embodying the present invention. System 20 is a first and a second
Subsystems 22 and 24 of. Subsystem 22
In the preferred embodiment consists of a DEC station 5000/200 engineering workstation manufactured by Digital Equipment Corporation. Subsystem 22 includes multiple parts interconnected by a system bus 26. Bus 26, in the preferred embodiment, comprises a standard 32-bit public bus known as the TURBO channel and includes a cabinet with multiple slots interconnected by back wiring. This "32-bit" destination is directed to the 32 signal lines of the TURBO channel, which carry address and data information at different times. Such lines are hereinafter referred to as "data lines" and are distinguished from control lines that carry forms of information other than address and data information.

The TURBO channel is an internal system bus used in products manufactured by Digital Equipment Corporation. The TURBO channel is an "open architecture" bus and the detailed specifications for this TURBO channel are the TURBO channel hardware specifications publicly available from Digital Equipment Corporation, serial number EK-369AA-OD.
-005. The subsystem 22 is a system module 28 connected to the system bus 26.
including. In the preferred embodiment, system module 28 comprises an R3000 processor.

Subsystem 22 also includes a plurality of option modules. Such an optional module may include the memory 30. A communications (Ethernet) controller 32 (denoted NI in FIG. 1) and a small computer system interface (SCSI) controller 34 may be included. Subsystem 22 may include a pair of slots 36, 38 that may receive other system parts such as additional memory and controllers.

The system 20 also includes an interconnection device 40 consisting of first and second adapter modules 42,44 interconnected by an interconnection bus 46. The adapter module 42 allows the system bus 2 to be occupied by occupying slots in the TURBO channel cabinet.
6 is removably connected. In the preferred embodiment, the second subsystem 24 includes a second system bus 48.
VME bus system including System bus 48
Comprises a VME bus in the preferred embodiment. This bus is a bus that is asynchronously interlocked with other data and address lines. This VME bus is IE
It is an industry standard bus defined by EE standard 1014. Subsystem 24 also includes a plurality of VMEI / O boards 50, which are commercially available from a number of sources including Motorola Corporation, for array processing, image processing, communication control, and I / O operations. Such a function can be achieved. The second adapter module 44 is removably connected to the second system bus 48 by plugging into a slot on the bus 48.

While the present invention provides the ability to interconnect a variety of different buses, subsystem 22 in the preferred embodiment comprises a host subsystem and subsystem 24 comprises an I / O subsystem. The first subsystem bus 26 is a "TURBO channel" (or 3MA
X) and the system bus 48 is called the "VME bus". The adapter 42 is called the host adapter 42. The host adapter 42 is sometimes referred to in the table as 3VIA. Similarly, adapter 44 is referred to as I / O adapter 44 or "MVIB" in the table. Interconnect bus 46 is referred to in the table as the "YA bus."

Referring to FIG. 2, the interconnection device 40 is shown in detail. Interconnect bus 46 of device 40 includes first and second multi-conductor unidirectional information paths each having a plurality of data signals. The number of data signals in each information path is less than the number of data lines in TURBO channel 26 and VME bus 48. In the preferred embodiment, the information paths 52, 54 each include 16 data signals. In particular,
The information path 52 is the first and second twisted pair cables 5.
6, 58, each cable connected to a plurality of twisted pair conductors and first and second conductors 60, 62. Path 54 includes third and fourth twisted pair cables 64, 66 connected to conductors 62, 60, respectively.
In addition, the information paths 52, 54 each include three polarity signals, three form and mask signals, strobe signals, and reset signals. The information paths 52, 54 are therefore four of the twisted conductors surrounded by both the blade and foil shield.
Includes 7 pairs (plus 3 spares). Information path 5
A pin count of 2,54 is shown in Table 1 for the preferred embodiment.

[0019]

[Table 1] Each signal requires two pins with twisted pair wiring. Although the preferred embodiment of the present invention employs a single cable that includes 50 twisted conductor pairs surrounded by a shield and interconnected by first and second conductors 60 and 62, The invention is not limited to this. Of course, other forms of connection that can be employed will be readily appreciated by those skilled in the art.

The device 40 also includes first, second, third and fourth devices.
Interconnect modules 68, 70, 72 and 74 of. Modules 68 and 72 are equivalent and each consist of an interconnected transmitter. Modules 70 and 74 are equivalent and each consist of an interconnected receiver. Therefore, only modules 68 and 70 will be described in detail. The host adapter 42 includes a host interface circuit 75, and the adapter 44 includes an I / O interface circuit 76.

In accordance with the preferred embodiment, the host interface circuit 75 includes a first TURBO channel 26, such as a TURBO channel 26.
It is specially configured to interface with the information bus. The I / O interface circuit 76 is the VEM bus 4
It is specially configured to interface with a second information bus such as 8. As described in more detail below, the host interface circuit 75 receives and transmits via the TURBO channel 26 using the instructions defined as part of the TURBO channel specification. Similarly, the I / O interface circuit 7
6 performs transmission and reception via the VME bus 48. This bus uses instructions defined as part of the VMEbus specification. However, an important feature of the present invention is that the interconnect bus 46 and interconnect module 6 are
Adopting 8-74 in conjunction with another host interface circuit 75 and another I / O interface circuit 76 facilitates TURBO with minimal design effort.
The purpose is to interconnect the information buses other than the channel 26 and the VME bus 48. For example, the host interface circuit 75 may be a DEC system 550RIS manufactured by Digital Equipment Corporation.
It can be designed to interface with systems that employ C-based servers. In addition, I / O interface 7
The 6 is redesigned to interface with systems that employ another bus, such as the Futurebus.

As can be seen from FIG. 2, the data is TURBO.
It flows bidirectionally between the channel 26 and the host interface circuit 75. Data is transferred from the host interface circuit 75 to the first connector 60 and the second connector 6
2, through the second twisted pair cable 58 and the second interconnection module 70 to the I / O interface circuit 76 in one direction. Data flows bidirectionally between the I / O interface circuit 76 and the VME bus 48. Data is transferred from the I / O interface circuit 76 to the third
Host interface circuit 75 via interconnect module 72, third twisted pair cable 64, second connector 62, first connector 60, fourth twisted pair cable 66, and fourth interconnect module 74.
Flows in one direction.

TURBO channel 26, as fully described by the TURBO channel use described above.
Is an address data bus in which 32 bits are switched in synchronization with 40 nS cycle time. Direct memory access (DMA) has a transfer capacity of up to 100 megabytes / second. The TURBO channel 26 supports one interrupt per slot and maps up to 512 Mbytes of I / O on the "SEL" line. Arbitration has been granted to DMA. If there is contention on the VMEbus 48, the "collision" signal allows the CPU read and write requests to be "retryed". Byte mask byte is DM
Supported for CPU I / O transactions (in the address field) rather than A. The host adapter 42 accomplishes the read-modify-write cycle (non-atomic) to DMA to the memory circuit 30 (FIG. 1).
Enables byte writing. TURBO channel 2
The instruction forms supported by 6 are described in Table 2.

[0024]

[Table 2] Referring to FIG. 3, a detailed block diagram of the host interface circuit 75 is shown. As shown in FIG. 3, the buffer 80 transfers data between the TURBO channel 26 and the host interface circuit 75. The buffer 80 can be, for example, a model number 29FCT52B buffer circuit commercially available from Integrated Devices Technology, Inc. (IDT). Addresses and data are strobed out of the TURBO channel 26 (via buffer 80) to the interconnect module 68 when a write instruction is executed from subsystem 22 to subsystem 24. In some applications, address and data information may be first processed by multiplexer 82.

The host interface circuit 75 also includes a programmable read only memory (PROM) 84. The PROM 84 is provided for diagnostic purposes. The address information from the backup 80 is the address register 8
It is translated as an address input to PROM 84 via 6. This address translation step is accomplished to uniquely select a particular location within PROM 84. PROM
The contents of 84 are then provided to buffer 80 via line 88.

The host interface circuit 75 also includes a command status register (CSR) 90. C
SR 90 stores error and status information from interconnect bus 46 and provides reset control. The specific configuration of CSR 90 is described in Tables 3-8.

[0027]

[Table 3]

[0028]

[Table 4]

[0029]

[Table 5]

[0030]

[Table 6]

[0031]

[Table 7]

[0032]

[Table 8] The host interface 75 also includes a register 92. Registers 92 are FIFO 190 (FIG. 6) and TUR
It is provided to synchronize the data between the output buffers 80 on the BO channel. The register 92 can be a model number 29 FCT52B buffer circuit available from the IDT.

The host interface circuit 75 further includes a register 94. This register 94 is the VME bus 48
Given to enable DMA transfer to. In particular, address information is stored in register 94 and is incremented each time each word is transferred from VME bus 48 to TURBO channel 26 via the DMA process. The host interface circuit 75 further includes a control logic circuit 96.
Circuit 96 defines the instructions for TURBO channel 26 and interconnect bus 4 on line 97.
Translate between the instructions defined for 6. This is explained in detail below.

FIG. 4 shows the I / O interface circuit 7
A detailed block diagram of 6 is shown. The I / O interface circuit 76 uses a model number VIC068 VMEbus controller 100 commercially available from VTC Corporation. The VIC controller 100 fully satisfies IEEE Standard 1014 and supports all standard VMEbus operations including data transfer instructions as shown in Tables 9-11.

[0035]

[Table 9]

[0036]

[Table 10]

[0037]

[Table 11] In addition, controller 100 handles data bytes 0-7 and addresses 0-7 from VMEbus 48. Upper address and data bytes are buffers 102 and 10, respectively.
4 to and from the VME bus 48.

A feature of certain VEM bus interrupts is that the VIC
Similarly supported by controller 100. In particular, V
The IC controller 100 receives the following interrupts. ACfail (provided by power), DCfail (obtained from VMEbus 48), arbitration time out and interrupt handshake from VME interrupter, request from VMEbus interrupt, and seven local interrupts shown in Table 12 below. Is. The VIC controller 100 interrupt handler is
Interrupt handler register (IHR) of controller 100
When programmed by, encode each interrupt or interrupt group into any of the seven levels. Two
All 0 interrupt levels are aggregated into a single interrupt request to processor 20 (unique to the option slot occupied by processor 28 in FIG. 1). VI
The interrupt priorities processed by the C controller 100 are listed in Table 13.

[0039]

[Table 12] Load the VIC local interrupt base register with the value 08H for the specified LIRO vector.

When these local interrupts are enabled (via the VIC interrupt control register), a vector (programmable from the VIC local interrupt vector base register when the IVS is read when the interrupt is pending) -See Figure 12.10 of the VTC068 specification). All interrupts send 8-bit data on the YA bus and 3VIA feeds these data to 3MAX. MIPS Fair 2
Requests a 16-bit vector from MVIA, and 8 on d [7: 0]
The bit vector is added to the vector offset register (VOR) 9 on d [15: 8], filling d [15: 0] on the RIO data [15: 0] with the complete 16-bit vector.

[0041]

[Table 13] The VIC controller 100 uses the data byte 7 of the VMEbus 48.
You can return the associated vector above. This vector can then support processor 28 for vector cycles or be read as a vector register. The I / O interface circuit 76 is the VIC controller 1
00 to achieve a vector cycle, VIC controller 10
Whenever an interrupt vector source (IVS) of 0 is read, the interrupt vector is obtained.

The VMEbus interrupt vectors 00H to 3FH are assigned to special peripherals that are not part of the present invention, and all interrupts and tables generated by the VIC controller 100 listed in Table 13 are listed. It is used to provide the exception vector generated by the I / O interface circuit 76, including the I / O interface circuit 76 local interrupts listed in 12.
Furthermore, the host interface circuit 75 uses the vector 01
An error interrupt of H can be sent and the interconnection bus 46
Can handle protocol errors.

When the local interrupt in Table 12 is enabled, the vector is IVS when the interrupt is pending.
Is generated when reading the. All interrupts are sent to the interconnect bus 46 as 8-bit data and the host interface circuit 75 presents these interrupts to the TURBO channel 26. The host interface circuit 75 also includes the control circuit 101. This control circuit 101 is a circuit 7
Control signals for the five constituent circuits are given. Control circuit 10
1 is a signal line 103 connected to the interconnection modules 70 and 72.
Connected via. A detailed description of the circuit 101 is given below.

As described above, the embodiment described here is T
Provides interconnection between URBO channels and VMEbus 48. The TURBO channel 26 is designed for use with a processor manufactured by Digital Equipment Corporation. VMEbus 48 is designed for use with a processor manufactured by Motorola. Such processors handle data according to different byte-order address translations, known by those skilled in the art as "big endian" and "little endian," respectively. Therefore, the I / O interface circuit 76 includes a byte swap circuit 106 and uses the modes defined in Table 14 to provide the proper alignment of data and addresses.

[0045]

[Table 14] As shown in FIG. 4, the I / O interface circuit 76
Includes an internal data bus 108 and an internal address bus 110. The circuits 100, 102, 106 are connected to buses 108, 110 as shown in FIG.

Incoming data from interconnect bus 46 and module 70 is provided to internal data bus 108 via data buffer 112. Buffer 112 is ID
It can be model number 29FCT520B commercially available from T. Output data to interconnect bus 46 is passed from VME bus 48 to data bus 108 via circuits 100, 104 and 106, and then to interconnect bus 46 via data buffer 114 and via module 72. Buffer 114 is model number 29FCT commercially available from Motorola Corporation.
820 circuits.

To enable the byte swapping function described above, the I / O interface circuit 76 includes a PIO page map RAM (PMR) 116 and a DMA P.
Includes MR 118. PI to connect with byte write latch
O PMR 116, address buffer 122, and data buffer 124 work with byte swap circuit 106 to accomplish byte swapping operations on data transferred from interconnect bus 46 to VME bus 48. DMAPMR1 that connects to the multiplier 126
18 and the buffer 114 are the byte swap circuit 106.
Works together to provide byte swapping operations for data transferred from VME bus 48 through module 72 to interconnect bus 46. Design considerations in connection with such bite swapping operations are well known to those skilled in the art, but are not essential to understanding the present invention.
However, details of the bite swapping technique implemented in the preferred embodiment are described by James Duval et al., 1990.
Listed in U.S. Patent Application No. 546,507, filed June 29 and assigned to the applicant. Reference may be made to the disclosure of this application.

The error address register 128 is a PIO P
Working in conjunction with MR 116, it supplies the error address to internal data bus 118 in the event that the transaction has not completed, such as because there is no memory device at the address location. The instruction status register (CSR) 130 is I
/ O interface circuit 76 is provided. CSR
The formats of 130 are shown in Tables 15-21.

[0049]

[Table 15]

[0050]

[Table 16]

[0051]

[Table 17]

[0052]

[Table 18]

[0053]

[Table 19]

[0054]

[Table 20]

[0055]

[Table 21] The present invention thus initiates a transfer from a first information bus to a second information bus and from a second information bus to a first information bus in response to a command received from the first and second information buses. Control means for In this embodiment, the control means is composed of interface circuits 75 and 76.

A detailed block diagram of the first interconnect module 68 is shown in FIG. The module 68 constitutes a transmitter for transferring data from the host interface circuit 75 to the first twisted pair cable 56. Module 68 includes a first in first out (FIFO) memory 140. The memory 140 is connected to the TURBO via the line 83.
Store the 32-bit word of address and data information from the 32 data lines of channel 26. Memory 40
Are provided to a first pair of registers 142, 144, each register from the first pair of 16 line sets of data lines on the TURBO channel 26 (FI
Each receives a first pair of 16-bit sets of transferred information sets (via FO 140). Register 14
The 2, 144 may be model number 74F374, commercially available from Motorola Corporation. The outputs of the registers 142, 144 are provided to the first multiplexer 146 for sequentially transferring each set of the first pair of information sets from the registers 142, 144 via the 16 data signals of the path 52. .

Various forms of digital logic circuits are available to circuit designers, as is well known to those skilled in the art. One example of such a circuit configuration is an emitter coupled logic (E
CL). Another available form is transistor-transistor logic (TTL). Preferably, the invention comprises first ECL differential converter means coupled between the first multiplexer and the first twisted pair cable. In the preferred example, such means comprises an ECL differential converter 148. The converter 148 functions are all available from Motorola Corporation, Model No. 10
This can be achieved with an H351 converter circuit and a model number 10H151 differential latch circuit.

The present invention further preferably comprises a second ECL differential converter means coupled between the second multiplexer and the third twisted pair cable 64 for converting a TTL compliant signal to an ECL compliant differential signal. Including. In the preferred embodiment, such means comprises a differential converter circuit 148 within the interconnect module 74 corresponding to the converter circuit 148. The function of this corresponding circuit is provided by the model number 10H351 converter circuit and the model number 10H151 differential latch circuit.

While ECL technology employs voltage levels of -5.2 volts and ground, in the preferred embodiment of the present invention,
The common terminal of the circuit provides "pseudo ECL (pECL)" operation by tying it to the +5.0 volt output of the system power supply. Such ECL compatible voltage levels of the differential pair of conductors provide the constant current and offer the significant advantage of producing less surge and switching noise when compared to TTL and CMOS configurations. Moreover, the common mode noise signal level is reduced and a single 5 volt power can be employed.

Each data signal representing the first pair of bits of the set of information from registers 142 and 144 is converted into a differential signal that is transferred through one twisted pair of conductors of the first twisted cable 56. It The control signal from the circuit 96 of the host interface circuit 75 is supplied to the control logic circuit 150 via line 97. Circuit 150
Translates commands on the TURBO channel 26 into commands unique to the interconnect bus 46. Circuit 96
And a more detailed discussion of 150 is described below in connection with FIGS. 9 and 10, respectively. Table 2 shows the interconnection bus instructions
Shown in 2.

[0061]

[Table 22] ^An interrupt vector is obtained by accomplishing a register read to a vector location rather than deciding the vector cycle to the YA bus protocol. This particular host interrupt module produces the appropriate vector cycle through this "read register" method. ^{2 When a} DMA read is requested, xVIA sends a block of 256 bytes to MVIB's YtM FIFO. If the VME DMA does not need all the data sent, the unused data will be
It needs to be removed from the FIFO before a YA bus message can be sent. ³ n cannot exceed 63, which corresponds to 256 bytes of data. ⁴ Issued by MVBI only ⁵ Data field provided to provide byte mask information for read transactions. ⁶ Data field is the IP of the newly sent interrupt request
Provided to deliver L [3: 1]. ⁷ Negative confirmation for transfer module: Parity error, incorrect command, memory not present or incorrect PMR selected ⁸ Error message issued when multiple messages are outstanding An error command is issued and a specific command causes a Nack. Guarantee that you got. See Section 10.8 for details.

The interconnect bus command is the interconnect bus 46.
Control circuit 150 supplies to multiplexer 146 for transfer via. The control circuit 150 also provides the form and mask (TAM) signal for transfer via the interconnect bus 46 and via the ECL differential converter 155. The morphology and mask signals specify the morphology of the information carried over the data lines provided as output from the converter 148. In particular, the following forms of information: commands, addresses, data and idles are carried over interconnect bus 46. The morphology and mask signals determine the morphology of the transferred data shown in Table 10. For all forms of information, the lower halfwords are sent first and clocked at the end of the strobe signal. The upper halfword (D [31:16]) is sent next and clocked on the falling edge of the strobe signal.

[0063]

[Table 23] ^{For one} mask bit, "1" indicates that the data byte is correct and "0" indicates the incorrect data byte. Mask [1] is associated with data bytes [31:24] or data bytes [15: 0], and mask [0] is associated with data bytes [23:16] or data bytes [7: 0].

Information begins and ends with an idle frame, and is transferred over interconnect bus 46 as a message containing a command frame and an address frame. The message also includes one or more data frames.
All messages get positive confirmation from the receiving end. The command, address and data frame formats for interconnect bus 46 are shown in Tables 24-26, respectively.

[0065]

[Table 24]

[0066]

[Table 25]

[0067]

[Table 26] The output of the memory 140 is also provided to the parity generator 152 to generate a pair of parity signals for transfer across the interconnect bus 46 via the ECL differential converter 153.

As shown in FIG. 5, the first clock signal 154 is supplied to the register 142. Clock signal 1
54 has a clock rate of 25 MHz in the preferred embodiment. As will be described in more detail, the second clock signal is provided to the third register pair within module 72, as is clock signal 154. A third clock signal 156 is similarly provided. The clock signal 156 is generated by the oscillator circuit 158 at a rate of 50 MHz in the preferred embodiment.
Generated by. The third clock signal 156 is supplied to the SEL terminal of the multiplexer 146. The corresponding fourth clock signal, like the third clock signal 156, is provided to the corresponding multiplexer in module 72. The clock signal 156 is a 2: 1 divider circuit 16
0, and a clock signal 154 is generated. The clock signal 154 is the delay circuit 162 and the TTL-pECL.
A differential strobe signal 165 is provided to converter circuit 163 and is similar to clock signal 154, but delayed by a period of 10 nS. Circuits 160, 162, 16
3 (and the corresponding circuitry of interconnect module 72)
The third and fourth clock signals are divided into first and second clock rates, respectively, to generate first and second clock signals, the first and second information paths being respectively routed to the first and second clock paths. It comprises frequency divider means for supplying the second clock signal.

The interconnect modules 68 and 72 further include 2
The first and second clock speeds of 5 MHz are set to the first register
And means for storing information in the first and third pairs of registers, respectively, and third and fourth clocks at twice the first and second clock rates (ie 50 MHz). Means for supplying a third and a fourth clock signal having respective speeds to the first and second multiplexers, and a third at a third and a fourth clock speed respectively in response to the third and the fourth clock signal. It will be appreciated that it further includes means for transferring information across the first and second information paths.
In the preferred embodiment, such means are oscillators 15.
8, frequency divider 160, and multiplexer 146, and the corresponding circuitry of interconnect module 72.

The signal on control line 97 is reset 170.
including. Reset signal 170 is provided to converter circuit 174 via buffer 172 to provide a pECL differential reset signal via information path 52. Referring to FIG. 6, a detailed block diagram of the interconnect module 70, which comprises a receiver for the interconnect module bus 46, is shown. As described above, the interconnect module 74 is the module 70.
Is equivalent to Module 74 is therefore not discussed in detail.

As shown in FIG. 6, the differential signal of the information path is received through the connector 62, and the ECL differential receiver 1 is received.
80. Each set of the first pair of information sets is sequentially received via the receiver 180 and provided to a second pair of registers 182, 184, respectively. That is, TU
The data bits from lines 0-15 of RBO channel 26 are first transmitted as 16 data signals on interconnect bus 46 and stored in register 182. Then T
Data bits from lines 16-31 of URBO channel 26 are transmitted as data signals on interconnect bus 46 and stored in register 184.

The strobe signal 165 is converted by the first and second clock multiplier means by the first and second clock multiplier means and converted by the interconnect modules 70 and 74 to transfer the transferred first and second clock signals. Transferring the clock signal provided to the fourth pair to transfer information from the second and fourth pairs of registers to the second and first information buses at third and fourth clock rates, respectively. .. Preferably, such means are connected to the connector 62 and registers 182 and 184, respectively, to provide a divided third clock signal to the registers 182 and 18, respectively.
4 and a pair of ECs feeding the interconnection module 74
It consists of L differential receiver circuits 186 and 188. Circuit 18
6 and 188 provide non-inverted and inverted transfer clock signals 187 and 189, each consisting of a single-ended TTL compatible signal.

The output of the differential receiver 180 is a 16-bit wide path and is provided to registers 182 and 184. These registers consist of 16-bit wide storage devices. The outputs of registers 182 and 184 are provided to the upper and lower halves of 32-bit wide path 192 and as inputs to FIFO memory 190, which comprises a 32-bit wide memory. The line of path 192 is also connected to control logic 194. The control circuit 194 is also ECL
Received form and mask information from the differential receiver 196 and received command information and receiver 19 from line 192.
VM using the morphology and mask information received from
Generates command instructions compatible with E-bus 48 and provides confirmation of the request issued from the VME-bus.

The parity check circuit 198 is an ECL.
The parity signal generated by the parity generator 152 is received from the differential receiver 200 and the TTL via the ECL differential converter circuit 153 (FIG. 5). The parity checker 198 uses this information to check the parity on line 192 and provide an error signal 202 upon parity error detection.

The reset signal generated by the ECL converter 174 (FIG. 5) and provided on the interconnect bus 46 is received by the ECL differential receiver 204 and the VM
It is provided as a reset signal 206 for use on the E-bus 48. FIG. 7 shows details of the termination circuit of the ECL differential converter and ECL differential receiver shown in FIGS. As can be seen from FIG. 7, each converter has a non-inverting output 2
10 and inverted output 212. Inverted output 212 is represented by one cycle at the output of each ECL differential converter.

The termination resistor 214 is connected between the output 210 and the ground. Similarly, the termination resistor 21
6 is connected between the output 212 and the ground. In the preferred embodiment, termination resistors 214 and 2
Each 16 has 360 ohms. Each ECL differential receiver includes a non-inverting input 218 and an inverting input 220. The termination resistor 222 is the input 21 of each ECL differential receiver.
It is connected between 8 and 220. In the preferred embodiment, the value in register 222 is 110 ohms. As a result, each twisted pair has an impedance of 105 ohms.

A description of the operation of interconnect modules 68, 70, 72 and 74 is provided with reference to FIGS. When data is received by the FIFO 140,
A “FIFO NOT EMPTY” signal is generated and supplied to the control circuit 150. Control circuit 150 then causes circuit 140 to provide 32 bits of data on output line 141. Data is clocked into each register 142 and 144 at the rising edge of clock signal 154. The data from registers 142 and 144 is the multiplexer 14
Appears in 6 inputs. One or the other of the data sets appearing at the inputs of the multiplexer 146
6 is provided as an output from the multiplexer depending on the state of the SEL terminal. SEL terminal is clock signal 1
56 is connected to the SEL of the multiplexer 146.
The terminal changes at a speed of 50 MHz. Accordingly, multiplexer 146 sequentially transfers the first pair of sets of information from registers 142 and 144 via the data lines of information path 52.

The first pair of 16-bit information from registers 142 and 144 is transmitted through twisted pair cable 56, connector 60, connector 62, and twisted pair cable 58 to differential receiver 1 of module 70.
80 (FIG. 6). Strobe signal 165 is 2
A clock signal ECL differential receiver circuit 186 and 188 is provided as a differential signal at a speed of 5 MHz. The outputs of these differential receiver circuits are connected to the clock terminals of registers 182 and 184, respectively. Circuits 186 and 1
The strobe signal received by 88 is provided to registers 182 and 184 as the non-inverted and inverted transfer clock signals, respectively, thus register 182 and 184.
Transfers 16 bits of data from each line of the output of circuit 180 to each of registers 182 and 184 at a rate of 25 MHz. The outputs of registers 182 and 184 are then
It is provided as a 32-bit wide word on line 192 for storage in FIFO 190 at an effective rate of 50 MHz.

From the above description, the present invention receives a first group of sets of information connected to a second connector and sequentially transferred by a first multiplexer,
It can be seen that it includes a first demultiplexer which supplies a respective first group of sets of this information to a second group of registers. As in this embodiment, the first demultiplexer means comprises differential receiver circuits 180, 186 and 188. The invention also receives a second group of multiple sets of information coupled to the first connector and sequentially transferred by the second multiplexer, and registering the second group of multiple sets of information to a register. Includes second demultiplexer means for supplying each to the fourth group. As in the present embodiment, this second demultiplexer means comprises the differential receiver circuit of the interconnection module 74 corresponding to the differential receiver circuits 180, 186 and 188.

Interconnect module 72, as previously described.
And 74 are equivalent to modules 68 and 70, respectively. Therefore, the operation of modules 72 and 74 occurs analogically. The apparatus and method described above thus provide two 16-bit data paths, using a positive confirmation protocol to generate a raw bandwidth of 100 Mbytes / sec with a continuous data strobe of 25 MHz.
All data is transferred in 32 bit words and 16 bit entities are clocked in on both the rising and falling edges of the clock.

FIG. 8 is a timing diagram showing the relative timing of various signals of the apparatus shown in FIG. 2 for a WRITE WORD cycle. As shown in FIG.
Clock signal 156 (also shown in FIG. 5) consists of clock pulses at a rate of 50 MHz. Each full clock cycle consists of 20 nS. The strobe signal 165 (also shown in FIG. 5) has a rate of 25 MHz and each half cycle is 2
It has a period of 0 nS and is delayed by 10 nS. Figure 6
The outputs 187 and 188 of the circuits 186 and 188 of
It consists of a pair of anti-phase clock signals having a speed of MHz. These signals are used as clock data to the registers 182 and 184, the rising end of the signal output by the circuit 186 clocks the data into the register 182, and the rising end of the output of the circuit 188 transfers the data to the register 184. Input the clock inside.

Thus, a WRITE WORD cycle consists of a pair of idle cycles 250 and 252, followed by a command cycle 254 and the transfer of bits 0-15 of the command word. Strobe signal 165
The rising end of cycle 2 at the time indicated as 256
16 bits of data appearing as the output of circuit 180 in 54 (ie, the low order bits) are clocked into register 182. In command cycle 258,
The upper bits of the command word are transferred via interconnect bus 46. Strobe signal 1 generated at time 260
The falling of 65 is the signal 165 output by the circuit 188.
Coincides with the rising end of. The rising edge of signal 189 latches the upper 16 bits of the data transferred to register 184 via interconnect bus 46 after the lower 16 bits.

In a similar manner, the low and high bits of the address word and the low and high bits of the data word are transferred sequentially into registers 182 and 184, and FIFO1
90. As a result of the WRITE WORD cycle, a pair of idle cycles is transferred. The preferred embodiment employs a pair of differential receiver circuits for the strobe signal 165 and data is provided to the interconnect module 70 on both the rising and falling edges of the strobe signal 165. Other methods can be adopted. For example, registers 182 and 1 that directly latch a pair of latch circuits from the single-ended signal 165 at the ends of the positive and negative pulses of signal 165, respectively.
It can be used instead of 84.

The transaction uses a positive acknowledge signal and conducts through the interconnect bus 46 using the flags described in Table 27. Flags A and B
Is located in module 68 (FIG. 2) and flag C is located in module 72.

[0085]

[Table 27] The present invention includes means for receiving a block data read command from the VME bus and transferring the block data read command to the TURBO channel. In the preferred embodiment, these means comprise I / O interface circuit 76 which receives a DMA READ command from VME bus 48. The I / O interface circuit 76 is transferred by the interconnect module to the interconnect module 74 via the interconnect bus 46. The host controller 75 then sends the TU
Transferred via RBO channel 46, DMA RE
The AD command is next generated.

The present invention sends the block data read confirmation signal and the requested data to the VME bus in response to the block data read command from the VME bus, and sends the block data read flag when the block data read confirmation signal is sent. Means for delivering is further included in the first interconnect module. In this embodiment, this means is a READ that is transferred over the interconnect bus 46. BLOCK
ACK signal, READ It includes a control circuit 150 that is generated when a BLOCK command is received. At the same time, B
The flag is set and stored in control circuit 150 as shown in Table 14.

The control circuit 150 generates a signal to the host interface circuit, and the host interface circuit 75
Prohibits receiving commands from the TURBO channel as long as the B flag is set. The invention further preferably temporarily stores the data received in response to the block data read command, purges the storage means, and when the purging of the storage means is complete, a purge complete command is issued to the fourth command. Means for forwarding interconnect commands are included in the interconnect module 70. In this embodiment, such means are provided by the F of the interconnection module 70.
It consists of IFO 190. It receives data transferred from subsystem 22 via interconnect bus 46 in response to a DMA read command originally generated by the VMEbus. FIFO 190 for all requested data
Control circuit 194 flushes unused data from the FIFO 190 and sends an appropriate indication to the VIC control circuit 100. The VIC control circuit 100 then transfers to the control circuit 150 of the interconnect module 72, PURGE which is transferred to the interconnect module 74 via the information path 54.
Generate a COMPLETE command.

The present invention further preferably includes means for resetting the block data read flag when a purge complete command is received by interconnect module 74. Such means are embodied in the control circuit 150 of the interconnection module 68, which is the PURGE COMP.
When the LTE command receives the interconnect module 74, it resets the B flag.

The present invention is more preferably from a VMEbus.
Receives the data transfer command and sends the data command
Data to the TURBO channel via path 54
Set the data transfer flag when transferring a transfer command
From the VEM bus when the data transfer flag is selected
Of commands received by the interconnection module 72
Includes means for prohibiting transfer via information path 54.
Mu. In this embodiment, the I / O interface circuit 76 is
These commands are sent to the control circuit of the interconnection module 72.
This control circuit transfers data through the information path 54.
READ WORD, WRITE WORD, RE
AD BLOCK and WRITE BLOCK command
Generate a corresponding command such as. A command like this
Of the interconnect module 72 when any of the
Control unit 150 sets the C flag. C hula
VME bus commands are translated as long as
Not be forwarded through the information path.

Preferably, the present invention is an interconnect module.
That the data transfer command has been received by
In response, generate a data transfer confirmation signal and confirm the data transfer.
Includes means for sending signals to the interconnect module 70.
Mu. Such means are provided by the interconnection module 74.
READ when the corresponding data transfer command is received
WORD ACK, WRITE WORD ACK, R
EAD BLOCK ACK or WRITE BLOCK
Control of interconnection module 68 for generating ACK signal
Embodied in circuit 150.

The present invention further preferably includes means for resetting the data transfer flag when a data transfer confirmation signal is received by the interconnect module 70. Such means are provided for the control circuit 150 of the interconnection module 72.
This circuit resets the C flag when a corresponding confirmation signal is received by the interconnect module 70.

FIG. 9 shows the control circuit 96 of FIG. 3 in detail. The control circuit 96, in the preferred embodiment, includes four state machine units 300, 302, 304 and 306, respectively PIO control, address decode, and DM.
It corresponds to A control and interrupt control. The PIO controller 300 is a TUR for programmed I / O requests.
Manages the BO channel interface. PIO controller 300 includes select and write inputs that accept PIO read word requests and PIO write word containers, respectively. The PIO control device 300 is a PIO The ACK confirmation signal is received as a protocol sequence checker in circuit 150, as described in detail below.
The PIO controller 300 produces an output to the TURBO channel 26 that includes the rdy signal and the collision signal. PI
The O controller 300 includes a circuit 15 described in detail below.
The PIO REQ signal is generated to the command generation circuit of 0.

The address decoding device 302 uses all PIOs.
By performing the functions of decoding cycles and making signal paths available, the morphology of the transactions required by the PIO cycle is clarified. The address decoding device 302 includes TURBO along with selection and clock signals.
22 bits of address information are received from channel 26. The address decoding device 302 uses cs for csr
The r select signal, the PROM chip select signal supplied to the PROM 84, the ivs chip select signal, and the ya bus chip select signal are generated to the circuit 150 of the command generator circuit as described in detail below.

The DMA controller 304 manages the TURBO channel interface for direct memory access requests generated from the VMEbus. The DMA controller 304 accepts the DMA request from the control circuit 150, requests the TURBO channel access, and sends the TURB.
D on the O channel (including address and data information)
It performs the function of generating MA cycles, generating RMW operations for partial words, generating DMA acknowledge signals to the arbiter for bus 46, and sending data to interconnect module 68 in block read commands. DMA controller 3
04 sends rdy, ack, and collision signals from the TURBO channel 26 and DMARE from the control circuit 150.
Receive the Q signal. The DMA controller 304 uses rReq
And wReq signal to the TURBO channel 26,
The RMW buffer control signal is given to the register 92, and the circuit 1
DMA to 50 A read data signal is provided to the ACK signal and the circuit 150.

The interrupt controller 306 handles interrupt requests received on the VME bus and handles these requests in TURBO.
Send to channel 26. The interrupt controller 306 responds to the request received via the interconnect bus 46 by the TUR.
It achieves the function of generating an interrupt request on the BO channel and the clear function when the CPU reads the ivs register. The interrupt controller 306 uses the INT from the circuit 150. REQ and FAIL Receive the STATUS signal. The interrupt controller 306 sends the int signal to the TUR
Occurs on BO channel and INT to circuit 150 REQ
Generate an ACK signal.

FIG. 10 is a detailed block diagram of the control circuit 101 of the I / O interface circuit 76.
Circuit 101 includes six state machine units 318, 320,
322, 324, 326 and 328. Device 318
Consists of a PIO address decoder device which unravels the form of transactions required by PIO cycles on interconnect bus 46. Decode all PIO cycles to achieve the function of making a particular path available. Address decoder device 318 receives the 22 FIFO output address signal from FIFO 190. Device 31
8 is an address cycle (addr) from the control circuit 150 of the module 70. cycle) signal is received. Address decoder device 318 selects csr chip (cs)
Generate a signal to the CSR 130. Other outputs of the address decoder device 318 include the PIOpmr chip select (cs) signal to the PIO-PMR RAM 116 and PIO-PMR controller 320. Address decoder device 31
8 further includes a DMApmr chip select (cs) signal.
This signal is used by the DMA-PMR RAM 118 and the DMA.
-Supplied to the PMR controller 322. The INT cycle is supplied to the interrupt controller 328 and fails-addr chip select (fail). The adrsel) signal is supplied to the failure address register 128. Finally, the address decoder unit 318 selects VIC (se
l) and VME selection (sel) signals to VIC control circuit 1
Supply to 00.

The PIO PMR controller 320 writes PIOs to write (wrt) and read (rd) (load and test) and to access RAM (PIO access).
Manage page map RAM. This control device 320
Sends an error if it accesses an incorrect register. The device 320 accomplishes the functions of enabling data paths for PMR loading and PMR testing, and DMA access for PMR and testing incorrect data paths for pmr. The device 322 uses the PIO from the address decoder 318. PMR chip selection and PIO
Receive a REQ signal. Device 320 also receives read (rd) and write (wr) signals from circuit 150, and
io pmr d signal to PIO-PMR RAM116
To receive from.

The device 320 outputs a buffer rice as an output.
Generate a table signal to the data buffer 124, and
pmr rd and pio pmr RAM for wr signal
It occurs to 116 and pio pmr not correct (inva
lid) signal to circuit 150. DMA PMR
The controller 322 writes (wrt) and reads (r
d) Access (load and test) and DMA requests to RAM
Manages the DMA page map register to access
It Also, every time the incorrect register is accessed, the device
Send an error to. Device 322 loads and tests the pmr.
Make the data path available for trials and use the DMA access of pmr
Incorrect pm that can use the address path for access
It accomplishes the function to test r. Device 322 is D
MA The address decoder device 3 receives the pmr chip select signal.
18 to VIC control circuit 100 to vic DMA R
Receive the EQ signal. Device 322 is from control circuit 194
Read (rd) and read from VIC control circuit 100
It receives the (rd) and write (wr) signals. Device 32
2 is further dma pmr Receives D signal from RAM 118
Believe. Device 322 can buffer A as output
(Enable) signal to buffer 114, mux control
Multiplexer 126 for control signal
, DMA PMR PDdma pmr WR signal
Send to gram 118. Finally, the device 322
Is dma pmr invalid signal
Occurs and interrupts controller 328.

Bus arbitration device 324 manages internal buses 108 and 110 of circuit 76. This device 324 accomplishes the function of arbitrating between host requests, VME requests and interrupt requests. The device 324 uses the host sel signal from the circuit 194 and the vme from the VIC control circuit 100. The REQ signal and the interrupt (int.) Req signal from the interrupt controller 328 are received. Device 324 is host has The bus signal is generated to the PIO-PMR controller 320, the VIC control circuit 100, and the byte swap controller 326. Finally, the device 324 interrupts the interrupt controller 328. has bu
The s signal is output.

Byte swap controller 326 manages the data path between interconnect bus 46 and VEM bus 28. This unit 326 accomplishes the function of swapping bytes on a 32-bit word boundary specified by control bits in the page map register. That is, the byte swap control is specified on a page-by-page basis.
Device 326 is RAM 116 to PIO d byte swap control signal (PIOd) and RAM 118 to DMA
d-byte swap control (DMA d) Receive a signal.
The device 326 receives the 3-bit mask signal from the FIFO 190 and sends it from the VIC control circuit 100 to the VME. dso-
ds1, A01, Receive the LWORD signal. Device 326 is also a vme from bus arbitration device 324. has
bus and host has Bus signal to VIC
A PIO read / write request (rea from the control circuit 194
d / write req) signal, and DMA read / write (read / write re) from the VIC 100.
q) Receive the signal. Finally, the device 326 receives a DMA chip select (sel) signal from the VIC control circuit 100. The device 326 is a swap control (control)
And swap direction signal to VIC
It is given to the control circuit 100.

Interrupt controller 328 manages interrupts generated by VME bus 26 and circuit 76 via VIC control circuit 100. These interrupt requests are translated and the interrupt request message is formatted for interconnect bus 46. The device 328 samples the IPL signal from the IC control circuit 100 to detect the request,
It sets the latch for each detected request to each IPL level, sends an interrupt request to circuit 150, and performs the function of sampling the interrupt vector request cycle to clear the latch. The device 328 is IPLed from the VIC circuit 100.
Signal, interrupt cycle signal from PIO address decoder 328, and IPL from address buffer 122.
A 4-bit address signal indicating the level is received. Device 3
28 is an interrupt request to the circuit 150 (int.req)
Generate an output signal consisting of

FIG. 11 shows the control circuits 150 and 194 in detail. The circuit 150 includes a command generator state machine unit 350 and a command sequencer state machine unit 352. Command generator 350 generates and formats the commands transferred over interconnect bus 46. The generator 350 loads the FIFO 140, controls the multiplexer 146 for PIO requests, generates a DMA ACK signal, and PIO request to DMA. It achieves the ability to generate and format commands to achieve arbitration control for ACKs. Device 350 is a PIO controller to PIO REQ
Signal, YA bus chip select (BUS CS) signal from address device 302, IVS chip select (CS) signal from address decoder 302, DMA controller 304
To DMA ACK signal to TURBO channel 26
To rdy in the form of rdy signal data rdy signal from the interrupt controller to INT REQ The ACK signal is sent from the protocol sequencer 356 to FAIL.
Receive the STATUS signal. The device 350 has a FIF
Request command and confirmation command to be stored in O140, mux control (con
16-bit data consisting of a control signal and a mux control signal for the multiplexer 146.

The command sequencer unit 352 manages the interconnect module 68 to ensure that the proper commands and data are being sent at all times. The device 352 is
It provides the ability to send signals to the interconnect bus 46, generate morphology and mask signals, and check sequences.
The device 352 receives the 16-bit data signal from line 141 and the four form and mask signals from FIFO 140 to fifo non-empty and from FIFO 140 to dma. rtn
The data ready signal is received. Device 352 provides the 3-bit form and mask (ta) provided to device 155.
m) Generate a signal. Device 352 includes internal flags A and D.

Circuit 194 includes a command decoder state machine unit 354 and a protocol chucker state machine unit 356. The command decoder unit 354 receives the message from the interconnect bus, validates it and loads the appropriate instruction, address and data into the FIFO. The command decoder device 354 interprets commands from the interconnection bus 46, detects errors such as incorrect commands, out-of-sequence operations, and parity errors, and outputs command, address, data, form and mask (tam) information to the FIFO. Achieve the ability to load and screen idle cycles. Command decoder device 35
The output from 4 is the signal provided to the FIFO 190, the purge complete signal provided to the command generator device 350,
And wen supplied to the FIFO circuit 190 fifo
Including signal.

Protocol Sequence Checker Device
356 pulls the command from the FIFO 190 and
Transaction machines 300, 304 and 306
Request a request. Is this device 356 an interconnect bus 46?
These commands are interpreted and the address for the DMA request operation is read.
Load information, DMA Generate REQ signal, DM
A write data is sent to the device 304 for PIO ACK signal
Is generated and PIO confirmation information is sent to the PIO controller 300.
Send, notify interrupt request (INTREQ), request error
Achieve the function of notifying. The input of the device 356 is FI
16-bit data from FO190 and FIFO190
Fifo from not Includes the empty signal. apparatus
The output from 356 is provided to the DMA controller 304.
DMA The REQ signal is supplied to the PIO controller 300
PIO Supplied to ACK signal and interrupt control signal 306
PIO Supply to ACK signal and interrupt control signal 306
INT REQ, devices 300, 304 and 350
To be supplied to STATUS signal and register
Latch address (latch) supplied to 94 add
r) contains the signal. (FIG. 3) FIG. 11 shows the appropriate signal technology.
Is used to control the control circuit 150 of modules 68 and 74 and
And 194 are shown. Pairs for modules 70 and 72
The corresponding circuit has an equivalent structure. But Naga
PIO and DMA technology for request and confirmation signals
To be rolled.

The preferred embodiment of the present invention employs a discrete circuit as described above. However, the system of the present invention provides an application specific integrated circuit (ASI).
C) Particularly suitable for implementation in the technology. For example, the functions of the host interface circuit 75 and the I / O interface circuit 76 can be implemented by different ASICs. Similarly, the functions of interconnect modules 68 and 74 (other than differential drivers) can be implemented in a single ASIC, similar to the functions of interconnect modules 70 and 72.

In the preferred embodiment, each unidirectional information path 52 and 54 comprises a single set of 16-bit data signals, although the invention is not so limited. In some applications, each unidirectional information path employs a group of multiple sets of multi-conductor path signals,
It is desired to achieve higher data rates.
In yet another embodiment, a high speed fiber optic data link is inserted between conductors 60 and 62 to provide long distance interconnection. For example, the model number GA9711 data link transmitter and the model number GA9012 data link receiver are Ga
It is commercially available from Zelle Corporation and can be inserted directly between connectors 61 and 62, creating a high speed long distance interconnect between a pair of information buses.

The bus of the present invention provides an apparatus and method for interconnecting first and second information buses in which a high data transfer rate is achieved. By using pseudo ECL technology,
Current spikes are avoided and electromagnetic interference is reduced. Similarly, the use of pseudo-ECL compatible voltage levels across twisted pair cables reduces the sensitivity of the system and counters the effects of noise. Moreover, the use of pairs of multi-conductor unidirectional information paths minimizes the number of signals required to interconnect the information buses, reducing cost and complexity.

It will be apparent to those skilled in the art that various modifications and variations can be made to the device and method of the present invention. Accordingly, the specification and drawings are intended for purposes of illustration only and the true scope and spirit of the invention is set forth in the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system, according to a preferred embodiment of the present invention, comprising a pair of information buses each having a plurality of components and connected by an interconnection system including a pair of adapters and an interconnection bus;

2 is a block diagram of a bus adapter and interconnect bus of the system of FIG.

3 is a detailed block diagram of an interface circuit of the first adapter of FIGS. 1 and 2;

FIG. 4 is a detailed block diagram of the interface circuit of the second adapter shown in FIGS. 1 and 2.

5 is a block diagram of an interconnect transmitter included in the adapter of FIGS. 3 and 4;

6 is a block diagram of an interconnect receiver included in the adapter of FIGS. 3 and 4;

FIG. 7 is an electrical schematic diagram showing respective termination circuits of the transmitter and receiver of FIGS. 5 and 6;

FIG. 8 is a timing diagram showing the timing relationships between the signals of the system shown in FIGS.

9 is a detailed block diagram showing the configuration of the control circuit of FIG.

10 is a detailed block diagram showing the configuration of the control circuit of FIG. 5, and

FIG. 11 is a detailed block diagram of the control circuit shown in FIGS. 5 and 6; 20 system 22, 24 subsystem 26 system bus 28 system module 30 memory 32 communication controller 34 small computer system interface 36 slot 40 interconnection device 42, 44 adapter module 46 interconnection bus 48 system bus 50 VME I / O board

 ─────────────────────────────────────────────────── ─── of the front page continued (72) inventor Richard E. Hadonoru United States, New Hampshire Nashua Juniper lane 15 (72) inventor Phillip G. hunt United States, New Hampshire hump Steed Emerson Abenyu over 80

Claims (16)

[Claims] 1. A device for interconnecting first and second information buses each having a plurality of data lines, the first and second multi-conductor unidirectional information paths each having a plurality of data signals. Groups, wherein the number of data signals on each information path is less than the number of data lines in at least one of the information buses, said first and second groups, a plurality of sets of data lines of a first information bus A first group of registers for respectively receiving a first group of sets of information from the first group of, a first group of registers via a data line of a first information path A first multiplexer for sequentially transferring each set of a first group of multiple sets of information from the first interconnect module, and a first interconnect module comprising a first connector coupled to the first multiplexer; From multiple sets of That one of the first set of group second
A second group of registers for respectively supplying one set of a second group of sets of data lines of the information bus, a second connector removably connected to the first connector, A first group of multiple sets of information coupled to the second connector and sequentially transferred by the first multiplexor, and a first group of multiple sets of information in the second group of registers. A second interconnect module consisting of a demultiplexer each supplying a group of data lines, a second group consisting of a plurality of sets of data lines of a second information bus to a second group consisting of a plurality of sets of information. A third group of registers for respectively receiving the sets, and sequentially transferring each set of the second group of multiple sets of information from the third group of registers via a data line of the second information path. Do A third interconnect module consisting of a second multiplexer connected to the second connector, and a first set of information from a first set of multiple sets of data lines of the first information bus. Receiving a fourth group of registers each for supplying one set of a second group of sets, a second group of sets of information sequentially transferred by a second multiplexer,
And a second group of multiple sets of information to a fourth register
Said device comprising a fourth interconnect module comprising a second demultiplexer means for supplying each of said groups. 2. A transfer of information from the first information bus to the second information bus and a transfer of information from the second information bus to the first information bus are received from the first and second information buses. The apparatus of claim 1, further comprising control means for initiating in response to the command. 3. First and second converters respectively connected to first and second multiplexers for converting a TTL compatible signal to a differential ECL compatible signal, respectively second and fourth groups of registers. Combined with EC
First and second ECL differential receivers for converting the L-compliant signal to a TTL-compliant signal, coupled to the first connector and the first multiplexer,
A first twisted pair cable, coupled to a second connector and a first ECL differential receiver, a second twisted hair cable, coupled to a second connector and a second multiplexer,
The apparatus of claim 1 comprising a third twisted pair cable, a fourth twisted pair cable coupled to the first connector and the second ECL differential receiver. 4. A device for interconnecting first and second information buses, each having a plurality of data lines, comprising:
The apparatus comprises first and second multi-conductor unidirectional information paths each having a plurality of data signals, wherein the number of data in each information path is greater than the number of data lines in at least one of the information buses. Fewer unidirectional information paths, a set of registers each receiving one of the first pair of sets of information appearing in the first pair of sets of data lines of the first information bus, A first of a plurality of sets of information from a first pair of registers via a data line
A first interconnect module comprising a first multiplexer for sequentially transferring each set of information pairs, a second set of information lines to a second set of data lines of a second information bus, A second pair of registers for respectively supplying one set of one pair, a second connector removably connected to the first connector, and a second connector coupled to and sequentially transferred by the multiplexer. A second interconnection module comprising first demultiplexer means for receiving the first pair of information sets and respectively supplying the first pair of information sets to the second pair of registers; A third pair of registers for receiving one of the second pair of sets of information appearing on the second pair of sets of data lines of the information bus, and a second connector, respectively. 2 emotions A third interconnect module comprising a second multiplexer for sequentially transferring one set of the second set of information from the third pair of registers across the data line of the path; Sequentially by a fourth pair of registers and a second multiplexer for respectively supplying one set of the first pair of sets of data lines of the information bus with one set of the second pair of sets of information A second demultiplexer coupled to the first connector for receiving a second pair of information sets to be transferred and respectively supplying the second pair of information sets to a fourth pair of registers. An apparatus comprising a fourth interconnection module comprising means. 5. Transfer from a first information bus to a second information bus and transfer from a second information bus to a first information bus,
The apparatus of claim 4 comprising control means for initiating in response to a command received from the first and second information buses. 6. A first twisted pair cable for connecting to a first connector, coupled between a first multiplexer and a first twisted pair cable for converting a TTL compliant signal to an ECL compliant differential signal. A first ECL differential conversion means, coupled to a second connector, coupled to second and third twisted pair cables, a second twisted pair cable of the resistor and a second pair of resistors, and having an ECL matching difference. Motion signal TTL
A first ECL differential receiver for converting to a compliant signal, a second ECL differential receiver for converting between a second multiplexer and a third twisted pair cable to convert a TTL compliant signal to an ECL compliant differential signal. ECL differential converter means, fourth twisted pair cable connected to the first connector, ECL compatible differential signal and TTL compatible signal connected between the fourth twisted pair cable and the fourth pair of resistors. The apparatus of claim 4 including a second ECL differential receiver for converting to. 7. A first and second clock signal having a first and a second clock rate, respectively, is provided to the first and second pairs of registers, respectively, to provide information to the first and third pairs of registers. The apparatus of claim 4 including means for storing. 8. Means for respectively transferring the first and second clock signals through the first and second information paths, and means for receiving the transferred clock signals, second and fourth registers. 8. The apparatus of claim 7 including means for latching information transferred to the second and fourth pairs of registers on both the rising and falling edges of the transferred clock signal in the pair of. 9. The means for providing first and second clock signals reduce the third and fourth clock signals to first and second clock speeds, respectively.
Frequency divider means for generating a clock signal and supplying the first and second clock signals respectively over the first and second information paths, and converting the first and second clock signals respectively, The clock signals provided to the second and fourth pairs of registers are transferred to transfer information from the second and fourth pairs of registers to the second and first information buses at third and fourth clock rates. 9. The apparatus of claim 8 comprising first and second clock multiplier means for transferring. 10. The means for providing first and second clock signals comprises a first 2: 1 divider circuit, a first delay circuit, and a first delay circuit and a first connector. A first clock signal ECL differential driver circuit for supplying the divided third clock signal to the first information path as an ECL compatible differential signal, A clock multiplier means is connected to the second connector and is connected to the first and second registers of the second register pair, respectively, and transfers the transferred first clock signal to a non-single-ended TTL compatible signal. Comprising first and second clock signal ECL differential receiver circuits that provide inverted and inverted transfer clock signals to the first and second registers of the second pair of registers and provide first and second clock signals. The above Stage further second 2: 1 divider circuit, the second delay circuit is connected between the second delay circuit and the second Kotakuta, 4th which is divided
A second clock signal ECL differential driver which supplies the second clock signal ECL as an ECL compatible signal to the second information path, wherein the second clock multiplier means is connected to the first connector and Of the fourth register pair are respectively coupled to the first and second registers of the fourth register pair as a non-inverted and inverted transfer clock signal comprising a single ended TTL compatible signal, respectively. 10. The apparatus of claim 9, comprising third and fourth clock signal ECL differential receiver circuits feeding a second register. 11. The apparatus of claim 10, wherein the first and second delay circuits have a delay period equal to half the period of the third and fourth clock signals. 12. The first clock signal ECL differential driver comprises a non-inverting output and an inverting output, and the first clock signal ECL differential receiver circuit comprises a first
A non-inverting input coupled to a non-inverting output of a first clock signal ECL differential driver circuit via the first information path, a first clock via the first information path, A second clock signal ECL differential receiver circuit comprising an inverting input coupled to a non-inverting output of a signal ECL differential driver circuit and an output coupled to a first register of a second pair of registers, , First
An inverting input coupled to a non-inverting output of a first clock signal ECL differential driver circuit via an information path of
A non-inverting input coupled to the inverting output of the first clock signal ECL differential driver circuit and an output coupled to the second register of the second pair of registers via said information path of Clock signal ECL differential driver comprises a non-inverting output and an inverting output, and a third clock signal ECL differential receiver circuit is coupled to the first clock signal ECL differential driver circuit via a second information path. A non-inverting input, an inverting input coupled to an inverting output of a second clock signal ECL differential driver circuit via a second information path, and a first register of a fourth pair of registers. A fourth clock signal ECL differential receiver circuit is coupled to the non-inverting output of the second clock signal ECL differential driver circuit via the second information path. , A non-inverting input coupled to the inverted output of the second clock signal ECL differential driver circuit via a second information path, and an output coupled to the second register of the fourth pair of registers. The device of claim 11, which comprises: 13. Means for receiving a block data read command from a second information bus, requesting data from the first information bus, and transferring the block data read command to the first information bus. A second block data read confirmation signal and the requested data in response to a block data read command from the second information bus in the second interconnect bus module.
Means for setting the block data read flag when the block data read confirmation signal is sent, and the first information bus when the block data read flag is set in the first interconnection module. Means for preventing a command from being received from the second interconnect module, temporarily storing data received in response to a block data read command, and purging the storage means being completed, The apparatus of claim 4 including means for sending a purge complete command to the fourth interconnect module, and means for resetting a block data read flag when the purge complete command is received by the fourth interconnect module. . 14. A data transfer command is received from a second information bus, the data transfer command is transferred to the first information bus via the second information path, and the data transfer flag is transferred when the data transfer command is transferred. And preventing the command received by the third interconnect module from the second information bus when the data transfer flag is set from being transferred via the second information path. Means for generating a data transfer confirmation signal in response to a data transfer command being received by the fourth interconnection module and transmitting the data transfer confirmation signal to the second interconnection module; and a second interconnection module. 5. The apparatus of claim 4, including means for resetting a data transfer flag when a data transfer confirmation signal is received by. 15. A method of interconnecting first and second information buses each having a plurality of data lines over first and second multi-conductor unidirectional information paths each having a plurality of data signals. , A method in which the number of data signals in each information path is less than the number of data lines in at least one of the information buses is such that a set of information from a first pair of data lines of a first information bus is Receiving a first pair in each of the first pair of registers and activating a first multiplexer to transfer the set of information from the first pair of registers via the data lines of the first information path. Sequentially transferring each set of the first pair, receiving in the second pair of registers, respectively, the first pair of sets of information sequentially transferred by the first multiplexer, from the second pair of registers. The first pair of information to the second
Simultaneously supplying respectively to the second pair of the information bus data line sets, the second pair of information sets from the second pair of the second information bus data line sets to the third register set. , Respectively, and actuating a second multiplexer to sequentially transfer each set of the second set of information from the third pair of registers via the data lines of the second information path. And in a fourth pair of registers, receiving a second pair of information sequentially transferred by the second multiplexer,
A method comprising simultaneously supplying a second pair of information sets to a first pair of data line sets of a first information bus, respectively. 16. A device for transferring data between a first and a second information bus, an interconnect bus, means for collecting data transferred via the interconnect bus, an interconnect bus at a predetermined data rate. Means for transferring data through the interconnect bus at a clock rate of half the data rate, means for transferring a strobe signal having a rising edge and a falling edge, transferred through the interconnect bus Means for receiving the transferred data, having means for receiving the transferred strobe signal and latching the transferred data in the receiving means at both the rising and falling edges of the transferred strobe signal. , The device wherein data is received over the interconnect bus at double the strobe speed.