JP2011142525A - Data transfer device, data transfer system, data transfer method, data transfer program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relate to a data transfer device, a data transfer system, a data transfer method, a data transfer program, and a recording medium which simultaneously transfer the same data inside a memory to a plurality of slave devices. <P>SOLUTION: In a printer device 1, when a DFE 2 transfers transfer data in the memory 12 to printer engines 3a and 3b which are a plurality of transfer destinations, frame data of the transfer data read out from the memory 12 is distributed, for as many as transfer destinations of the data by a distribution circuit 23, and the distributed frame data is simultaneously sent to a plurality of printer engines 3a and 3b from a first sending port 4a and a second sending port 4b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data transfer device, a data transfer system, a data transfer method, a data transfer program, and a recording medium, and more particularly, a data transfer device and a data transfer system that simultaneously transfer the same data in a memory to a plurality of destination devices. The present invention relates to a data transfer method, a data transfer program, and a recording medium.

  In a device that transfers a large amount of data in a memory to a node that is a plurality of engine units, such as a printer device that forms a high-definition image on a wide sheet-like member, print data sent from a host device The RIP (Raster Image Processor) is developed on a memory by a front-end server or the like, and the image data developed on the memory is transferred to a printer engine, an image inspection apparatus, or the like.

  In such data transfer, conventionally, a bus connection method, a crossbar switch connection method, a LAN (Local Area Network), an optical fiber, or the like has been used as a method of transferring signals and data between the transmission side and the reception side. A network connection method is used.

  Conventionally, when one master device 100 transfers data “AA” and “BB” read from the memory 101 to the slave device 110 and the slave device 111 as shown in FIG. The data is transferred to the slave devices 110 and 111 via the data control circuit 102 including the CPU, chip set, and input / output port. In this case, the data “AA” and “BB” stored in the memory 101 are read out, the data “110AA” and “110BB” are read out for the slave device 110, and the data “111AA” and data “110” are read out for the slave device 111. 111BB "is read out and transferred to the data control circuit 102. From the data transfer circuit 102, the data" 110AA "and data" 110BB "are transferred to the slave device 110, and the data" 111AA "and data" 111BB "are transferred to the slave device 111 sequentially. Send.

  That is, the master device 100 reads data “AA” and “BB” from the memory 101 for the slave device 110 and the slave device 111, respectively, in order to transfer image data to the slave device 110 and the slave device 111 in order. The data control circuit 102 sequentially transfers the data to the slave device 110 and the slave device 111. As a result, as shown in FIG. 9, when the access time (read time) to the memory 101 for data acquisition is T, the data “AA” and the data “BB” are stored in the memory for each of the slave devices 110 and 111. When the memory 101 is accessed to obtain the information by accessing the memory 101, the access time to the memory 101 is 4T hours.

  If data is transferred to multiple slave devices by performing access to the memory as many as the number of slave devices for each data, data transfer is performed when the number of slave devices is small and the data transfer size is small. However, if a large amount of data is transferred to multiple slave devices within a short period of time, such as a high-speed printer device or a wide-width printer device, the data In order to improve the transfer speed, there was a need for improvement.

  Conventionally, when data is transferred from a master node to a plurality of slave nodes via a high-speed serial transmission path, in order to smooth the synchronization timing at the start of data transmission / reception between both nodes, A technique using a timing adjustment sequence that is slower than data transmission is disclosed (see Patent Document 1).

  However, in the prior art described in the above publication, since timing adjustment is performed using a timing adjustment sequence that is slower than data transmission, synchronization can be appropriately performed. Even when data is transmitted to the slave nodes, it is necessary to read out data from the memory by the number of slave nodes to be transmitted and sequentially transmit the data, resulting in poor transfer efficiency. Further, in the conventional data transfer, when an error occurs in data transfer, retry processing is performed to quickly transfer the same data. Therefore, it is desired to improve transfer efficiency when a transfer error occurs.

  Therefore, the present invention provides a data transfer apparatus, a data transfer system, a data transfer method, a data transfer program, and a data transfer apparatus that efficiently and at high speed perform data transfer processing when transferring the same transfer target data on a memory to a plurality of transmission destinations. The object is to provide a recording medium.

  In order to achieve the above object, according to the present invention, when transferring the transfer target data in the memory to a plurality of transmission destinations, the block data of the transfer target data read from the memory is set to the number of transfer destinations of the data. The distributed block data is transmitted to each of the plurality of transmission destinations.

  Further, the present invention may be characterized in that information relating to the transfer of the transfer target data is generated as transfer information, and the generated transmission information is transmitted to each of the transmission destinations prior to transmission of the transfer target data.

  Further, according to the present invention, when there is a retransmission request specifying the block data of the transfer target data from the transmission destination, the block data specified in the retransmission request among the transfer target data is read from the memory. It may be characterized by transmitting to the transfer destination.

  Further, the present invention may be characterized in that it has a double transmission configuration in which the same block data is transmitted twice for each transmission destination.

  ADVANTAGE OF THE INVENTION According to this invention, the data transfer process in the case of transferring the same transfer object data on memory to several transmission destinations can be performed efficiently and at high speed.

1 is a block diagram of a main part of a printer apparatus to which a first embodiment of the present invention is applied. The circuit block diagram of a distribution circuit. The sequence diagram which shows a data transfer process. Explanatory drawing of the data transfer from DFE to a printer engine. Explanatory drawing of the data transfer in 1st Example. Explanatory drawing of the data reading time in the data transfer of FIG. The principal part block block diagram of the printer apparatus of 2nd Example. Explanatory drawing of the data transfer in the conventional data transfer system. Explanatory drawing of the data reading time in the conventional data transfer system of FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 6 are diagrams showing a first embodiment of a data transfer device, a data transfer system, a data transfer method, a data transfer program, and a recording medium according to the present invention. FIG. 1 shows a data transfer device according to the present invention, 1 is a block diagram of a main part of a printer apparatus 1 to which a first embodiment of a data transfer system, a data transfer method, a data transfer program, and a recording medium is applied.

  In FIG. 1, a printer apparatus (data transfer system) 1 includes a DFE (Digital Front End Saber) 2 as a data transfer apparatus, printer engines 3a and 3b as a plurality of transfer destination apparatuses, and the like (not shown). , An operation display unit, a paper feeding unit, a paper discharge unit, a communication interface, and the like. The communication interface transmits print data and print information to the printer device 1 via a dedicated line or a LAN to send a print request. A host device such as a computer to be connected is connected.

  The DFE 2 includes a CPU (Central Processing Unit) 11, a memory 12, a data control circuit 13, and first transmission ports 4a, second transmission ports 4b, and first transmission / reception ports 5a corresponding to the number of printer engines 3a and 3b that are transfer destination devices. The second transmission / reception port 5b is provided, and the data control circuit 13 is provided with a DMAC (Direct Memory Access Controller) 21, a bus 22, a distribution circuit 23, and the like.

  The printer engines 3a and 3b include reception ports 31a and 31b, transmission and reception ports 32a and 32b, CPUs 33a and 33b, data control circuits 34a and 34b, memories 35a and 35b, and a predetermined image forming method ( For example, it includes an engine main body that forms an image on a sheet (sheet-like member) by an electrophotographic method, an ink jet method, and the like, a paper supply unit that supplies paper to the engine main body, and the like, and the data control circuits 34a and 34b respectively Check circuits 36a and 36b are provided.

  The DFE 2 receives print data and print information from the host device, performs RIP (Raster Image Processor) processing on the print data under the control of the CPU 11, and stores the processed data (drawing data) on the memory 12. Store.

  For example, a RAM (Random Access Memory) or the like is used as the memory 12. The drawing data (transfer target data) developed by the RIP process, the transfer information related to the drawing data, and the DMA (Direct Memory) of the drawing data are used. Access) The descriptor used for transfer is written by the CPU 11.

  In the data control circuit 13, the memory 12 is connected to a bus 22, and a distribution circuit 23 as distribution means and a first transmission / reception port 5a and a second transmission / reception port 5b as transmission means are connected to each other. The circuit 23 is connected to the first transmission port 4a and the second transmission port 4b.

  The first transmission port 4a and the second transmission port 4b are dedicated transmission ports, and are connected to the reception port 31a of the printer engine 3a and the reception port 31b of the printer engine 3b, respectively. The first transmission port 4 a and the second transmission port 4 b read the drawing data read from the memory 12 by the DMAC (reading means) 21, added with check digit information, etc., and sent via the distribution circuit 23. , Respectively, to the reception ports 31a and 31b of the corresponding printer engines 3a and 3b.

  The first transmission / reception port 5a and the second transmission / reception port 5b are bidirectional ports, and transmit the print information received from the memory 12 via the bus 22 to the transmission / reception ports 32a, 32b of the corresponding printer engines 3a, 3b. Information received from the transmission / reception ports 32a and 32b, for example, error information is received. The first transmission / reception port 5a and the second transmission / reception port 5b function as transmission / reception means by passing information sent from the printer engine 3a or the printer engine 3b to the CPU 11 via the bus 22.

  The distribution circuit 23 has a circuit configuration as shown in FIG. 2, for example, and connects the first switch 23a, the bus 22, and the second transmission port 4b for connecting / disconnecting the bus 22 and the first transmission port 4a. / The 2nd switch 23b which performs isolation | separation is provided. The first switch 23a and the second switch 23b are, for example, semiconductor MOS (Metal Oxide Semiconductor) switches, gate switches, driver ICs (Integrated Circuits), registers, etc., and are turned on / off under the control of the CPU 11. The output of the data read from the memory 12 is permitted / prohibited to the first transmission port 4a and the second transmission port 4b. That is, the CPU 11 turns on the first switch 23a and the second switch 23b when transmitting the same data to the printer engines 3a and 3b, and transmits data only to either the printer engine 3a or the printer engine 3b. The switches 23a and 23b on the printer engine 3a and 3b side that transmit data are turned on, and the switches 23a and 23b on the printer engine 3a and 3b side that do not transmit data are turned off.

  In transferring the drawing data stored in the memory 12 to the printer engines 3a and 3b, the CPU (control means) 11 first transfers transfer information relating to drawing data to be transferred, such as job information, paper size information, and data. Print information such as quantity information is transmitted to the corresponding printer engines 3a and 3b using the first transmission / reception port 5a and the second transmission / reception port 5b. After that, a descriptor is prepared in the memory 12, and the DMAC 21 Drawing data and a check digit used for error checking of the drawing data are transmitted from the memory 12 to the printer engines 3a and 3b using the transmission ports 4a and 4b.

  When the transmission information transmitted from the transmission / reception ports 5a and 5b of the DFE 2 is received by the transmission / reception ports 32a and 32b prior to reception of the drawing data, the printer engine 3a and the printer engine 3b receive a CPU (control unit). 33a and 33b hold the transfer information in a register (not shown) in the CPU 33a and 33b, and then wait for the reception ports (reception means) 31a and 31b to receive the drawing data transmitted from the DFE2. .

  When the receiving ports 31a and 31b receive the drawing data, the printer engines 3a and 3b store the drawing data in the memories 35a and 35b via the check circuits (error check means) 36a and 36b of the data control circuits 34a and 34b. When an error is detected in the drawing data by 36a and 36b, the number of bytes in which the error has occurred in the received drawing data without stopping the data transfer and performing the data transfer again as in the prior art. The CPU 33a, 33b obtains error information (error frame information) indicating at which frame an error has occurred and stores it in an internal register (error information storage means), etc., and reception of all drawing data has been completed. Thereafter, the error information (error frame information) stored in the internal register or the like is sent to the transmission / reception ports 32a and 32b. Through, and transmits it to the DFE2. As this error check, for example, a normal error check using the check digit information can be used.

  When the first transmission / reception port 5a and the second transmission / reception port 5b receive error information from the printer engines 3a and 3b, the CPU 11 reads the drawing data (frame data) of the frame in which the error has occurred from the memory 12 and transmits / receives it. When the drawing data is retransmitted, the CPU 33a, 33b of the printer engine 3a, 3b retransmits the drawn drawing data to the corresponding one of the memories 35a, 35. Overwrite the data area and correct it.

  Since the drawing data in which the error has occurred is retransmitted only to the printer engines 3a and 3b in which the error has occurred, the transmission path between the transmission / reception ports 5a and 5b and the transmission / reception ports 32a and 32b without using the distribution circuit 23. Do through.

  The printer 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), a DVD ( A data transfer program for executing the data transfer method of the present invention recorded on a computer-readable recording medium such as a digital versatile disk (SD), a secure digital (SD) card, or an MO (Magneto-Optical Disc) is read and the DFE2 A data transfer method for transferring drawing data, which will be described later, efficiently and at a high speed by being introduced into a ROM or the like read by the CPU 11 or introduced into a ROM or the like read by the CPUs 33a and 33b of the printer engines 3a and 3b. It is built as a data transfer system. This data transfer program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. Can be distributed.

  Next, the operation of this embodiment will be described. The printer apparatus 1 according to the present embodiment efficiently and rapidly transfers data from the DFE 2 that is a data transfer apparatus to the printer engines 3a and 3b that are transfer destination apparatuses. Hereinafter, a case where the same drawing data is transferred from the memory 12 of the DFE 2 to the printer engines 3a and 3b and print processing is performed by the printer engines 3a and 3b will be described with reference to FIGS. 3 and 4 show only the processing steps when transferring from the DFE 2 to the printer engine 3a for clarity of explanation, the same applies to the printer engine 3b from the DFE 2. .

  That is, as shown in FIG. 3, when printing the print data received from the host device, the printer device 1 develops the print data into drawing data (RIP processing) by the CPU 11 of the DFE 2 and stores it in the memory 12. As shown in FIG. 4, the CPU 11 further transfers transfer information of drawing data as the print data, for example, print information (transfer information) such as job information, paper size information, and data amount information to the first transmission / reception port 5a and The data is transmitted from the second transmission / reception port 5b to the transmission / reception ports 32a, 32b of the printer engines 3a, 3b.

  As shown in FIG. 3, when the transmission / reception ports 32a and 32b receive the print information, the printer engines 3a and 3b send the print information to the CPUs 33a and 33b, and the CPUs 33a and 33b store the received print information in an internal register. The receiving ports 31a and 31b are set as the drawing data receiving ports, and the receiving ports 31a and 31b wait for the drawing data to be received. Further, as shown in FIGS. 3 and 4, the CPUs 33a and 33b of the printer engines 3a and 3b send a reception notification that the print information has been received from the transmission / reception ports 32a and 32b to the first transmission / reception port 5a and the second transmission / reception port of the DFE2. Send to port 5b.

  When the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE 2 receive the reception notification of the print information, as shown in FIG. 3 and FIG. 4, the reception communication is sent to the CPU 11, and the CPU 11 sends all the drawing data. When the reception notification is received from the destination, the DMAC 21 is set for DMA transfer (the start address of the transfer target data on the memory 12, the data amount, etc. are set in the descriptor on the memory 12), and the DMA transfer is set. When completed, the DMAC 21 starts DMA transfer. When the DMAC 21 is instructed to start DMA transfer, as shown in FIGS. 3 and 4, the DMAC 21 reads the descriptor of the memory 12, and draws the drawing data stored in the descriptor address from the memory 12 in packet units (block units). , Frame by frame). The DMAC 21 adds a check digit to the same drawing data that has been read, and divides and passes the same drawing data to the first transmission port 4a and the second transmission port 4b by the distribution circuit 23 through the bus 22, and the first transmission port 4a. Are simultaneously transmitted from the second transmission port 4b to the reception port 31a of the printer engine 3a and the reception port 31b of the printer engine 3b.

  When the reception ports 31a and 31b receive the drawing data, the printer engines 3a and 3b use the check digit in the check circuits 36a and 36b of the data control circuits 34a and 34b as shown in FIGS. The drawing data is checked for errors, the checked drawing data is stored in the memories 35a and 35b, and the drawing data check result is stored in the internal registers of the CPUs 33a and 33b.

  That is, during the data transfer, when the check circuits 36a and 36b detect that a transfer error has occurred in the drawing data (print data), in the prior art, the data transfer is stopped when the error is detected. In this case, in the printer apparatus 1 of this embodiment, the CPU 33a and 33b store the location where an error has occurred (error information indicating what byte the error has occurred) in an internal register or the like. Then, after all data transfer is completed, an error handling process is performed as described later.

  That is, when the CPUs 33a and 33b of the printer engines 3a and 3b refer to the print information received first and stored in the register and determine that all drawing data has been received and stored in the memories 35a and 35b, Referring to the internal register, as shown in FIG. 3, it is checked whether an error has occurred in receiving drawing data. When no error has occurred, data transfer has been completed normally as shown in FIG. A normal end notification to the effect is transmitted from the transmission / reception ports 32a and 32b to the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE2. When receiving the normal end notification, the first transmission / reception port 5a and the second transmission / reception port 5b pass the normal end notification to the CPU 11 and end the processing. When the error information is written by referring to the check result information of the internal register, the CPUs 33a and 33b of the printer engines 3a and 3b, as shown in FIG. 3 and FIG. Byte information etc.) is transmitted from the transmission / reception ports 32a, 32b to the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE2. When the first transmission / reception port 5a and the second transmission / reception port 5b receive the error information, the first transmission / reception port 5a and the second transmission / reception port 5b pass the error information to the CPU 11. The CPU 11 refers to the error information and the error-generated data in the drawing data of the memory 12 Read part. The CPU 11 transmits the drawing data of the error occurrence portion read from the memory 12 as retransmission information from the first transmission / reception ports 5a, 5b to the transmission / reception ports 32a, 32b of the printer engines 3a, 3b.

  Upon receiving the retransmission information, the transmission / reception ports 32a and 32b of the printer engines 3a and 3b pass the received retransmission information to the CPUs 33a and 33b, and the CPUs 33a and 33b store them in the memories 35a and 35b by using the drawing data that is the received retransmission information. Overwrite the corresponding data portion of the rendered data and save it.

  In other words, as illustrated in FIG. 5, in the printer device 1, the DFE 2 that is the master node is, for example, the same drawing data “AA” and “BB” stored in the memory 12 as two transfer destination devices. When transferring to the printer engines 3a and 3b, the drawing data “AA” and “BB” to be transferred are read from the memory 12 only once, sent to the data control circuit 13, and the same drawing is performed by the distribution circuit 23 of the data control circuit 13. The data “AA” and “BB” are divided and passed to the first transmission port 4a and the second transmission port 4b, and the same from the first transmission port 4a and the second transmission port 4b to the printer engine 3a and the printer engine 3b, respectively. The drawing data “AA” and “BB” are transferred.

  Therefore, as shown in FIG. 6, when it takes only the read time T to read the drawing data “AA” and the drawing data “BB” from the memory 12 respectively, the transfer target to be transferred to two transfer destinations with the read time of 2T. The drawing data “AA” and the drawing data “BB” can be read out, and the data can be read in half the time shown in FIG. The effect of shortening the reading time increases as the number of transfer destinations of drawing data read from the memory 12 increases.

  As described above, when the DFE 2 that is the data transfer device transfers the transfer target data on the memory 12 to the printer engines 3a and 3b that are a plurality of transmission destinations, the printer device 1 according to the present embodiment reads the data from the memory 12. The output frame data of the transfer target data is distributed to the number of transfer destinations of the data by the distribution circuit 23, and the distributed frame data is respectively transmitted from the first transmission port 4a and the second transmission port 4b to a plurality of printer engines 3a. 3b.

  Therefore, regardless of the number of data transfer destinations to which the same data is transferred, the number of times the data is read from the memory can be reduced to one to improve the transfer efficiency, and the data reading time and thus the total amount of data required for data transfer can be improved. Processing time can be shortened.

  Also, in the printer apparatus 1 of this embodiment, the DFE 2 generates print information that is transfer information for information related to transfer of transfer target data, and the print information is transmitted / received ports 5a and 5b different from the transmission ports 4a and 4b. To the printer engines 3a and 3b prior to transmission of the transfer target data.

  Therefore, it is possible to notify the transfer destination in advance of information related to the transfer of the data to be transferred, so that appropriate transfer data can be managed, and data transfer can be made appropriate.

  Further, when the DFE 2 receives a retransmission request specifying the frame data of the transfer target data from the printer engines 3a and 3b that are the transmission destinations, the printer apparatus 1 according to the present embodiment includes the retransmission request among the transfer target data. In response to this, the designated frame data is read from the memory 12 and transmitted from the transmission / reception ports 5a and 5b to the printer engines 3a and 3b.

  Therefore, when a transfer error occurs as in the prior art, only the frame data in which an error has occurred can be retransmitted after all the data transfer has been completed without performing the data transfer again when the error occurs. In addition, the processing efficiency of data transfer can be improved and data can be transferred reliably.

  FIG. 7 is a block diagram of the essential parts of a printer apparatus 100 to which a second embodiment of the data transfer apparatus, data transfer system, data transfer method, data transfer program, and recording medium of the present invention is applied.

  The present embodiment is applied to a printer apparatus similar to the printer apparatus 1 of the first embodiment. In the description of the present embodiment, the same components as those of the first embodiment are the same. The description will be omitted or simplified with reference numerals.

  In FIG. 7, the printer apparatus 100 includes a DFE 101 as a data transfer apparatus, two printer engines 102 a and 102 b as a plurality of transfer destination apparatuses, and an operation display unit, a sheet feeding unit, a discharge unit, and the like. A paper unit, a communication interface, and the like are provided, and a host device such as a computer that transmits print data and print information to the printer apparatus 100 via a dedicated line or a LAN to make a print request is connected to the communication interface. .

  The DFE 101 includes a CPU 11, a memory 12, a data control circuit 110, and first transmission ports 4aa, 4ab, second transmission ports 4ba, 4bb, which are transmission means corresponding to the number of printer engines 102a, 102b as transfer destination apparatuses, and transmission / reception means. A first transmission / reception port 5a, a second transmission / reception port 5b, and the like are provided. The data control circuit 110 includes a DMAC 21, a bus 22, a distribution circuit 111, and the like.

  The printer engines 102a and 102b include reception ports 31a and 31b as reception units, transmission and reception ports 32a and 32b as transmission / reception units, CPUs 33a and 33b, data control circuits 120a and 120b, memories 35a and 35b, and the like. And an engine body that forms an image on a sheet (sheet-like member) by a predetermined image forming system (for example, an electrophotographic system or an inkjet system), a paper supply unit that supplies the paper to the engine body, etc. The control circuits 120a and 120b include buffers 121aa, 121ab, 121ba, and 121bb, check circuits 122aa, 122ab, 122ba, and 122bb, selectors 123a and 123b, internal buses 124a and 124b, and transfer data frame counters 125a and 125, respectively. And transfer information register 126a, and a 126b, and the like.

  Similar to DFE 2 of the first embodiment, the DFE 101 receives print data and print information from the host device, performs RIP processing on the print data under the control of the CPU 11, and performs post-processing data (drawing data). Is stored on the memory 12.

  In the data control circuit 110, the memory 12 is connected to the bus 22, and the distribution circuit 111 is connected to the first transmission / reception port 5 a and the second transmission / reception port 5 b outside the data control circuit 110. Are connected to the first transmission ports 4aa, 4ab and the second transmission ports 4ba, 4bb.

  The first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb are dedicated transmission ports, and are connected to the reception ports 31aa and 31ab of the printer engine 3a and the reception ports 31ba and 31bb of the printer engine 3b, respectively. The first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb are read out from the memory 12 by the DMAC 21, added with check digit information and the like, and the drawing data sent through the distribution circuit 111 The data is transmitted to the reception ports 31aa and 31ab of the corresponding printer engine 3a and the reception ports 31ba and 31bb of the printer engine 3b, respectively.

  The first transmission / reception port 5a and the second transmission / reception port 5b are bidirectional ports, and transmit the print information received from the memory 12 via the bus 22 to the transmission / reception ports 32a and 32b of the corresponding printer engines 102a and 102b, respectively. Information received from the transmission / reception ports 32a and 32b, for example, error information is received. The first transmission / reception port 5a and the second transmission / reception port 5b pass information sent from the printer engine 3a or the printer engine 3b to the CPU 11 via the bus 22.

  Although not shown, the distribution circuit (distribution means) 111 has the same configuration as the distribution circuit 23 of the first embodiment, and includes a first switch that connects / disconnects the bus 22 and the first transmission ports 4aa, 4ab. A second switch for connecting / disconnecting the bus 22 to / from the second transmission ports 4ba and 4bb is provided, and the first switch and the second switch are, for example, semiconductor MOS switches, as in the first embodiment. A gate switch, a driver IC, a register, or the like is used. Under the control of the CPU 11, the distribution circuit 111 turns on and off the first switch and the second switch, and the first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb of the drawing data read from the memory 12 Enable / disable output to. That is, the CPU 11 turns on the first switch and the second switch when transmitting the same data to the printer engines 102a and 102b, and transmits the drawing data only to either the printer engine 102a or the printer engine 102b. Turn on the first switch or the second switch on the side of the printer engine 102a, 102b that transmits the drawing data, and turn off the first switch or the second switch on the side of the printer engine 102a, 102b that does not transmit the drawing data. .

  As described above, in the printer apparatus 100, the drawing data transmission path from the DFE 101 to each of the printer engines 102a and 102b is received by the first transmission ports 4aa and 4ab, the reception ports 31aa and 31ab, and the second transmission ports 4ba and 4bb. Duplexed by ports 31ba and 31bb.

  In transferring the drawing data stored in the memory 12 to the printer engines 102a and 102b, the CPU 11 first sends print information, which is transfer information relating to drawing data to be transferred, to the first transmission / reception port 5a and the second transmission / reception port. 5b is transmitted to the corresponding printer engine 102a, 102b, and then a descriptor is prepared in the memory 12, and the DMAC 21 uses the drawing data from the memory 12 and a check digit used for an error check of the drawing data, The first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb are used for transmission to the printer engines 102a and 102b.

  When the printer engine 102a and the printer engine 102b receive the print information transmitted from the transmission / reception ports 5a and 5b of the DFE 101 prior to reception of the drawing data, the CPUs 33a and 33b receive the transfer information. The data is held in a register (not shown) in the CPUs 33a and 33b, and thereafter, the reception ports 31aa and 31ab and the reception ports 31ba and 31bb wait for the drawing data transmitted from the DFE 101 to be received.

  When the reception ports 31aa and 31ab and the reception ports 31ba and 31bb receive the drawing data, the printer engines 102a and 102b temporarily send the drawing data to the buffer 121aa and the buffer 121ab of the data control circuit 120a and the buffer 121ba and the buffer 121bb of the data control circuit 120b. The check circuit 122aa and 122ab and the check circuits 122ba and 122bb check whether or not there is an error in the drawing data of the buffers 121aa and 121ab and the buffers 121ba and 121bb.

  In the data control circuit 120a, when there is no error in any of the drawing data in the buffer 121aa and the buffer 121ab, the selector 123a selects a preset buffer, for example, drawing data (data frame) of the buffer 121aa and selects the bus. If the CPU 33a stores it in a predetermined area of the memory 35a and there is an error in one of the drawing data in the buffer 121aa and the buffer 121ab, the selector 123a determines that the error has not occurred. Drawing data is selected and sent to the memory 35a via the bus 124a, and the CPU 33a stores it in a predetermined area of the memory 35a. When an error occurs in any of the drawing data in the buffer 121aa and the buffer 121ab, the data control circuit 120a discards the drawing data in the buffers 121aa and 121ab and stops storing the drawing data in the memory 35a. At the same time, the value of the transfer data frame counter 125a is stored in the transfer information register 126a as abnormal frame number information.

  Similarly to the data control circuit 120a, the data control circuit 120b selects normal drawing data from the buffer 121ba and the buffer 121bb by the selector 123b and stores the selected drawing data in the memory 35b, and the drawing data in either the buffer 121ba or the buffer 121bb. When an error has occurred, the drawing data in the buffers 121ba and 121bb are discarded, the storage of the drawing data in the memory 35b is stopped, and the value of the transfer data frame counter 125b is transferred as the abnormal frame number information. Store in the register 126b.

  When all the drawing data is transferred from the DFE 101, the printer engines 102a and 102b check whether the abnormal frame number information is stored in the transfer information registers 126a and 126b, and the abnormal frame number information. Is transferred to the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE 101 via the transmission / reception ports 32a and 32b, and processing for prompting retransmission of only the drawing data (frame data) of the frame is performed. .

  When the first transmission / reception port 5a and the second transmission / reception port 5b receive the abnormal frame number information as error information from the printer engines 102a and 102b, the DFE 101 causes the CPU 11 to display drawing data in which an error has occurred (drawing data of the frame of the abnormal frame number). ) From the memory 12 and retransmitted from the transmission / reception ports 5a and 5b to the printer engines 102a and 102b. When the drawing data is retransmitted, the CPUs 33a and 33b of the printer engines 102a and 102b retransmit the drawing. The data is overwritten and corrected in the corresponding data area of the memories 35a and 35.

  Next, the operation of this embodiment will be described. The printer apparatus 1 of this embodiment improves the transfer processing speed by transferring the drawing data via the duplexed transmission path.

  That is, the printer apparatus 100 develops the print data received from the host apparatus into drawing data by the CPU 11 of the DFE 101 (RIP processing) and stores the drawing data in the memory 12, and the CPU 11 further transfers the drawing data transfer information (printing information). ) Is transmitted from the first transmission / reception port 5a and the second transmission / reception port 5b to the transmission / reception ports 32a, 32b of the printer engines 102a, 102b.

  When the transmission / reception ports 32a and 32b receive the print information, the printer engines 102a and 102b send the print information to the CPUs 33a and 33b, and the CPUs 33a and 33b store the received print information in internal registers and receive them as drawing data reception ports. The ports 31aa and 31ab and the reception ports 31ba and 31bb are set, and the reception ports 31aa and 31ab and the reception ports 31ba and 31bb wait for reception of drawing data. Further, the CPUs 33a and 33b of the printer engines 102a and 102b transmit a reception notification that the print information has been received from the transmission / reception ports 32a and 32b to the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE 101.

  When the first transmission / reception port 5a and the second transmission / reception port 5b of the DFE 101 receive the reception notification of the print information, the first transmission / reception port 5a and the second transmission / reception port 5b send the reception notification to the CPU 11, and the CPU 11 receives the reception notification from all the transmission destinations of the drawing data. When the DMA transfer setting is completed and the DMA transfer setting is completed, the DMAC 21 starts the DMA transfer. When instructed to start DMA transfer, the DMAC 21 reads the descriptor of the memory 12 and reads the drawing data stored at the descriptor address from the memory 12 in units of packets. The DMAC 21 adds a check digit to the same drawing data that has been read, and distributes the same drawing data to the first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb via the bus 22 by the distribution circuit 111. Transmission is simultaneously performed from the first transmission ports 4aa and 4ab and the second transmission ports 4ba and 4bb to the reception ports 31aa and 31ab of the printer engine 102a and the reception ports 31ba and 31bb of the printer engine 102b.

  When the receiving ports 31aa and 31ab and the receiving ports 31ba and 31bb receive the drawing data, the printer engines 102a and 102b temporarily send them to the buffers 121aa and 121ab of the data control circuits 120a and 120b and the buffers 121ba and 121bb of the data control circuit 120b. The corresponding check circuits 122aa and 122ab and check circuits 122ba and 122bb check whether there is an error in the drawing data of the buffers 121aa and 121ab and the buffers 121ba and 121bb. The data control circuit 120a and the data control circuit 120b are configured such that when there is no error in any of the drawing data in the respective buffers 121aa and 121ab and the buffers 121ba and 121bb, the selectors 123a and 123b The drawing data (data frame) of 121aa and 121ba are selected and sent to the memories 35a and 35b via the buses 124a and 124b, and the CPUs 33a and 33b store them in predetermined areas of the memories 35a and 35b, and the buffers 121aa and 121ab or If there is an error in the drawing data in either the buffer 121ba or the buffer 121bb, the selectors 123a and 123b select the drawing data in which no error has occurred and select the drawing data via the buses 124a and 124b. Li 35a, sent to 35b, CPU 33a, 33b is stored in a predetermined area of the memory 35a, 35b. Further, the data control circuits 120a and 120b store the drawing data in the buffers 121aa and 121ab and the buffers 121ba and 121bb when an error has occurred in any of the drawing data in the buffer 121aa and the buffer 121ab or the buffer 121ba and the buffer 121bb. Discard it, stop storing the drawing data in the memories 35a and 35b, and store the values of the transfer data frame counters 125a and 125b in the transfer information registers 126a and 126b as abnormal frame number information.

  That is, when the check circuits 122aa and 122ab and the check circuits 122ba and 122bb detect that a transfer error has occurred in the drawing data (print data) during the data transfer using the duplexed transmission path, the location where the error occurs (Error frame number information indicating at which byte an error has occurred) is stored in the transfer information registers 126a and 126b, and after all the data transfer is completed, an error handling process is performed as described later.

  That is, when the CPUs 33a and 33b of the printer engines 102a and 102b refer to the print information received first and stored in the register and determine that all drawing data has been received and stored in the memories 35a and 35b, It is checked whether or not abnormal frame number information is stored in the transfer information registers 126a and 126b. If abnormal frame number information is stored, the first transmission / reception port 5a and the second transmission / reception port of the DFE 101 are transmitted via the transmission / reception ports 32a and 32b. A process of forwarding to the port 5b and prompting retransmission of only the drawing data of the frame is performed.

  When the first transmission / reception port 5a and the second transmission / reception port 5b receive the abnormal frame number information as error information from the printer engines 102a and 102b, the DFE 101 causes the CPU 11 to display drawing data in which an error has occurred (drawing data of the frame of the abnormal frame number). ) From the memory 12 and retransmitted from the transmission / reception ports 5a and 5b to the printer engines 102a and 102b. The CPUs 33a and 33b of the printer engines 102a and 102b receive the retransmitted drawing data at the transmission and reception ports 32a and 32b. Then, the redrawn drawing data is overwritten and corrected in the corresponding data area of the memories 35a and 35.

  As described above, the printer apparatus 100 according to the present exemplary embodiment includes the transmission ports 4aa and 4ab and the transmission ports 4ba and 4bb for each of the printer engines 102a and 102b that are transmission destinations, and the same data is transmitted to the printer engines 102a and 102b. Duplicated transmission.

  Therefore, it is possible to improve the accuracy of data transfer by adopting only the data that can be normally transferred through the duplex communication path as the received data, and to suppress the chance of re-transfer, thereby reducing the processing speed. Can be further improved.

  Also in this embodiment, when a transfer error occurs, after all the data transfer is completed, only the block data (frame data) in which the error has occurred is retransmitted, further improving the transfer efficiency. The transfer processing speed can be further improved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention is used for a printer device that transfers data from a data transfer device such as a control unit to a plurality of transfer destination devices such as an engine, a data transfer device such as a printer device, a data transfer system, a data transfer method, a data transfer program, and a recording medium. can do.

1 Printer device 2 DFE
3a, 3b Printer engine 11 CPU
12 memory 13 data control circuit 4a first transmission port 4b second transmission port 5a first transmission / reception port 5b second transmission / reception port 21 DMAC
22 bus 23 distribution circuit 23a first switch 23b second switch 31a, 31b reception port 32a, 32b transmission / reception port 33a, 33b CPU
34a, 34b Data control circuit 35a, 35b Memory 36a, 36b Check circuit 100 Printer device 101 DFE
102a, 102b Printer engine 110 Data control circuit 4aa, 4ab First transmission port 4ba, 4bb Second transmission port 111 Distribution circuit 120a, 120b Data control circuit 121aa, 121ab, 121ba, 121bb Buffer 122aa, 122ab, 122ba, 122bb Check circuit 123a 123b selector 124a, 124b internal bus 125a, 125b transfer data frame counter 126a, 126b transfer information register

JP 2003-318932 A

Claims (11)

In a data transfer device that transfers data to be transferred on a memory to a plurality of transfer destination devices,
Reading means for reading out the transfer target data from the memory;
Distributing means for distributing the transfer target data read by the reading means to the number of transfer destination devices;
Transmitting means for transmitting each of the transfer target data distributed by the distributing means to the transfer destination device;
The reading unit reads the data to be transferred from the memory in a predetermined block data unit, the block unit distributes the block data to block data for the transfer destination unit, and the transmission unit sets the transfer destination unit. Control means for transmitting to each of them,
A data transfer device comprising: The data transfer device
Transfer information generating means for generating, as transfer information, information related to the transfer of the transfer target data;
A transmission / reception means for exchanging various information with each of the transmission destinations;
The control unit causes the transmission / reception unit to transmit the transfer information generated by the transfer information generation unit to each of the transfer destination devices prior to transmission of the transfer target data. Data transfer device.   When there is a re-transmission request specifying the block data of the transfer target data from the transfer destination device, the control means sends the block data specified in the re-transmission request out of the transfer target data from the memory. 3. The data transfer apparatus according to claim 2, wherein the data transfer apparatus reads the data and transmits the data to the transfer destination apparatus.   The data according to any one of claims 1 to 3, wherein the transmission means has a double transmission structure for transmitting the same block data twice for each transfer destination device. Transfer device. In a data transfer system in which a data transfer device transfers data to be transferred on a memory to a plurality of transfer destination devices,
The data transfer device
Reading means for reading out the transfer target data from the memory;
Distributing means for distributing the transfer target data read by the reading means to the number of transfer destination devices;
Transmitting means for transmitting each of the transfer target data distributed by the distributing means to the transfer destination device;
Transmitting and receiving means for exchanging various types of information with each transfer destination device;
The reading unit reads the data to be transferred from the memory in a predetermined block data unit, the block unit distributes the block data to block data for the transfer destination unit, and the transmission unit sets the transfer destination unit. Control means for transmitting to each of them,
With
The transfer destination device is:
Transmission / reception means for transmitting / receiving various information to / from the transmission / reception means of the data transfer device;
Receiving means for receiving the block data transmitted from the transmitting means;
Error checking means for performing error check on the block data received by the receiving means and identifying error information for identifying block data in which an error has occurred in an error information storage means;
When all the transfer target data is received, control means for transmitting the error information stored in the error information storage means from the transmission / reception means to the transmission / reception means of the data transfer device;
With
The control means of the data transfer device includes:
When the transmission / reception means receives the error information from the transfer destination apparatus, the data transfer system is characterized in that the block data specified by the error information is read from the memory and transmitted from the transmission / reception means to the transfer destination apparatus. The data transfer device
Transfer information generating means for generating, as transfer information, information relating to the transfer of the transfer target data,
6. The data transfer according to claim 5, wherein the control unit causes the transmission / reception unit to transmit the transfer information generated by the transfer information generation unit to the respective transfer destination devices prior to transmission of the transfer target data. system. In a data transfer method for transferring data to be transferred on a memory to a plurality of transfer destination devices,
A read processing step of reading the transfer target data from the memory;
A distribution processing step of distributing the transfer target data read in the read processing step to the number of transfer destination devices;
A transmission processing step of transmitting each of the transfer target data distributed in the distribution processing step to the transfer destination device;
In the read processing step, the transfer target data is read from the memory in a predetermined block data unit, and the block data is distributed to the block data for the transfer destination device in the distribution processing step. Control processing steps to be transmitted to each of the transfer destination devices;
A data transfer method characterized by comprising: A data transfer method for transferring transfer target data in a memory from a data transfer device to a plurality of transfer destination devices,
The data transfer device is
A read processing step of reading the transfer target data from the memory;
A distribution processing step of distributing the transfer target data read in the read processing step to the number of transfer destination devices;
A transmission processing step of transmitting each of the transfer target data distributed in the distribution processing step to the transfer destination device;
A transmission / reception processing step for exchanging various types of information with the respective transfer destination devices;
The read processing step reads the transfer target data from the memory in predetermined block data units, the block processing data is distributed to the block data for the transfer destination device in the distribution processing step, and the transmission processing step Control processing steps to be transmitted to each of the transfer destination devices;
Have
The destination device is
A transmission / reception processing step for exchanging various types of information with the transmission / reception processing step of the data transfer device;
A reception processing step of receiving the block data transmitted by the transmission processing step;
An error check processing step for performing error check on the block data received in the reception processing step and storing error information for identifying block data in which an error has occurred in an error information storage unit;
Upon receiving all the transfer target data, a control processing step for transmitting the error information stored in the error information storage means from the transmission / reception processing step to the transmission / reception processing step of the data transfer device;
Have
The control processing step of the data transfer device comprises:
When the error information is received from the transfer destination device in the transmission / reception processing step, block data specified by the error information is read from the memory and transmitted to the transfer destination device by the transmission / reception processing step. Data transfer method. In a data transfer program for transferring transfer target data on a memory to a plurality of transfer destination devices,
On the computer,
A read process for reading the transfer target data from the memory;
A distribution process for distributing the transfer target data read in the read process to the number of the transfer destination devices;
A transmission process for transmitting each of the transfer target data distributed in the distribution process to a plurality of the transfer destination devices;
The read processing causes the transfer target data to be read from the memory in predetermined block data units, the block data is distributed to the block data for the transfer destination device in the distribution processing, and the transfer destination device is used for the transmission processing. Control processing to send to each
A data transfer program characterized in that In a data transfer program in which a data transfer device transfers data to be transferred on a memory to a plurality of transfer destination devices,
The data transfer program installed in the data transfer device is:
On the computer,
A read process for reading the transfer target data from the memory;
A distribution process for distributing the transfer target data read in the read process to the number of the transfer destination devices;
A transmission process for transmitting each of the transfer target data distributed in the distribution process to the transfer destination device;
A transmission / reception process for exchanging various information with each of the transfer destination devices;
The read processing causes the transfer target data to be read from the memory in predetermined block data units, the block data is distributed to the block data for the transfer destination device in the distribution processing, and the transfer destination device is used for the transmission processing. Control processing to send to each
And execute
The data transfer program installed in the transfer destination device is:
A transmission / reception process for transmitting / receiving various information to / from the transmission / reception process of the data transfer device;
A receiving process for receiving the block data transmitted from the transmitting process;
An error check process for performing error check on the block data received in the reception process and specifying error information for identifying block data in which an error has occurred in an error information storage unit;
When all the transfer target data is received, a control process for transmitting the error information stored in the error information storage unit to the transmission / reception process of the data transfer device by the transmission / reception process;
And execute
The control process of the master node is
When the transmission / reception process receives the error information from the transfer destination apparatus, the block data specified by the error information is read from the memory and transmitted to the transfer destination apparatus by the transmission / reception process.   A computer-readable recording medium on which the data transfer program according to claim 9 or 10 is recorded.

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