JP2006260273A - Subsystem module, information processor, and data transfer method in the subsystem module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently recover transfer errors in a bus access, and to enhance transfer accuracy. <P>SOLUTION: A bit for indicating the generation of a data parity error is formed in a control register 17, status of the parity error bit indicates the error, sequence number is written in an error status area of the control register 17, and the error is notified to a main board 5, when the data parity error is generated in a bus interface 14 in bus master thereof. Data, generating the transfer error, are thereby retransmitted to a subsystem module with respect to the sequence number written in the error status area of the control register 17, in a main board 5 side receiving error notification, and the transfer error in the bus access is recovered efficiently, thereby enhancing the transfer accuracy. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a subsystem module, an information processing apparatus, and a data transfer method in the subsystem module that are bus-connected to a main board including various electronic circuits.

  When transferring data with a large amount of information, such as image data, it is desirable to perform DMA (Direct Memory Access) transfer. Also, a PCI (Peripheral Component Interconnect) bus as a bus for performing DMA transfer is used in various systems because it can support a wide band from low speed to high speed.

  Patent Document 1 proposes an invention related to the internal configuration of a system for transferring image data by DMA.

  Patent Document 2 describes a system using a PCI bus.

JP-A-8-163339 JP-A-11-191073

  However, bus access and data transmission / reception using the bus are likely to become performance bottlenecks in various electronic circuit systems, although they are very frequent operations.

  In addition, in the case of multi-bit transmission on the PCI bus, transfer data may be garbled due to electrical problems such as wiring and cables. This is because the PCI bus is a high-speed and parallel bus, and the bit string of data flowing on the bus is different from the original bit string.

  The present invention has been made in view of the above, and is a subsystem module, an information processing apparatus, and data in a subsystem module that can efficiently recover a bus access transfer error and improve transfer accuracy. An object is to provide a transfer method.

  The present invention has been made in view of the above, and an object of the present invention is to provide a subsystem module, an information processing apparatus, and a data transfer method in the subsystem module that can increase the data transfer rate.

  In order to solve the above-described problems and achieve the object, the subsystem module of the invention according to claim 1 is connected in parallel bus to a main board having various electronic circuits, and data is transferred from a memory on the main board. A storage unit for temporarily storing data transferred from the memory on the main board, and directly reading the data stored in the memory on the main board to the storage unit. A DMA controller that performs DMA (Direct Memory Access) transfer, a bus interface that serves as a bus master during DMA transfer using the parallel bus by the DMA controller, and access from the main board is also possible. Data parity error occurred when the bus master A control register in which a bit indicating the error is generated, individual data error determination means for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA controller, and transfer data by the individual data error determination means When it is determined that an error has occurred, the status of the parity error bit of the control register is set to error occurrence, and an individual data error writing means for writing a sequence number in the error status area of the control register, and the control register Error notification means for notifying the main board of an error when the status of the parity error bit indicates that an error has occurred.

  According to a second aspect of the present invention, in the subsystem module according to the first aspect, the individual data error determination means is stored in a data area of transfer data stored in the storage unit by the DMA controller. When the checksum is compared with the checksum of the data area of the transfer data calculated by the bus interface, and it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, the transfer Determine that an error has occurred in the data.

  According to a third aspect of the present invention, in the subsystem module according to the first aspect, the error notification means notifies the individual transfer data of an error after the final data is transferred from the memory on the main board. Collectively, an error is notified to the main board.

  According to a fourth aspect of the present invention, in the subsystem module according to any one of the first to third aspects, the entire transfer data is transferred when the data transfer from the memory on the main board is completed and the data is ready. Is further provided with a whole data error judging means for judging whether or not an error has occurred, and when it is judged by the whole data error judging means that there is an error in the transfer data, the parity error bit of the control register The status is set to error occurrence, and an error notification is sent to the main board.

  According to a fifth aspect of the present invention, in the subsystem module according to any one of the first to fourth aspects, the parallel bus is a PCI (Peripheral Component Interconnect) bus.

  According to a sixth aspect of the present invention, there is provided an information processing apparatus comprising: a main board having various electronic circuits; and a subsystem module connected to the main board in parallel bus and transferring data from a memory on the main board. In the information processing apparatus provided, the subsystem module includes a storage unit for temporarily storing data transferred from the memory on the main board, and data stored in the memory on the main board. Controller that directly reads out and transfers DMA (Direct Memory Access) to the storage unit, a bus interface that serves as a bus master, and access from the main board during DMA transfer using the parallel bus by the DMA controller When the bus interface is a bus master A control register in which a bit indicating the occurrence of a data parity error is formed, individual data error determination means for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA controller, and the individual data error When it is determined by the determination means that an error has occurred in the transfer data, the status of the parity error bit of the control register is set to generate an error, and the individual data error writing means for writing the sequence number in the error status area of the control register; Error notification means for notifying the main board of an error when the status of the parity error bit in the control register indicates an error occurrence, and the main board includes the subsystem module. When an error notification is received from the control module, a retransmission means is provided for retransmitting the data causing the transfer error to the subsystem module according to the sequence number written in the error status area of the control register.

  According to a seventh aspect of the present invention, in the information processing apparatus according to the sixth aspect, the individual data error determination means is stored in a data area of transfer data stored in the storage unit by the DMA controller. When the checksum is compared with the checksum of the data area of the transfer data calculated by the bus interface, and it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, the transfer Determine that an error has occurred in the data.

  According to an eighth aspect of the present invention, in the information processing apparatus according to the sixth aspect, after the final data is transferred from the memory on the main board, the error notification means notifies an error of individual transfer data. Collectively, an error is notified to the main board.

  The invention according to claim 9 is the information processing apparatus according to any one of claims 6 to 8, wherein the subsystem module completes data transfer after data transfer from the memory on the main board is completed. In the step, the apparatus further comprises overall data error determining means for determining whether or not an error has occurred in the entire transfer data, and when it is determined by the overall data error determining means that an error has occurred in the transfer data, the control The status of the parity error bit of the register is set to error occurrence, and an error is notified to the main board.

  According to a tenth aspect of the present invention, in the information processing apparatus according to any one of the sixth to ninth aspects, the parallel bus is a PCI (Peripheral Component Interconnect) bus.

  According to an eleventh aspect of the present invention, in the data transfer method in the subsystem module, the data transfer in the subsystem module connected in parallel bus to the main board having various electronic circuits and transferred from the memory on the main board. A DMA transfer step of directly reading data stored in a memory on the main board by a DMA controller and transferring the data to a storage unit for temporarily storing the data; An individual data error determination step for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA transfer step, and it has been determined that an error has occurred in the transfer data by the individual data error determination step. Access from the main board is also possible. An individual data error writing step of setting the status of the parity error bit of the control register that has formed a bit indicating the occurrence of a data parity error when the bus interface is a bus master as an error occurrence and writing the sequence number in the error status area of the control register; And an error notification step of notifying the main board of an error when the status of the parity error bit of the control register indicates that an error has occurred.

  The invention according to claim 12 is the data transfer method in the subsystem module according to claim 11, wherein the individual data error determination step is stored in a data area of transfer data stored in the storage unit. When the checksum is compared with the checksum of the data area of the transfer data calculated by the bus interface, and it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, the transfer Determine that an error has occurred in the data.

  According to a thirteenth aspect of the present invention, in the data transfer method in the subsystem module according to the eleventh aspect, in the error notification step, after the final data is transferred from the memory on the main board, individual transfer data is transferred. The error notifications are collectively notified to the main board.

  The invention according to claim 14 is the data transfer method in the subsystem module according to any one of claims 11 to 13, wherein the data transfer from the memory on the main board is completed and the data is ready. And an overall data error determination step for determining whether or not an error has occurred in the entire transfer data, and when it is determined that an error has occurred in the transfer data in the overall data error determination step, the parity of the control register The error bit status is set to error occurrence, and an error notification is sent to the main board.

  The invention according to claim 15 is the data transfer method in the subsystem module according to any one of claims 11 to 14, wherein the parallel bus is a PCI (Peripheral Component Interconnect) bus.

  According to the subsystem module of the first aspect of the present invention, a bit indicating the occurrence of a data parity error is formed in the control register of the bus interface, and if a data parity error occurs when the bus interface is a bus master, the control of the bus interface is performed. When the status of the parity error bit in the register indicates an error and the sequence number is written to the error status area of the control register, and the status of the parity error bit in the control register indicates that an error has occurred, Added error notification. As a result, the main board that received the error notification can retransmit the data causing the transfer error to the subsystem module according to the sequence number written in the error status area of the control register. Transfer errors can be efficiently recovered, and transfer accuracy can be improved. In addition, since the transfer amount can be minimized, the data transfer rate can be increased.

  According to the subsystem module of the invention of claim 2, the individual checksum stored in the data area of the transfer data stored in the storage unit and the check of the data area of the transfer data calculated by the bus interface When it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that an error has occurred in the transfer data. It can be performed efficiently.

  According to the subsystem module of the invention of claim 3, after the final data is transferred from the memory on the main board, the error notifications of the individual transfer data are collectively notified to the main board. As a result, the number of bus accesses can be reduced and the load can be reduced.

  According to the subsystem module of the invention of claim 4, the data accuracy can be improved by checking the data when the transfer is completed and the data is ready.

  According to the subsystem module of the invention of claim 5, data transfer can be performed at high speed because the parallel bus is a PCI bus.

  According to the information processing apparatus of the sixth aspect of the present invention, a bit indicating the occurrence of a data parity error is formed in the control register of the bus interface, and when the data parity error occurs when the bus interface is a bus master, the bus interface If the status of the parity error bit in the control register indicates an error and the sequence number is written to the error status area of the control register, the status of the parity error bit in the control register indicates that an error has occurred. An error notification was made. As a result, the main board that received the error notification can retransmit the data causing the transfer error to the subsystem module according to the sequence number written in the error status area of the control register. Transfer errors can be efficiently recovered, and transfer accuracy can be improved. In addition, since the transfer amount can be minimized, the data transfer rate can be increased.

  According to the information processing apparatus of the invention of claim 7, the individual checksum stored in the data area of the transfer data stored in the storage unit and the check of the data area of the transfer data calculated by the bus interface When it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that an error has occurred in the transfer data. It can be performed efficiently.

  According to the information processing apparatus of the invention according to claim 8, after the final data is transferred from the memory on the main board, the error notifications of the individual transfer data are collectively notified to the main board. As a result, the number of bus accesses can be reduced and the load can be reduced.

  According to the information processing apparatus of the ninth aspect of the present invention, the data accuracy can be improved by checking the data when the transfer is completed and the data is ready.

  In the information processing apparatus according to the tenth aspect of the present invention, since the parallel bus is a PCI bus, data can be transferred at high speed.

  According to the data transfer method in the subsystem module of the invention of claim 11, a bit indicating the occurrence of a data parity error is formed in the control register of the bus interface, and when the data parity error occurs when the bus interface is the bus master. When the status of the parity error bit in the bus interface control register indicates an error and the sequence number is written to the error status area of the control register, and the status of the parity error bit in the control register indicates an error has occurred Added error notification to main board. As a result, the main board that received the error notification can retransmit the data causing the transfer error to the subsystem module according to the sequence number written in the error status area of the control register. Transfer errors can be efficiently recovered, and transfer accuracy can be improved. In addition, since the transfer amount can be minimized, the data transfer rate can be increased.

  According to the data transfer method in the subsystem module of the invention of claim 12, the individual checksum stored in the data area of the transfer data stored in the storage unit and the transfer data calculated by the bus interface are stored. When the check result of the data area is compared, and it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that there is an error in the transfer data. It is possible to efficiently perform error determination.

  According to the data transfer method in the subsystem module of the invention of claim 13, after the final data is transferred from the memory on the main board, the error notifications of the individual transfer data are put together to the main board. By notifying an error, the number of bus accesses can be reduced and the load can be reduced.

  According to the data transfer method in the subsystem module of the fourteenth aspect of the invention, the data accuracy can be improved by checking the data when the transfer is completed and the data is ready.

  According to the data transfer method in the subsystem module of the fifteenth aspect of the present invention, since the parallel bus is a PCI bus, data can be transferred at high speed.

  Exemplary embodiments of a subsystem module, an information processing apparatus, and a data transfer method in the subsystem module according to the present invention are explained in detail below with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which a color laser printer is applied as an information processing apparatus.

  FIG. 1 is a longitudinal side view schematically showing a configuration of an information processing apparatus including a data communication apparatus according to a first embodiment of the present invention. In FIG. 1, the control unit 3 of the information processing apparatus 1 receives a data from the host PC 2 and develops it into a bitmap, a data communication device 10 (see FIG. 2) having a printer controller, DMA (Direct Memory Access) controller, And an engine control unit for controlling the operation of the mechanical mechanism 4 of the information processing apparatus 1. The data communication apparatus 10 according to the present embodiment is a wireless local area network (LAN) card for transmitting and receiving data by wireless communication. Therefore, the information processing apparatus 1 and the host PC 2 perform data communication with a wireless LAN.

  FIG. 2 is a block diagram illustrating a configuration of the control unit 3 mainly including the data communication apparatus 10. As shown in FIG. 2, the data communication device 10 has a subsystem module configuration in which a bus connection is made to a main board 5 functioning as a printer controller or an engine control unit via a connection unit 10a. The connection unit 10a is a part that connects the data communication device 10 that is a subsystem module to the connection unit (slot) 6 of the main board 5, and is connected to a PCI (Peripheral Component Interconnect) bus.

  FIG. 3 is a block diagram showing the configuration of the main board 5. As shown in FIG. 3, the main board 5 includes various electronic circuits (not shown) that control the information processing apparatus 1 and a CPU (Central Processing Unit) 5 a that controls each unit. The CPU 5a is connected to a memory 5b for storing a program such as firmware for controlling the data communication apparatus 10 and a PCI I / F 5c connected to a connection unit (slot) 6.

  Next, the data communication apparatus 10 will be described in detail. As shown in FIG. 2, the data communication apparatus 10 includes a CPU 11 that performs overall control of the data communication apparatus 10. The CPU 11 includes a memory 12, an ASIC (Application Specified IC) 13, a PCI I / F 14, and a wireless communication. The LAN module 20 is connected by a bus.

  The memory 12 is SRAM, SDRAM, DRAM, or the like, and is used for storing information such as firmware.

  The ASIC 13 includes a TxDMAC 15, a TxRAM 16, and a CTRLRAM 17. The TxDMAC 15 is a transmission DMA (Direct Memory Access) controller, and performs DMA transfer from the memory 5b on the main board 5 to the TxRAM 16. As described above, the TxRAM 16 is a memory that receives information from the TxDMAC 15 and is an SRAM, SDRAM, or DRAM. That is, the TxRAM 16 is a storage unit for temporarily storing data transferred from the memory 5b on the main board 5. The CTRL RAM 17 is a dual port RAM (SRAM, SDRAM, DRAM) and is accessible from the main board 5 and the CPU 11. Information can be exchanged between the main board 5 and the CPU 11 via the CTRLRAM 17. The CTRLRAM 17 functions as a control register of the PCI I / F 14.

  The PCI I / F 14 is a bus interface, and becomes a bus master when the TxDMAC 15 performs DMA transfer from the memory 5b on the main board 5 to the TxRAM 16 using the PCI bus.

  With such a configuration, the data communication apparatus 10 that is a subsystem module can receive, for example, a program necessary for the operation of the data communication apparatus 10 from the memory 5b on the main board 5. More specifically, the TxDMAC 15 performs DMA transfer of data on the memory 5b on the main board 5 to the TxRAM 16, and the CPU 11 copies the data from the TxRAM 16 to the memory 12 every time the data is stored in the TxRAM 16. By repeating this transfer, it is possible to arrange all the data on the memory 12, and the CPU 11 can execute a program which is data on the memory 12.

  However, when data is transferred from the memory 5b on the main board 5 to the data communication device 10 which is a subsystem module via the PCI bus, the bit string of data flowing on the bus is inherently high because the PCI bus is a high-speed and parallel bus. The bit string of the transfer data may be garbled.

  Therefore, in the present embodiment, a bit indicating the occurrence of a data parity error is formed in the CTRLRAM 17 which is the control register of the PCI I / F 14, and when the PCI I / F 14 has a data parity error when it is a bus master, the PCI I / F 14 The parity error bit of the CTRLRAM 17, which is the control register of / F14, indicates an error.

  Here, a transfer data format used for data transfer between the data communication apparatus 10 as a subsystem module and the main board 5, that is, transfer data used for data transfer to the TxRAM 16 will be described.

  FIG. 4 is an explanatory diagram showing the configuration of the first transfer data format, and FIG. 5 is an explanatory diagram showing the configuration of the second and subsequent transfer data formats. In this embodiment, transfer data is transferred using the data portion of the transfer data format shown in FIGS. Common data components in FIGS. 4 and 5 are address, size, and sequence number. This is because the amount of data transferred once depends on the size of the TxRAM 16. The address is used when data is copied after transfer to the TxRAM 16. Normally, the DMA transferred data is copied and transferred to the memory 12 or the like for each transfer. The size indicates the data size for each transfer. The sequence number becomes an identifier of the transfer data, and numbers 1 to 65535 are used in the transfer order. The individual checksum is a checksum of the data area for each transfer. In this embodiment, the address is 32 bits, the size is 16 bits, the sequence number is 16 bits, and the individual checksum is 32 bits. The number of bits can be changed and used.

  In the first transfer data format shown in FIG. 4, a total checksum and a total size are added. The total checksum is a checksum of the entire data downloaded from the main board 5 by the data communication apparatus 10 as a subsystem module, and is used to check the data when the transfer is completed and the data is ready. Such an overall checksum is not always necessary, but the accuracy of the data is increased. On the other hand, the total size can be used to know the end of data transfer. Such a total size is not always necessary.

  By having such a transfer data format of FIG. 4 or FIG. 5 for each transfer, a data check for each transfer can be performed.

  When transferring a program, a transfer data format as shown in FIG. 6 may be used. In the first transfer data format shown in FIG. 6, instead of the total size described in FIG. 4, a program size, an ID, and a version are components. The program size is the size of the entire program data stored in the data part that does not include the header area. ID is the ID of this program data. The version indicates the version of the program data.

  Next, error detection of DMA individual data in the data communication apparatus 10 will be described. FIG. 7 is a flowchart showing a flow of data transfer processing in the data communication apparatus 10. As shown in FIG. 7, the CPU 11 of the data communication apparatus 10 that is a subsystem module receives data from the main board 5 and stores the data in the TxRAM 16 according to the program stored in the memory 12 (in step S1). Y) Cause the PCI I / F 14 to calculate the checksum of the data area of the transfer data.

  When the calculation result by the PCI I / F 14 is compared with the individual checksum added to the transfer data, and the calculation result by the PCI I / F 14 is determined to be inconsistent with the individual checksum added to the transfer data, That is, if it is determined that the individual checksum is an error (Y in step S2: individual data error determination means), the error status of the CTRLRAM 17 is set to error, and the sequence number is written to the error status area of the CTRLRAM 17 (step S3). : Individual data error writing means). The CTRLRAM 17 is a dual port RAM that can be accessed from the main board 5 and the CPU 11 of the data communication apparatus 10. The data communication apparatus 10 writes the sequence number that caused the error to the CTRLRAM 17 as an error notification of the DMA individual data. It is possible to inform the main board 5 of the sequence number that caused the transfer error. As a result, the main board 5 can retransmit the data causing the transfer error to the data communication apparatus 10. If an error is detected by the individual checksum, the data communication device 10 as a subsystem module does not write the block in which the error data is detected to the memory 12.

  On the other hand, if it is determined that the individual checksum is not an error (N in step S2: individual data error determination means), the CPU 11 copies the data in the TxRAM 16 to the memory 12 (step S4). If no jump command due to a PCI interrupt has occurred (N in step S2), the process returns to step S1 and waits for the next data reception from the main board 5.

  On the other hand, if the final data has been transferred and a jump command has been generated (Y in step S5), an overall checksum check of the memory 12 is performed (step S6: overall data error determination means).

  If it is determined that the entire checksum is an error (Y in step S7), the error status of the CTRLRAM 17 is set to error (step S8), and the CTRLRAM 17 is read to notify the error (step S9: error notification means).

FIG. 8 is an explanatory diagram showing an error check status register in the CTRLRAM 17. Bit 0 shown in A is an overall checksum error status, and indicates 1 when an overall checksum error has occurred. Bit 1 shown in B is an individual checksum error status, and indicates 1 when an individual checksum error has occurred. As the error status of the individual data, a sequence number is written when an error occurs in the following area of the CTRL RAM 17.
2804h 1
2806h 2
2808h 3
280Ah 4
・ ・ ・ ・ ・ ・
2A00h 255
It should be noted that data that does not generate an individual checksum error is not written.

  Here, the reason why the individual data error notifications are collectively notified after the final data transfer and the entire checksum check are completed will be described. The reason why the individual data error notifications are collectively notified is that the number of times of PCI access can be reduced by collectively reporting. This is because access to the PCI bus places a heavy load on the CPU 11 and the CPU 5 a on the main board 5.

  On the other hand, if it is determined that the overall checksum is not an error (N in step S7), the process proceeds to step S10, where remap and firmware are executed.

  On the main board 5 side, when an error notification is received from the data communication device 10 by the CPU 5a following the program stored in the memory 5b, the data is transferred according to the sequence number written in the error status area of the CTRLRAM 17 of the data communication device 10. The data causing the error is retransmitted to the data communication apparatus 10. As a result, the transfer amount can be minimized, so that the data transfer rate can be increased. Here, the function of the retransmission means is executed.

  As described above, according to the present embodiment, a bit indicating the occurrence of a data parity error is formed in the CTRLRAM 17 which is the control register of the PCI I / F 14, and when the PCI I / F 14 has a data parity error when it is a bus master, The status of the parity error bit of the CTRLRAM 17 that is the control register of the PCI I / F 14 indicates an error, and the sequence number is written in the error status area of the CTRLRAM 17 that is the control register, and the status of the parity error bit of the CTRLRAM 17 that is the control register An error is notified to the main board 5 when indicates an error. As a result, the main board 5 that has received the error notification retransmits the data causing the transfer error to the data communication apparatus 10 that is the subsystem module according to the sequence number written in the error status area of the control register CTRLRAM 17. As a result, it is possible to efficiently recover a bus access transfer error and improve transfer accuracy. In addition, since the transfer amount can be minimized, the data transfer rate can be increased.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted. In this embodiment, a data communication apparatus to which an external memory is connected is applied as a data communication apparatus.

  FIG. 9 is a block diagram illustrating a configuration of the control unit 3 mainly including the data communication apparatus 10 according to the second embodiment of the present invention. As shown in FIG. 9, the data communication apparatus 10 according to the present embodiment includes a memory controller 30 for connecting and controlling an external memory 31 in addition to the configuration of the first embodiment. 30 is bus-connected to the CPU 11. The external memory 31 is a storage unit such as a flash memory, EEPROM, DRAM, or hard disk, and the memory controller 30 performs various settings necessary for the CPU 11 to control the external memory 31.

  With such a configuration, the data communication device 10 which is a subsystem module receives, for example, a program for operating the data communication device 10 stored in the external memory 31 from the memory 5b on the main board 5, and stores the program in the external memory 31. It is possible to rewrite the contents. The TxDMAC 15 performs DMA transfer of the data in the memory 5b on the main board 5 to the TxRAM 16, and the CPU 11 copies or writes data from the TxRAM 16 to the external memory 31 each time the data is stored in the TxRAM 16. By repeating this transfer, it is possible to arrange all the data on the external memory 31, and the external memory 31 can be rewritten. Further, the CPU 11 can execute a program that is data on the external memory 31.

  In each embodiment, an example in which a color laser printer is applied as an information processing apparatus has been described. However, the present invention is not limited to this, and the information processing apparatus can include a copy function, a facsimile (FAX) function, a print function, and a scanner. Applying to a digital color multi-function peripheral called a so-called MFP (Multi Function Peripheral) that combines functions and functions for delivering input images (images read by the scanner function or images input by a printer or FAX function). You can also.

1 is a longitudinal side view schematically showing a configuration of an information processing apparatus including a data communication apparatus according to a first embodiment of the present invention. It is a block diagram which shows the structure of the control part mainly having a data communication apparatus. It is a block diagram which shows the structure of a main board. It is explanatory drawing which shows the structure of the 1st transfer data format. It is explanatory drawing which shows the structure of the transfer data format after the 2nd. It is explanatory drawing which shows another structure of the 1st transfer data format. It is a flowchart which shows the flow of the data transfer process in a data communication apparatus. It is explanatory drawing which shows the error check status register in CTRLRAM. It is a block diagram which shows the structure of the control part which mainly made the data communication apparatus concerning the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 5 Main board 5a Memory on main board 10 Subsystem module 14 Bus interface 15 DMA controller 16 Storage part 17 Control register

Claims (15)

In a subsystem module connected in parallel bus to a main board having various electronic circuits and transferring data from a memory on the main board,
A storage unit for temporarily storing data transferred from the memory on the main board;
A DMA controller that directly reads data stored in a memory on the main board and transfers the data to the storage unit (DMA (Direct Memory Access));
A bus interface serving as a bus master during DMA transfer using the parallel bus by the DMA controller;
Access from the main board is also possible, a control register that forms a bit indicating a data parity error occurrence when the bus interface is a bus master, and
Individual data error determination means for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA controller;
When it is determined by the individual data error determination means that an error has occurred in the transfer data, the status of the parity error bit of the control register is set to generate an error, and the individual data to be written in the error status area of the control register Error writing means;
An error notification means for notifying the main board of an error when the status of the parity error bit of the control register indicates an error occurrence;
A subsystem module comprising: The individual data error determination means includes an individual checksum stored in the data area of transfer data stored in the storage unit by the DMA controller, and a checksum of the data area of transfer data calculated by the bus interface. If it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that an error has occurred in the transfer data.
The subsystem module according to claim 1. The error notification means, after the final data is transferred from the memory on the main board, collectively error notification of individual transfer data to notify the error to the main board,
The subsystem module according to claim 1. The data transfer from the memory on the main board is completed, and further comprises overall data error determination means for determining whether or not an error has occurred in the entire transfer data when the data is ready.
When it is determined that an error has occurred in the transfer data by this overall data error determination means, the status of the parity error bit of the control register is set to error occurrence, and an error is notified to the main board.
The subsystem module according to any one of claims 1 to 3, wherein: The parallel bus is a PCI (Peripheral Component Interconnect) bus.
The subsystem module according to any one of claims 1 to 4, wherein: In an information processing apparatus comprising a main board including various electronic circuits, and a subsystem module connected to the main board by a parallel bus and transferring data from a memory on the main board,
The subsystem module is
A storage unit for temporarily storing data transferred from the memory on the main board;
A DMA controller that directly reads data stored in a memory on the main board and transfers the data to the storage unit (DMA (Direct Memory Access));
A bus interface serving as a bus master during DMA transfer using the parallel bus by the DMA controller;
Access from the main board is also possible, a control register that forms a bit indicating a data parity error occurrence when the bus interface is a bus master, and
Individual data error determination means for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA controller;
If the individual data error determination means determines that an error has occurred in the transfer data, the status of the parity error bit of the control register is set to generate an error, and the individual data to be written in the error status area of the control register Error writing means;
An error notification means for notifying the main board of an error when the status of the parity error bit of the control register indicates an error occurrence;
With
The main board is
Receiving means for receiving an error notification from the subsystem module comprises a retransmission means for retransmitting data causing a transfer error to the subsystem module according to a sequence number written in an error status area of the control register.
An information processing apparatus characterized by that. The individual data error determination means includes an individual checksum stored in the data area of transfer data stored in the storage unit by the DMA controller, and a checksum of the data area of transfer data calculated by the bus interface. If it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that an error has occurred in the transfer data.
The information processing apparatus according to claim 6. The error notification means, after the final data is transferred from the memory on the main board, collectively error notification of individual transfer data to notify the error to the main board,
The information processing apparatus according to claim 6. The subsystem module is
The data transfer from the memory on the main board is completed, and further comprises overall data error determination means for determining whether or not an error has occurred in the entire transfer data when the data is ready.
When it is determined that an error has occurred in the transfer data by this overall data error determination means, the status of the parity error bit of the control register is set to error occurrence, and an error is notified to the main board.
The information processing apparatus according to claim 6, wherein the information processing apparatus is an information processing apparatus. The parallel bus is a PCI (Peripheral Component Interconnect) bus.
The information processing apparatus according to claim 6, wherein the information processing apparatus is an information processing apparatus. A data transfer method in a subsystem module connected in parallel bus to a main board having various electronic circuits and transferring data from a memory on the main board,
A DMA transfer step of directly reading data stored in the memory on the main board by the DMA controller and transferring the data to a storage unit for temporarily storing the data (DMA (Direct Memory Access));
An individual data error determination step for determining whether or not an error has occurred in the transfer data stored in the storage unit by the DMA transfer step;
If it is determined in this individual data error determination step that an error has occurred in the transfer data, access from the main board is also possible, and a control that forms a bit indicating the occurrence of a data parity error when the bus interface is a bus master An individual data error writing step for setting the status of the parity error bit of the register to generate an error and writing the sequence number in the error status area of the control register;
An error notification step of notifying the main board of an error when the status of the parity error bit of the control register indicates an error occurrence;
A data transfer method in a subsystem module comprising: The individual data error determination step compares the individual checksum stored in the data area of the transfer data stored in the storage unit with the checksum of the data area of the transfer data calculated by the bus interface, If it is determined that the calculation result by the bus interface does not match the individual checksum added to the transfer data, it is determined that an error has occurred in the transfer data.
The data transfer method in the subsystem module according to claim 11. In the error notification step, after the final data is transferred from the memory on the main board, the error notification of the individual transfer data is collectively notified to the main board,
The data transfer method in the subsystem module according to claim 11. An overall data error determination step for determining whether or not an error has occurred in the entire transfer data when the data transfer from the memory on the main board is completed and the data is ready;
If it is determined that an error has occurred in the transfer data in the overall data error determination step, the status of the parity error bit in the control register is set to generate an error, and an error is notified to the main board.
14. A data transfer method in a subsystem module according to claim 11, wherein the data is transferred in the subsystem module. The parallel bus is a PCI (Peripheral Component Interconnect) bus.
15. The data transfer method in the subsystem module according to claim 11, wherein the data is transferred in the subsystem module.

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