CS219975B1 - Control unit for connecting the periphery devices to the computers - Google Patents

Description

The invention solves a controller for connecting peripheral devices to selector or multiplex channels of computers whose interfaces are parallel and asynchronous, based on the principle of query-response.

In the case of commonly manufactured computers, the contact between the computer and the peripheral device is carried out according to a well-defined protocol, which for some computers can be quite complex. To realize the connection according to the protocol, the peripheral devices are equipped with a block intended for connection to the channel. Due to the required communication speed, this block is solved using integrated circuits and other electronic components and its wiring diagram is fixed by the respective wiring protocol and by the given peripheral device. In computer centers, there is often a need to connect non-dedicated devices to the computer, where the connection of the channel connection block is different.

The problem is eliminated by a controller for connecting peripheral devices to a computer according to the invention, which consists of receiving amplifiers which are connected via a data bus and a control signal bus to an input bus decoder whose data output is connected to a block for connection to a an auxiliary device that is coupled to a register block that is connected to transmit amplifiers via data buses and control signal buses, wherein the input bus decoder, the register block, and the auxiliary connection block are coupled to a control block that is connected to the memory.

According to a feature of the invention, the control block is formed by a multiplexer whose address inputs are coupled to the first to fifth counter input inputs and whose output is coupled to the input input of the first D-flip-flop whose output is connected to the first input of the first logical equivalence circuit. the input is connected to the output of the second D-flip-flop, whose setting input is connected to the sixth setting input of the counter. The output of the first logic equivalence circuit is connected to the first input of the first logic product circuit, the second input of which is connected to the output and to the K-input of the JK-flip-flop whose negated J-input is connected to the eighth counter input. The output of the first logic product circuit is connected to the negated first input of the third logic equivalence circuit. To the first input of the second logic equivalence circuit, the second inputs of which are connected to a generator to which the JK flip-flop synchronization input is connected, through the inverter, the first D-flip-flop, the second D-flip-flop, and the third D-flip-flop. via the inverter of the synchronous logic product circuit, the third logic product circuit and the fourth logioc product, whose first inputs are interconnected, the third inputs are connected to the seventh counter input input. The fourth inputs are coupled to the eighth counter setting input, and the fifth inputs of the third and fourth logic products are coupled to the sixth counter setting input. The output of the second logical product circuit is connected to the input of the first demultiplexer information, the output of the third logical product circuit is connected to the input of the second demultiplexer information, and the output of the fourth logical product circuit is connected to the input of the third demultiplexer information. The address inputs of the first, second and third demultiplexers are coupled to the first to fifth counter input inputs. The output of the third logical equivalence circuit is connected to the counter count pulse input, the output of the second logical equivalence circuit is connected to the counter synchronous setting input. Via the inverter, this output of the second logic equivalence circuit is connected to a D-flip-flop synchronization input with a set-up asynchronous input and this set-up asynchronous input is connected to an output for transmission to the next row of the counter. Further, the D-flip-flop setting input with the asynchronous input setting is coupled to the output of the third D-flip-flop, whose setup vistuip is coupled to the seventh counter input input. Individual outputs of the second demultiplexer are connected to the setting inputs of RS-flip-flops, to whose reset inputs the individual outputs of the third demultiplexer are connected.

The main problem is the speed of the controller, because the interface of the peripheral devices with the computer is divided into short sections, lasting up to several tens of seconds, during which up to 100 instructions must be executed, depending on the complexity of the connection protocol.

The controller according to the invention is programmable using the following instructions:

Conditional Jump - This instruction allows you to compare one of the 31 levels, eg the levels on the control wires from the computer channel, to the expected level that is specified in the instruction.

In case of a match, jump to the address specified in the instruction. The address contains a maximum of 9 bits. In the event of a mismatch, the program continues with the following instruction.

Unconditional jump - this instruction executes a jump to the address specified in it, max address has 9 bits. Flip Circuit Setting - This instruction allows you to set or reset one of the 32 flip-flops, such as flip-flops controlling the output wires from the peripheral to the computer, or flip-flops to remember the internal states of the controller.

Pulse Generation — This instruction allows you to generate one of 31 pulses of 50 nS duration. These pulses can be used to reset registers, set and reset flip-flops in registers, etc.

Empty instruction - this instruction causes only a time delay of 200 nS in program execution.

Furthermore, the controller allows asynchronous interruption of its operation, i.e., return to the start address in case of certain conditions arising from the cooperation with the channel. The length of the control word can be different, for better clarity the description of the individual instructions is based on a specific application in which the control word is 8 bits long. The execution time of individual instructions depends on the component base used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a controller of the present invention; and FIG. 2 is a diagram of a control block for an eight-bit control word version.

The controller for connecting the peripheral devices to the computer according to FIG. 1 is formed by receiving amplifiers 1, which are connected via a data bus and a control signal bus to an input bus decoder 3, the data output of which is connected to a block 5 a register block 4 which is connected via the data bus and the control signal bus to the transmit amplifiers 2, the input bus decoder 3, the register block 4 and the auxiliary device block 5 being connected to a control block fi which is connected to the memory 7 .

The receiver amplifiers 1 convert the electrical signal levels used on the channel buses to logical levels.

The transmit amplifiers 2 convert the logical levels to the bus signal levels.

The input bus decoder 3 comprises a channel data bus decoder, which is necessary for recognizing the address of the peripheral device, checking the parity of the information, checking the admissibility of the operation, and the like.

The register block 4 comprises a data buffer and service registers, for example a status information register, an error register and the like. The connection of said blocks depends on the particular computer to which the controller according to the invention is connected.

Block 5 for connection to the auxiliary device comprises buffer registers for the data and possibly also a control signal decoder. The wiring of this block depends on the particular device to be connected.

The control block 6 of FIG. 2 comprises a multiplexer 8 whose address inputs are connected to the first to fifth setting inputs of the counter 20 and whose output is connected to the setting input of the first D-flip-flop 10, the output of which is connected to the first input of the first circuit 14 the second input of which is connected the output of the second D-flip-flop 11, the setting input of which is connected to the sixth setting input of the counter 20. The output of the first logic equivalence circuit 14 is connected to the first input of the first logic product 15 of connected to the output and to the K-input of the JK flip-flop 12, whose negated J-input is connected to the eighth setting input of the counter 20. The output of the first logic product 15 is connected to the negated first input of the third logic equivalence circuit 16. To the first input of the second logic equivalence circuit 17, the second inputs of which are connected to a generator 21, to which the synchronization input of the JK-flip-flop 12 is further connected, through the inverter 9 the synchronization inputs of the first D-flip-flop 10, the second D-flip-flop 11 and the third D-flip-flop 13, and the second inputs of the second logic 22, the third logic 23, and the fourth logic 24, whose first inputs are interconnected, the third inputs are connected to the seventh counter input of the counter 20. The fourth inputs are connected with the eighth counter input 20 and the fifth inputs of the third and fourth logic product 23 and 24 are connected to the sixth counter input input 20. The output of the second logic product circuit 22 is connected to the information input of the first demultiplexer 25; to input information kind The output inputs of the first, second and third demultiplexers 25, 26, 27 are coupled to the first to fifth setting inputs of the counter 20. The output of the third logical equivalence circuit 16 is connected to the counted pulse input of the counter 20, the output of the second logic equivalence circuit 17 is connected to the input for synchronous adjustment of the counter 20. Through the inverter 18 this output of the second logic equivalence circuit 17 is connected to the synchronization input of the D-flip-flop 19 with the setting asynchronous input. the adjusting asynchronous input is connected to the output for transmission to the next row of the counter 20. Further, the adjusting input of the D-flip-flop 19 with the adjusting asynchronous input is connected to the output of the third D-flip-flop 13, the adjusting input of which is connected to the seventh adjusting input or 219975 t. The individual outputs of the second demultiplexer 26 are connected to the adjusting inputs of the RS-collapsing circuits 28 to 59, to whose reset inputs the individual outputs of the third demultiplexer 27 are connected. The adjusting inputs of the counter 20 are connected to the control outputs of the memory 7 whose address inputs they are connected to the outputs of the counter 20.

For each specific application, 76543 2 10 222 2 2222 is needed

The common number of inputs of the multiplexer 8 is connected to the outputs of the input bus decoder 3, the register block 4 and the block 5 for connection to the auxiliary devices, as well as the required number of RS-flip-flop 28 to 59 outputs and the outputs of the first demultiplexer 25.

Before explaining the operation of the control block 6, an 8-bit control word is described.

number of analysis, command, or RS-flip-flop

------- In the case of the analysis instruction, the expected level is here.

In case of RS-flip-flop instruction - setting of RS-flip-flop 0 means - resetting of RS-flip-flop

In the pulse instruction, this bit is ignored.

code instruction - instruction impulse · 10— instruction flip-flop 0 X - instruction jump

In the case of a jump instruction, the lower 8 bit jump addresses are stored at the following address.

The unconditional jump instruction has the form:

X 0 1 1 1 1 1, ie the input 31, which is permanently grounded, is analyzed, so the levels always match.

Address - binary Information - binary

000000000

000000001

000000010

000000011

000000 100 000000101

00101100

00000011

10100100

11001000

11111111

01011111

000000110 01110000

Before the first synchronization pulse is received, information from the memory 7 is 0010110 0.

With the rising edge of the synchroimpulse, 1 is added to the address counter 20 and the selection of new information begins. However, the information output from memory 7 remains unchanged for min. With the falling edge of the first synchronization pulse, the length of which must not be greater than 50 nS, the second D-flip-flop 11 and the JK-flip-flop 12 will write, with 0 into the D-flip-flop 19 s to set X has the meaning of the highest bit of the jump address

The empty instruction has the form:

11111111, ie. a pulse generation is made to output 31 which is not connected. The control block 6 is in the initial state, i.e. all RS-flip-flops 28-59 and address counter 20 are reset. The following information is written to the initial memory addresses:

Meaning Information Analysis of the 12th Multiplexer Input 8 Lower 8 Bits Jump Address Setting the Fourth RS-Flip Circuit 31 to 1 Pulse on the Eighth Output of the First Demultiplexer 25 Empty Operation Unconditional Jump to Counter 170 by Incoming Asynchronous Input and First Level Multiplexer 8 Set First D-flip-flop 10.

Throwing in the JK flip-flop 12 will allow the operation of the comparison circuit, which before the second synchronization pulse arrives, evaluates whether the level written on the first D flip-flop 18 matches the level written on the second D flip-flop 11. circuit 15 of the logic product. In this case, the second synchronization pulse arrives at the input for the synchronous setting of counter 28 and the counter 28 writes the information 0 0 0 0 0 0 1 1 which is

1 3 5 7 5 β

now at the output of the memory 7. The highest bit of the address is memorized in the third D-flip-flop 13 and is written to the D-flip-flop with the rising edge of the second synehimpulse. The state of the third D-flip-flop 13 can only change again with the falling edge of the second synehro-pulse.

In this case, when the expected level was equal to the level on the 12th multiplexer 8 input, the program will continue from address 0 0 0 0 0 0 0 1 1. If the comparison circuit does not evaluate the level compliance, there is no 1 on the first circuit 15, with the rising edge, 1 is added to the address counter 20 and the program continues to execute, the instruction stored at address 0 0 0 0 0 0 '0 1 0. After the second synchronization pulse, the JK flip-flop 12 is reset with its falling edge. the function of the comparator circuit and at the same time the execution of other instructions is allowed. Blocking of other instructions while the jump instruction is executed is necessary so that the lower 8 bits of the jump address are not decoded as instructions.

The execution of the "pulse" and "flip-flop" instructions is clear from the diagram. To execute these instructions, the following conditions must be met:

1. The instruction code must match.

2. Jump instructions must not be performed.

3. There must be a synchronization pulse.

In the "flip-flop" instruction, the setting or dropping of the flip-flop is differentiated by bit # 5.

It is not necessary to use a buffer register at the output of the memory 7, since the use of conventional integrated circuits does not change the output information before 70 nS after the address change. The read from memory 7 is permanently enabled and the read information is only synchronized in control block 6. The flip-flops 10, 11 and 13 do not reset and change their state with each falling edge of the sync pulse. However, their state is only relevant when executing the jump instruction, i.e. when the JK-flip-flop 12 is started.

The controller according to the invention can also be used in some applications in measurement or process control. Furthermore, the controller can be used in the opposite function, that is, to imitate a computer channel, for example, to connect a line printer to mini- and microcomputers equipped with standard magnetic tape, which would allow this configuration to be used for off line printing of longer computer configurations.

Claims (2)

SUBJECT Controller for connecting peripheral devices to a computer, characterized in that it consists of receiving amplifiers (1) which are connected via a data bus and a control signal bus to an input bus decoder (3) whose data output is connected to a block (5) ) for connection to an auxiliary device which is connected to a register block (4), which is connected to transmit amplifiers (2J) by means of data buses and control signal buses, the input bus decoder (3), register block (4) and block (5) ) for connection to the auxiliary device are connected to a control block (6) which is connected to the memory (7). Controller according to claim 1, characterized in that the control block (6) consists of a multiplexer (8) whose address inputs are connected to the first to fifth setting inputs of the counter (20) and whose output is connected to the setting inputs of the first D- a flip-flop (10), the output of which is connected to a first input of the first logic equivalence circuit (14), the second input of which is connected to the output of the second D-flip-flop (11), the setting input of which is connected to the sixth setting input of the counter (20) and the output of the first logic equivalence circuit (14) is coupled to the first input of the first logic product (15J), the second input of which is connected to the output, and to the K-input of the JK-FLASH circuit (12) whose negated J-input is connected to the eighth setting input of the counter (20) and the output of the first logical product circuit (15) is connected to the negated first input of the third logical equivalence circuit (16) and to the first input of the second logical circuit (17) equivalents, the second inputs of which are connected to a generator (21), to which are further connected the synchronization input of the JK-flip-flop (12), through the inverter (9) the synchronization inputs of the first D-flip-flop (10J). 11j and a third D-flip-flop (13J) and second inputs of a second logic product (22), a third logic product (23) and a fourth logic product (24) whose first inputs are interconnected, the third inputs are connected to the seventh the counter input input (20), the fourth inputs being coupled to the eight counter counter input (20) and the fifth inputs of the third and fourth logic products (23 and 24 J) are connected to the sixth counter input input (20) and the second circuit output (22) ) of the logic product is connected to the input of information of the first demultiplexer (25), the output of the third circuit (23) of the logical product is connected to the input of demultiplexer (26J) and the output of the fourth circuit (24J logic product) is connected to the in219973 formation of the third demultiplexer (27), while the address inputs of the first, second and third demultiplexers (25, 26 and 27) are connected to the first to fifth counter inputs. 20), wherein the output of the third logical equivalence circuit (16) is connected to the counted pulse input of the counter (20), the output of the second logical equivalence circuit (17) is connected to the input for synchronous adjustment of the counter (20) and the output of the second logic equivalence circuit (17) is connected to a D-flip-flop (19) synchronization input with a set-up asynchronous input, and this set-up asynchronous input is connected to an output for transmission to the next row of counter (20); circuit (19) with setting asynchronous input connected to output of third D-flip-flop (13), the input is connected to the seventh adjustment input of the counter (20), while the individual outputs of the second demultiplexer (26) are connected to the adjustment inputs of the RS-flip-flops (28-59), to whose reset inputs the individual outputs of the third demultiplexer (27) are connected.