TWI245406B - Cascaded gate-driven ESD clamp - Google Patents

Abstract

A method is provided for semiconductor ESD protection in a mixed voltage device using cascaded gate driven NMOS clamp circuit. Used of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate-driven NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or ""core"" circuits.

Description

1245406 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to electrostatic discharge protection circuits, static lightning protection of moving discharge transistors. ㈣ 4 疋 There is a mechanism for using an electrostatic discharge protection circuit with a gate drive. . —Only included in integrated circuits using gold gas semi-techniques [Previous technology] The reliability of semiconductor circuits is increased in complexity and density in chip design, not to mention the circuit «link easy to receive The electrostatic discharge of snow that would damage the internal components and the electric material n μ pieces of coffee will mess with the fine Jiebei stomach-sunscreen tablets in Weizhong. Attached to-large circuits (such as: attached to susceptible to electrostatic discharge, so Electrostatic discharge protection is particularly important for maintaining semiconductor production, and commercial integrated circuits are usually expected to withstand electrostatic discharge (e.g., special body mode electrostatic discharge voltage). Will suffer ^ damage 1 ^ volt preparation (逋 often called people. Semiconductor components have become increasingly complex, and the circuit of simple components also & accommodates newer and more complex functions, due to interconnection The multi-round input voltage level has made the yuan shrink: the opportunity for Jingdian discharge to increase, and the other challenge is to protect the components: the second circuit's address, data and control lines are damaged by electrostatic discharge electric current. Power for body circuit And the dust level difference between the power supply pin bearing is electrically insulated, also makes the internal power supply from an external ^ # ...

; Although there may be a static electric circuit near the output pad of the integrated circuit, this kind of isolation is still used as an example of known methods of electrostatic discharge control in interface circuits that are more susceptible to electrostatic discharge damage. Disclosed in the following references: Yu Bai 0503-A30870TWF 5 1245406 N. Maene, published in 1992 by pr.ceecjings 〇fe〇S / ESD Symposium, "Inputs for Complementary Metal Oxide Half Circuits" Output and power supply electrostatic discharge protection (〇n

Chip Electrostatic Discharge Protections for Inputs, Outputs, and Supplies of CMOS Circuits) j; Professor Ke Mingxuan et al.

Reliability's "ESD Protection (ESD Pr〇tecti〇nt〇〇verc_ Gate <) xide on Digital-Analog, which overcomes the damage of the internal interlayer oxide layer of the digital / analog interface of a mixed-mode complementary metal-oxide semiconductor integrated circuit "Interface of Mixed-Mode CMOS 1C, s)"; "Complementary metal-oxide-semiconductor for multiple power supply pins" published by Professor Ke Mingdao and others in 1994 at PlOeeedings Qf EEE Intematial Integrated Reliability Workshop Integral Electrostatic Discharge Protection for Large-Scale Integrated Circuit Chips (Professor PrOtecti〇n 钿 CMOS VLSI / ULSI with Multiple Power Pins) j; Professor Ke Yuedao and others in 1997 at prOceedings 〇f Developed by CuSt〇m Integrated — uits fOnference, "Complementary Metal Oxide Semi-Mixed Mode Frequency Switch with Sub-micron Complementary Metal Oxygen Semi-Technology ^ Integral Electrostatic Discharge" sequel e_Chip which adds ecti〇n

Scheme for CMOS Mixed-Mode IC5s in Deep ^ Submicron CMOS Technology). " The / ESD protection circuit is designed to be stronger than other circuits in the semiconductor device. -The ESD protection circuit usually directs the ESD voltage and current to the path that is easier to conduct ESD electrical muscles; therefore, it can protect Other circuits are subject to electrostatic discharge. Generally speaking, the ESD protection circuit is located near the component interconnection pad. There are many well-known ESD protection circuit groups. This specification discusses the new construction of the conventional gate drive clamping circuit. Some conventional gate drive clamping circuits are disclosed in: C. Duwmy et al., U.S. Patent No. 4,855,62; C. Lien, U.S. Patent No. 5,086,365; C.K., et al. In 1992, Pingedings of Int_ti〇nal

Reliability

0503-A30870TWF 1245406

Physics Symposium published "Dynamic Gate Coupling 〇f nm〇S f〇r 〇utput ESD

Protection) "; C. Duwury," Achieving Uniform NMOS Deviee Povrar ", published in Technical Digest of International Elelctmn Device Meeting," Achieving Uniform NMOS Deviee Povrar " Disibibution for Submicron ESD Reliability ";

Proceedings of International Reliability Physics Symposium published `` ESD / ESD Reliability of Deep Submi_ Devie_ S.R_SWamy et al. ㈣〇f

"Capadtor_Coiipled ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ASIC" published by Symposi's Leg "Compatible ESD Protection Circuit for Deep-Submicron Low-Voltage Complementary Metal Oxide Semi-Specific Application Integrated Circuit"; Ke Mingdao, etc. U.S. Patent No. 5,631,793. When an electrostatic discharge occurs, the clamping circuit provides a current path from the input pad or power supply to the substrate bias supply (Vss, usually ground), green to another—circuit components that can absorb the static discharge current. In the traditional power supply In the clamping circuit, during normal operation of the circuit, the power supply line passes through-the clamping transistor that is dusty and close to the ground, and the circuit is clamped when a voltage exceeding the maximum allowable voltage is detected on the power supply line. It will conduct, and conduct the induced electrostatic discharge potential to the minimum, and reduce the '_ capacitance ionization c circuit). It can also make Wei Wei supply input to absorb the electrostatic power surge surge. Examples of such circuits are further described in In the following references: C. Duwrny in 1991 at pr〇ceedings

Physics S—The "Non-type Metal Gate Oxygen Half Dynamic Gate Coupling (Dynamic Gate Co-ng of View ⑶ f〇r Efficient 〇mput 0503-A30870TWF 7 1245406

Protection) "; C. Duwury," The Achieving Uniform Energy Distribution of N-type Metal-Oxygen Half-Elements to Improve the Reliability of Sub-micron Electrostatic Discharge (Achieving Unif.), Published at the Technical Digest of International Elelctron Device Meeting in 1992. mi Device p〇wer

Distribution for Submicron ESD Reliability) ";

S. Ramaswamy was in 1996 at the top gE Transactions of VLSI

Symposium's `` 帛 于 深 次 微 #Low House Complementary ^ Metal Oxygen Half 彳 Finding the Integrated Circuit Circuits, Private Valley Surfaces and ESD Protection Circuits (Capacit0r_C0upled ESD pr〇tecti〇n Circuk

Deep-Submicron Low-Voltage CMOS ASIC) ". As mentioned above, chip designs sometimes support multiple power levels. For example, one power level is provided to internal or core circuits and another power level is provided to external circuits. The pass-through level is based on the internal or core circuit of the chip design. For example,-the semiconductor process of the chip design can use 2.5 volts internally to generate other

J ,, and fr size and car driver low power consumption, however, the external interface of the chip may need an external compatible with L volts, so that the external interface of the chip accepts 3.3 volts driven interface depending on the application . a, Xi power supply level design will generate challenges of electrostatic discharge protection, these challenges are detailed in Ke Ming Yun Jiao et al. 2002 in IEEE J〇umal 〇fs〇lid_s 论 circ_ for heart Electrostatic discharge protection of CMOS complementary metal-oxide-semiconductor half-input buffers (Book Gat c D1S ^ ge Protecti〇nf〇r Μ · ν〇1 A framework 'can provide a method of electrostatic protection without experiencing the mixed description [Summary of the invention] The following disclosure is a clamping circuit that can meet the electrostatic discharge protection requirements of mixed voltage circuits. These embodiments include improved electrostatic discharge for mixed M integrated circuits. Protective circuit

0503-A30870TWF 1245406 ^ The projectile f will receive a higher power than the internal or core power source. The ESD protection circuit is oxidized with a single electrode ^ tiger. "There are actually more nuclear followers. The thick oxide layer of the second transistor is the same as the use of the layer. This is partly due to the book "thin-circuit". The single gate is oxidized into the component between the ground terminal and the circuit. VD33 is within the rated value of m. 'I The voltage applied to the two ends of these components is still in the component. One embodiment of the present invention uses a voltage-plus-gated drive-type metal oxide side circuit, to a series of Γ =! Γ and—A string can be detected. An electrostatic discharge makes ^ the biased circuit of a tandem orange circuit positively declared (following the sentence two or more ^ in the ^ _ position when it exceeds its normal operation. Bias input, the circuit port is triggered at ^ means «light _ circuit can be used, then the 3-sided level time design can use existing components to operate smartly to interfere with internal circuits, electrical and verified reliability. Two or more = provides design convenience ESD «clamping transistor in series in the protection circuit .'― In addition, the partial dust and electric dust can be conducted in various embodiments. In addition to providing the speed and reliability of the static lightning discharge of the dust mixing system, the application is provided. The secret driving clamp circuit is provided. When the power supply constructed using a single interlayer oxide layer is re-conducted, the construction of the electric protection circuit can have the smallest DC leakage circuit; the electrostatic discharge is used in the electrostatic discharge protection circuit. The traditional and guilty component configuration enables [Embodiment] Figure 1 shows the conventional idle-drive N-type metal-oxide half-thunder ⑽ using the gate-driven clamping technique to build the grasping circuit _, (through vss), and implement it here In the example, the electrostatic discharge prevention voltage source and the substrate voltage source are connected to the power supply shaft.

/, The source and the pole are connected to the substrate bias voltage source VSS

0503-A30870TWF 1245406 = ^ 2_ Road 145 includes-miscellaneous capacitors_delay, resistance capacitor time lag resistor 180 and capacitor 185, electrostatic discharge detection circuit 145 has 147 'connected to the power supply Long Yuan Jia and the substrate inspection voltage Source ^ s 6. , 145 L of the resistor-capacitor time-delay circuit of the resistance lion and capacitor 185, the electrostatic discharge circuit and the -p-type metal-oxide complex_body 2 The Vx of the 80% 185 interval delay circuit i, ^^ ^ ^ Is connected between the wheel ㈣6 and the common connection 197 of the N-type metal-oxygen half-buffered transistor and the gate of — = 电 ==. The capacitor of this embodiment is formed by _ = crystal, which The free pole is connected to the N-type metal-oxide-semi-buffered transistor ⑽ and a common terminal of a P 3L metal-oxide-semi-buffered transistor 195 to form an N-type metal-oxide-semiconductor with a capacitance m.

The sum electrode, the source electrode and the substrate are connected in common to an input port 147 connected to the substrate bias electric V detection circuit. Please quickly release, in the embodiment that Yu Di 1 is familiar with, the resistance 18 and the capacitor 185 are determined based on the delay time constant of about 0.1 to 1.0 milliseconds. The resistor-capacitor circuit 85 is used to detect the crossing of the griffon and Then, the electrostatic discharge of 30, the electrostatic discharge protection_metal oxide semiconductor transistor 110 is turned on quickly, and the electrostatic discharge voltage across VDD and VSS is clamped. Under normal (DC) operating conditions of the VDD / VSS level, the capacitor ⑻ is charged to the fresh position, so that the transistor is in an on state because of the high-voltage dragon, and the transistor is a low-voltage pole and is in a lake position. State, therefore, under normal conditions, the idler of the transistor is connected, and the substrate bias voltage _ VSS m, so that the static_protection transistor encounters a closed complaint, and the setting of the interval constant between the resistance ⑽ and the capacitance m ^ , So that it can quickly side static electricity, and can also be used to supply sufficient __ plum electric charge. Continuing to refer to Figure 1, when an electrostatic discharge occurs, the reverse phase formed by the transistor 190 and m can change the state, and quickly trigger the electrostatic discharge protection transistor ιι to reduce the electrostatic discharge sugar on the power line. With other sources of miscellaneous sources and 3G, this box circuit can also use file input, output, address line, and control line.

0503-A30870TWF 10 1245406 == works normally within the required limits, however, this traditional clamping circuit will fail in the mixed soil port. In the mixed pressure design, the pin positions of the internal yuan line and the control line Voltage. '~ ,, 4 are shown in the figure 2 of the example of the wheel-in, wheel-out, and address. Among them,-the electrostatic discharge protection circuit can be composed of components and parts of the circuit. : Clamp the circuit for electrostatic discharge protection, and implement the shot here, assuming the internal "^ VDD is ⑽ 特 '_ 路 2_, set the physical capacity of the Micro Motion ㈣ input: wave, for example: 3.3 volts on the power supply line on the side shown However, it is said that ^ 2 in the sun neck is limited to the specific M described. More specifically, the implementation now described "allows two voltage adjustments or unadjusted multi-voltage levels with different values." Electrostatic discharge protection circuit · Clear scale display __ Circuit diagram of the block diagram of the external 3.3 volt power supply for E, because the external coffee level is Finnau level, the main electrostatic discharge path of the clamping circuit 205 is between _ technology By pressing VSS, under normal operation, the control switch that is partially turned on is turned on. The supply can connect the source of transistor 207 to GM, usually at-the design voltage is less than half of VD33, making the transistor 2〇 The deviation of 7 will not exceed the direct voltage range. The switch m of the inverter part m will be normal. It works as a circuit breaker, which can prevent the existence of the channel between the source / drain of the transistor, the current path, and therefore close the transistor view. Its dirty pot transistor 2] 5 is controlled, and the transistor 215 is The pole is turned to VDD by the conducting switch, so that it can dissipate any current that may exist in the transistor 215 (_, and pull the pole between the transistor 208 to about 0 volts. When static discharge At the time of the occurrence, the opening and closing 206 of the control part 202 was designed to be open circuit, and the switch of the inverter part was broken to be on. At that point in time, due to the electrostatic discharge, Ga I had a high mine such as: Shen Volt), then The relative electric dust between the P-type metal-oxide-semiconductor 2M source and the substrate 'P-type metal-oxide-semiconductor 214 is equivalent to 0 volts. Through the p-type metal-oxide semi-transistor 2] 4,

0503-A30870TWF 11 1245406 The gates of the bodies 207, 208 are celebrated to a high voltage. The earthenware parts are turned on by the clamping transistors. The clamping transistors 207, 208 will then discharge the electrostatic discharge current from the milk bag charter field VD3. Lead to ground, this current conduction will further step into a certain ground, the main ground, Laoshan, body, I main ground, this current conduction will be further advanced. &Amp; strengthened 'where' _ parasitic double carrier interface The crystal (Mpoiar junction _istOT) is formed by a substrate or two transistors connected to a well region. At the same time, the 'resistance-capacitance circuit part 203 includes the resistance 21 ° and the capacitances 2 ι and 212, which can be touched! X inversion „Li’ 4 The two valleys are separated to provide a delay time constant to control the transistor ~ ”by providing These separated capacitors and biases can reliably provide a safe bias voltage to the transistors 214 and 215. During the constant interval between the capacitors provided by the series capacitors 2 ι, 212 and the capacitors provided by the resistors, the type of metal oxide is half. The transistor gate of the transistor is gradually pulled to a voltage level of \ ^, so the transistor 214 starts to _. During the delay time constant, the capacitor will be charged, and the gate of the metal oxide semi-transistor will be pulled. High and make the transistor gradually turn on. When transistor 214 is turned on and transistor 215 is turned on, the orange circuit including transistor Fan and 208 also starts to close. It should be noted that the setting of the delay time constant must be lower than Static discharge takes longer.

Figure 3 is a thin schematic diagram of the circuit. This circuit can be used to provide the above-mentioned mixed-voltage electrostatic discharge protection method. In the 3 W, the circuit is driven by a series-connected _type metal-oxygen semi-electrostatic discharge. Circuits' can provide electrostatic discharge protection in mixed voltage circuit design. 3% of the switches in the control section 302 include p-type metal-oxide semiconductors in floating μ wells. These switches are self-biased or self-controlled. We will only pass the high voltage above, but it will open the low voltage signal. Under normal circuit operation, the switch is self-biased and closed very effectively. Therefore, the electric 3G6 is also connected to its _ And biased to (in this embodiment, ^ volts temporarily) the floating N-type well 31 known as the positive circuit is biased by the p-type metal-oxide semiconductor transistor, 332 to the power supply, Therefore, the leakage current can be reduced or suppressed, and the transistor 9 is maintained in a closed state under a positive condition, because the VDD package of the transistor is removed (such as · "· 8 volts) relative to The source bias of its normal battle ^ (eg: M volts)

0503-A30870TWF 12 1245406 ^ Intimidation series __, the pole of the relying object, the ground of the transistor is kept closed during normal operation, and the box-made mine road is 30%; part 30) will not affect the normal Core or interface circuit operation. ^ (乂 and hanging from + P age oxygen semi-transistor __ is _ shoes-open state, and therefore, the common source-level power saving between transistor 314, in this embodiment is U volts), This kind of fibrillation metal oxide half body = body 3: for thinness, for the sake of making other partial platoons may make P-type metal oxygen semi-crystals into j

The effect of the higher external bias voltage VD33 (in this embodiment, 3rd Rihong J Wangkou P pass, thorough, .... inch), due to the transistor 307, The domain f depends on VDD. If they come into contact with Xiao Li and Ke Ke, they will still be dependent on the external power. It will still depend on the same gate oxide thickness of the core circuit. Electrostatic discharge protection circuit. The circuit design achieves mixed voltage compatibility by using serial connection = circuit operation. Each circuit element achieves mixed pressure compatibility. Similarly, weaving 315 rounds, capacitors 31 Jingzhu 15 idle pole straight 4 stars Protection, so that the voltage from the resistor 313 is blocked by the capacitor at a DC level. The two include-the resistor-capacitor time delay circuit 3G3, the resistor-capacitor time delay circuit must include-the resistor 313 and the capacitors 311, 312 The capacitor 3 ι is formed by an n-type metal-oxide-semiconductor crystal: its source and non-electrode are connected to the substrate, and the capacitor 312 is a p-type metal-oxide semi-crystal, and its impurities and secrets are connected to the substrate resistor. 313 and p-type money idle electrode 'these capacitors and resistors form a delay time constant (as mentioned in the description of Figure 2), With the setting range of 5 microseconds to U microseconds, the electrostatic discharge potential on the G-side power supply is maintained, and the money is delayed.-When-electrostatic discharge occurs at 3, VDD power is often relative to thousands of volts in Satoshi

The electrostatic discharge electric dust pulse (such as Zhejiang, Di, Li, equivalent to zero volts, self-biased or self-biased from 0503-A30870TWF 13 1245406: P-type metal-oxide semiconductor 306 will be _, and as a switch, they are equivalent to The circuit is broken, and the relatively low voltage on the gate of the metal oxide substrate 309 will turn on the transistor and penetrate the saki pole, which will effectively circuit the circuit. In addition, the p-type metal oxide semiconductor transistor 314 is the free electrode. 2 pairs of low-key (the delay time constant of 312 due to the resistance of the resistor and the electric fine, will maintain the lateral position of the surface at the beginning of static electricity), so that the transistor will be turned on, and the intermetallic type of metal-oxygen semi-electric These crystals will be very strong because of crystallography and marriage. Zhao Chunfang „flowed from lion to vss, as discussed in Figure 2, and the current on the substrate of the transistor interface will directly pass through the clamp. The element substrate of the crystal 307, effectively discharges the electrostatic discharge current. The two partial records provided to the clamping transistor 307, 3⑽ can be provided by the high level officer, which will not damage the circuit. The p-type gold Oxygen Semi-Electric Crystal Hours: two clamped transistors W, deleted and turned on, will be connected to ^ Θ w 309, 314, and 315 'to ensure that these transistors will not be damaged in the factory tank, although The connected components'-higher level series connection can be completed in a similar way, so that higher voltages can be used according to other needs. Valley 3 also provides-floating N-type well area, which is composed of transistor 331. And 332 provide power, and the power is also provided to protect the circuit when the device is Wei. When Wei is turned on, to avoid inspection, the secret of the original transistor in the zero-volt fresh position- If the potential of the transistor is first applied to the floating N-type well 31 () of 18 to 3.3 volts, the element will not be damaged. The floating N-type well area can provide a surface with two or more power on. Among them, the N-type Wei cage can be raised, with the surface electricity "on, the voltage drop across t will not fall on the P-type element relative to the _ well area substrate, which can be turned on =

The voltage of the core VDD core power supply is then completed by turning on the power supply of the coffee. This is the fresh position. VDD Wei Wei supply scale, the p-type pure semitransistor on the left side will be 0503-A30870TWF 14 1245406 turned on, and VDD will be connected to N-type well area voltage level. When VD33 is then turned on, the voltage applied to the right transistor 332 will be reduced and therefore turned on. Vd% will be applied to the floating n-type well area. At the same time, the left transistor The high voltage of the gate of 331 will turn off the p-type metal-oxide semiconductor transistor, thus preventing VDD from being connected to VD33 through the transistors 331 and 332. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. For example, Although the structure shown in the specific combination makes the transistor (p-channel and N-channel metal-oxide half-field effect transistor) in a certain combination, other transistors combined with other cranes can be used to complete this real blue, resistance and Capacitors can be wire elements or modified metal-oxide-semiconductor half-effect transistors, or integrated circuit elements that are formed separately, for example,-resistance can-active negative = transistor or deposition-vertical or clear plane complex or amorphous The unit phase is formed. Although the present invention has a specific bias configuration, other bias configurations can be designed without simplifying the circuit. There is an excessive voltage design. The type of the semiconductor element is a single-silk money intermetallic oxygen half element, or the semiconductor element can be formed using other element technologies, and a specific component can be added to or discharged from an electrostatic discharge circuit according to design requirements. For example, the external circuit ΓΓΓΓΓ is 3.3 volts, the power supply can be 5 volts and the Exin supply is 1.8 volts. In this way, a bias circuit with three inputs and a series circuit can be used. In addition, the circuit can pass through the architecture The correction wire is modified to make the internal core, the circuit is 3.3V, and the external voltage is 5 or 6V. Although the circuit of the hybrid electric discharge protection circuit and the internal or core circuit = crystal gate layer is described in the description China is formed in the same way, and the above benefits are also applicable to the protection circuit and other nuclear pathways. It is the same as that of Qian Qianjing_Chi === 明 书 崎 _, or when the patent asks the patent to find out. Explain it, or the non-gate connection of the metal-oxide semiconductor transistor. Shi Chengyuan

Invention ==: = Example after the coffee _ solution _ including any other than 0503-A30870TWF 15 1245406 · [Schematic description] Figure 1 shows a conventional N-type gold gate drive for electrostatic discharge protection Circuit diagram of oxygen half clamp. Figure 2 is a circuit block diagram of an electrostatic discharge protection circuit using a series-connected gate-driven N-type metal-oxide half-clamp circuit at a multi-voltage input. FIG. 3 is a schematic diagram of a circuit element constructing the circuit block diagram of FIG. 2. [Description of main component symbols] 100 ~ N type metal-oxide semi-electrostatic discharge protection circuit; 120 ~ VDD; 130 ~ VSS; 145 ~ ESD detection circuit; 146, 147 ~ input port; 180 ~ resistor; 185 ~ capacitor; 190 ~ N-type metal-oxygen half-buffered transistor; 195 ~ P-type metal-oxygen half-buffered transistor; 197 ~ common wiring; 200 ~ electrostatic discharge protection circuit; 202 ~ control part; 203 ~ resistance capacitor circuit part; 204 ~ inverter; 205 ~ clamping circuit; 206a ~ switch; 206b ~ switch; 207 ~ clamping transistor; 208 ~ clamping transistor; 209 ~ part of the switch; 210 ~ resistor; 211 ~ capacitor; 212 ~ capacitor 214 ~ metal oxide semitransistor; 215 ~ transistor; 300 ~ clamping circuit; 3 02 ~ control part; 303 ~ resistance capacitor circuit part; 305 ~ clamping part; 306a ~ switch; 307 ~ transistor; 308 ~ Transistor; 309 ~ transistor; 310 ~ floating N-type well; 311 ~ capacitor; 312 ~ capacitor; 0503-A30870TWF 16 1245406 313 ~ resistor; 314 ~ transistor; 315 ~ transistor; 331 ~ P-type gold oxide Semi-transistor; 332 ~ P type gold Oxygen semitransistor. 0503-A30870TWF 17

Claims (1)

1245406 10. Scope of applying for patents .. Panji ^ Electrostatic discharge anti-Wei road, between the first end of the frequency circuit, the electrostatic discharge protection circuit includes: a charge dissipating circuit, there is a surface-an input checker; According to the data, the charge flow received by the charge hybrid circuit by the domain hybrid is received from the 就 terminal to the other terminal. It also includes the electrostatic discharge protection circuit of the series-connected question-electrode drive as described in item 1 of the scope of the patent application, an electrostatic discharge side circuit connected to the inspection and control weaving circuit, where the electrostatic discharge circuit is ribbed. — = The test circuit of this partial coffee circuit is Gu Jing_Test === Discharge and assert more than one input. 3. The cascade-type static electricity-dissipating cake protection circuit as described in the item "Converting Fiber", two or three of the electrostatic discharge circuit is connected to the first and second ends, and is used to make when the first end is A huge amplitude is generated from time to time and a control signal is provided during electrostatic discharge as an indication of the detection of a huge voltage. 4 · As described in item 3 of Shenjing's patent scope, the series-connected gate-driven electrostatic discharge protection circuit, /, the partial 1: control% road inclusion_transistor off, according to miscellaneous records At least two of them are substantially electrically connected, and the two inputs can be substantially asserted together by the flip signal. 5. The electrostatic discharge protection circuit of the series-connected inter-electrode drive as described in item 4 of the stated patent, wherein the control signal substantially drives a gate of the transistor switch. 6 · As described in Shen Xianli Gu's 3rd series, driven electrostatic discharge protection circuit, the 8th circuit should also include a time delay circuit, which can work in conjunction with the bias control circuit to maintain The inputs are positively asserted for more than a specified time. 7. The series-connected ESD protection circuit as described in item 6 of the scope of patent application, 0503-A30870TWF 18 1245406, where ‘the time delay circuit is a resistance-capacitance time delay circuit. In the middle, section 1 describes the series-connected and pole-driven electrostatic discharge protection circuit: 该 The power supply circuit includes a clamp circuit. In Zhongzhong, the cascaded idle-pole-driven electrostatic discharge protection circuit described in ^ 8 of the siege, the metal oxide half and the metal oxide half below; The first terminal is connected to the order of the semi-battery ㈣ with its source and circuit patent series „9 series connection type _ crane's electrostatic discharge protection / / two upper and lower metal-oxide semi-transistor The source electrode and the non-electrode are connected to each other. The circuit, the two-phase 4-pole gate-driven electrostatic discharge protection described in item 2 and 2. The circuit breaker can include self-controlled _, which is U during electrostatic discharge. .As described in the scope of the patent application, the series-connected idle-pole-driven electrostatic discharge protection electricity, its scale self-controlling switch is formed in-or a plurality of floating N-type well area W-type electric version, which is specially designed to float. The potential of the N-type well area can rise with the electrostatic discharge, so that the p-type transistors can block a core supply voltage from being applied to its input. Μ, the electrostatic discharge protection circuit of the series-connected M-pole drive as described in item 2 of the application Θ, wherein the bias circuit includes a plurality of series-connected transistors, and uses the core power supply as Dust, so that the non-connected transistor will connect all voltages across the first and second terminals. 14. The electrostatic discharge protection circuit of the connected-type pole electrode drive as described in Item 6 of the patent application, wherein the 'time delay circuit includes a first time signal and a second time signal, the first time signal is used to The first person of these biased wheelers maintains positive electricity during the first specified time, the second time mm to maintain the second person who loses these biased voltages to maintain the positive power within the second specified time. Electrical claims. I5 · As described in item M of the scope of the patent application, the series-connected pole-driven electrostatic discharge protection electric 0503-A30870TWF 19 6% 24540% 21 where 'the first time signal is from the first time signal is from the first Two resistors and capacitors = driven by a capacitor time delay circuit, the 时间-resistor and capacitor time delay circuit is connected in series, and = ¾ is driven, and the first and second resistor-electrical delay circuits are all 1 Somewhere in between, what makes it. Stomach _ all electricity across the first and second ends of the money 16. A test circuit, mitral interface or nuclear; supply voltage and-higher or in-round supply 2 ^, electricity = ^ = 路 = LOW A core voltage node; H the bias circuit includes:-the wheel-in-wheel-out voltage; at least a floating reference voltage node; and-dual supply_, supply_reference_core-contact, the input wheel == The coffee gate includes: the reference voltage node is biased to the core to supply electric dust; and when the position is 'on', the floating moving == _ switch to control the wheel when the wheel is at a high level, moving the tea The voltage test point is dusty to the input and output power house. The net 17 · bias voltage as described in item 16 of the scope of the patent application is used to supply power to the input and output modules. The core supply is connected to the input and output nodes. Kasumi. 4 ★ ’The reference of this oceanic movement. 18_ The bias circuit as described in item 16 of the patent application. The supply switch is a P-type metal-oxide semiconductor transistor. 'Total round-in and round-out 19. The partial a circuit as described in item 18 of the scope of application for patents, wherein the p-type crystals form a secret _ N 财 _, and the N-type Wei includes the county's ^ 20. Such as The bias circuit according to item 16 of the patent application, wherein: P2. -A series-connected, put-to-make circuit, although the floating float-holding dragon section is provided for at least-a transistor to directly or indirectly drive the = crystal in the series-connected electrostatic discharge clamp circuit. The core or core of the electric 0503-A30870TWF 20 4 1245406 will be mixed age, the interface circuit is located in the lower supply of the circuit, γ, the higher or the input wheel out to supply electric dust, the bias method includes: h / Sub-moving reference voltage node; View the core power supply on the floating reference green node; LV R, etc. 4_ long enough to make the mixed age circuit test _ '. Power supply? Apply the input and output supply voltage to the polluted McCaw voltage node. ~ 22 · The bias method as described on page 21 of the scope of the patent application, wherein the floating reference voltage node receives the internal and external supply voltage through a -pair p-type metal-oxide semiconductor transistor, and the p-type metal-oxide One of the half-packed crystals transmits the internal supply voltage and is turned on when the external supply voltage is at a low level, and the other of the P-type metal-oxide semiconductors transmits the external supply voltage and the external supply voltage is Turn on at high level. 0503-A30870TWF 21