TWI244141B - Method of manufacturing a semiconductor device for reducing resistance of a CoSi2 layer - Google Patents

Abstract

A method of manufacturing a semiconductor device for reducing resistance of a CoSi2 layer is disclosed. First, a cobalt layer is formed on the silicon substrate, and two of the annealing treatments are conducted. The first annealing treatment is used for converting cobalt into a cobalt silicide (CoSi) layer. Next, a cap layer, about 1000 Å to 3000 Å thick, is formed on the CoSi layer, for the purpose of inhibiting re-growth of CoSi grains in the subsequent thermal processes. Then, the CoSi layer is converted into a CoSi layer by the second annealing treatment.

Description

1244141

[Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method capable of reducing the resistance value of a CoSi2 layer in a device. [Previous Technology] In the manufacturing process of semiconductor devices, electrical points such as gate electrodes, source electrodes, or drain electrodes on the interconnect are often used.

Forms a CoS i2 layer with low resistance. Generally speaking, the process of cobalt disilicide is to form a metal cobalt (Co) layer on a silicon-containing substrate, and then convert the cobalt to lead disilicide through two annealing treatments. Among them, the first thermal process is to first diffuse cobalt into a silicon-containing substrate to form a cobalt silicide (CoSi) layer. The second thermal process is to transform the cobalt silicide layer into a low-resistance cobalt disilicide, thereby reducing the resistance value of the device. Please refer to Figures 1 A to 1 D, which shows a second stone in a semiconductor device. The traditional manufacturing method of the starting layer. First, a silicon substrate 10 is provided, as shown in FIG. 1A. Source / inverted regions 12, gates 14, gate oxide layer 16, and sidewall spacers 18 have been formed on the Shi Xi substrate 1 〇 Then, in the following manner: A metal layer 20 is formed on the silicon substrate 10, as shown in FIG. 1B. Thereafter, a titanium or titanium nitride layer can be deposited on top of the metallic cobalt layer (not shown) to protect the metallic cobalt from oxidation. Then, the first thermal process is performed to transform part of the metallic cobalt layer 20

^ 1059 (050401) CRF.ptc Page 7 1244141 _ Case No. 92〗 127fi0_Year Month Day Rev. RL 5. Description of the invention (2) Form a cobalt silicide (CoSi) layer 22, as shown in Figure 1C. The remaining unreacted cobalt is designated as 20 A. Among them, the implementation temperature of the first thermal process is in the range of about 450 ° C to 55 ° C. After the first thermal process, the unreacted cobalt is removed by 20A °. Then, the second thermal process is performed, the temperature of which is higher than the temperature of the first thermal process, about 7 50 ° C ~ 88 0 ° C range to transform the cobalt silicide (CoS i) layer 22 into a cobalt disilicide (CoSi2) layer 23. Among them, the resistance of the CoSig layer 23 is very low, so the resistance of the gate, source, or drain can be reduced. However, during the second thermal process at a high temperature, the grains of the original cobalt silicide (CoSi) layer 22 will re-grow and form larger grains. CoSD with large size grains (coSD) will cluster more easily under the thermal pressure of the subsequent high-temperature process. This phenomenon is known as "agglomeration". Therefore, according to the above The traditional method will cause agglomeration of the cobalt disilicide layer and cause defects in the device. For example, as shown in Figure 1D, the surface of the formed cobalt disilicide layer 23 is very rough, or the surface of the discolored The large grains 232 pass through the source / drain region 12 and come into contact with the silicon substrate 10, or after the clusters of grains cannot form a continuous two-lithium oxide starting layer 23, a discontinuous region 231 is generated. In Figure 1D, the "rough 4k surface of the disilicide layer caused by the clumping phenomenon" will reduce the flatness of the first petrified layer 23, and then affect the flatness of subsequent layers deposited on top. Flat (unevenanessj In addition to the surface appearance of a cobalt silicide layer 23, there is also an uneven interface between the cobalt silicide layer 23 and the source / drain region 12. If an insulating dielectric layer is used, A contact hole

Worse. So 'how to make the formed people work for one of the important goals. 92112760 e) (not shown) The cobalt silicide layer 2 3 is over-etched and breaks the large crystals of the substrate 10 cobalt. When the voltage is a resistance value due to the clustering of the grains, the cobalt silicide layer 2 3 is more flat, It is actually case No. 1244141. V. Description of the invention (3) (contact ho 1 is not flat. The silicon substrate 10 is in contact. In the contact hole, if the two fossil substrates 10 are in contact with leakage. In addition, two The defects described in the cobalt silicide layer 2 3 will become even more confusing after the second, and there will be a risk that the etching will not be refined with cobalt silicide. Once in contact, leakage particles 232 will pass through the source / apply to the semiconductor element. The discontinuity generated and the subsequent performance of the element is etched through a subsequent series of correction layers 23 is controlled, and the hole and the silicon substrate 10 are electrically connected. Then > and the pole region 12 and the component, It will also cause the area 231 to increase and cause an impact. And the research and development of a high-temperature thermal process [invention] In view of this, the purpose of the present invention is to provide a method for manufacturing a disilicide starting layer in a semiconductor device to increase a cobalt disilicide layer The flatness of According to the purpose of the present invention, a manufacturing method for reducing the resistance value of a cobaltite silicide layer in a semiconductor device is provided. First, a silicon substrate is provided and a cobalt layer is formed. ) On a silicon substrate. Next, a first annealing process is performed to form a CoS i layer, and unreacted metal lead is removed by selective engraving. Then, forming A cover layer (cap 1 ayer) is on the cobalt silicide layer to prevent the cobalt silicide grains from agglomerating in the subsequent high-temperature process. Then, a second annealing treatment is used to transform the fragmented junction layer into

™ 〇59 (〇5〇401) CRF.ptc Page 9 1244141 _Case No. 92112760 Car Month Day Amendment V. Description of the invention (4) 'CoSi? Layer. According to the present invention, the cover layer is, for example, a silicon oxide layer or a silicon nitride layer. The thickness of the cover layer is in the range of 100A to 300A. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, the preferred embodiments will be described in detail below, and will be described in detail with reference to the accompanying drawings. [Embodiment] Please refer to FIGS. 2A to 2E, which illustrate a manufacturing method for reducing the resistance value of a cobalt disilicide layer in a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 2A, the first & siHcon substrate 10 is provided. The source / drain region 12 is formed on the Shixi substrate 10 'according to a conventional method to define a channel region. The gate electrode 14 is mainly made of polycrystalline silicon, is formed in the channel region, and is located above a gate oxide layer 16. The sidewall spacer (sidewal 1 s p a c e r) 1 8 is made of silicon oxide, for example, and can be formed on both sidewalls of the gate electrode 14. Next, as shown in FIG. 2B, a metal cobalt layer 20 is formed on the silicon substrate 10, and the metal cobalt layer 20 covers the gate electrode 14. The metallic cobalt layer may be formed by a sputtering method. Thereafter, a titanium layer or a titanium nitride layer may be deposited on the metal cobalt layer 20 (not shown in the figure) to protect the metal diamond from oxidation.

TW1059 (050401) CRF.ptc Page 10, 1241141, January 10, 2014. _ Case No. 92112760 V. Description of the Invention (5) Then 'as shown in Figure 2C, the first thermal annealing treatment (f 丨 rst annealing treatment), A part of the metallic cobalt layer 20 is transformed into a silicon silicide (CoS i) layer 22. Substrates containing silicon components, such as silicon substrates and gates 14, will react with metal drills and consume a portion of the silicon. The remaining unreacted cobalt is labeled 20A. Among them, the implementation temperature of the first thermal process is in the range of 45 ° to 550 ° C, and the execution time is about 30 seconds to 90 seconds. Next, unreacted cobalt 20a is removed and an important step of the present invention is performed. As shown in FIG. 2D, a cap layer 24 is formed above the silicide junction layer 22. The cover layer may be a silicon oxide layer, a silicon oxide layer, or a silicon nitride layer. The thickness of the cover layer is about 1000A to 300A. The range is preferably about 2000 A. Then, as shown in FIG. 2E, a second annealing process is performed to transform the cobalt silicide (^; 〇8 丨) layer 22 Into a cobalt silicide (joSi'2) layer 26. The temperature of the second thermal process is higher than the temperature of the first thermal process, which is about 75 (PC ~ 88 ot range, the implementation time is about 30 seconds) ~ 90 seconds. After the CoSi2 layer 26 is formed, the cover layer can be removed or left 'depending on process requirements'. There is no particular limitation. In this case, the cover layer 2 4 Physically suppress the cobalt silicide (cosi) grains, making it impossible to re-aggregate (re-gr0w) during the second thermal process, even if the component undergoes the thermal pressure of subsequent-a series of high-temperature processes, Easy to group two. The cobalt silicide formed by V in accordance with the manufacturing method of the present invention is a tin knife, which solves the traditional process smoothly.

1244141

Questions such as: Cobalt disilicide layer with rough surface, or excessively large cobalt disilicide grains piercing the source / drain region and coming into contact with the silicon substrate 10, or discontinuity of the cobalt disilicide layer after the grains are clustered, etc. Many defects can be avoided. In addition, the manufacturing method for reducing the resistance of cobalt disilicide of the present invention can be applied to any process that requires the formation of cobalt disilicide on a silicon-containing substrate. The resistance test is performed on the manufactured components as follows. Resistance test (R e s s t a n c e T e s t) The test element includes two groups of samples. The series of measurement results of sheet resistance (s h e e t resistance, Rs) are shown in Table 1. Among them, sample a is a sample prepared according to the manufacturing method of the present invention (as shown in Figs. 2A to 2E), and includes a cover layer. Sample B is a sample made according to the traditional manufacturing method (as shown in Figures 1 A to 1D), without a cover layer. Table 1 Resistance value (Rs) Maximum value Minimum standard deviation Sample (Mat.) (Min.) (Mean) (Std%) A (with f cap) 8.621 7.237 7.880 6.870 B (without cap) 18.480 12.090 14.630 11.900 First, sample A (as shown in Figure 2E) and sample B (as shown in Figure 1D) are annealed at a high temperature of 9 50 ° C for 3 60 seconds. Then, the respective sheet resistance values are measured. Measurement results show: 6 spoons of sample A (with cover)

TW1059 (050401) CRF.ptc Page 12 1244141 Case No. 92112760

V. Description of the invention (7) The average sheet resistance value is only about sample B (half without cover layer (7.88 M4.630). Therefore, the sample A produced by testing the junction / average sheet resistance value method has the cover layer: Month 'according to the rise of the current value.' Resistance sheet resistance M n ^ t, sample A with a cover layer has not been tempered at 950 ° C for 360 seconds. The resistance value of H is about 6.6. Compared with the high-temperature tempered :: resistance value of 7.8M, the sheet resistance value of the sample A after tempering is not equal to the plus. Therefore, according to the manufacturing method of the present invention Sample A with a cover layer can indeed increase the thermal properties of the cobalt disilicide layer. Φ ^ Hall description 'Although the present invention has been disclosed as above with a preferred embodiment, then Γ :: Limits the present invention, anyone skilled in this art, in Without departing from the scope of the present invention; 2: The range Θ can be modified and retouched in various ways, so this " /, Qianganwei shall be determined by the scope of the attached patent application.

TW1059 (050401) CRF.ptc Page 13 1241441 Case No. 92112760 Brief description of revised drawings [Simplified illustration of drawings] Figures 1 A to 1 D show a traditional manufacturing method of a cobalt silicide layer in a semiconductor device; And FIGS. 2A to 2E illustrate a manufacturing method for reducing the resistance value of the cobalt silicide layer in a semiconductor device according to a preferred embodiment of the present invention. Description of reference numerals 10 · Broken substrate 1 2: Source / drain region 14: Gate 16: Gate oxide layer 18: Side wall spacer 20: Metal cobalt (Co) 2 0 A: Unreacted cobalt 22: Silicide Cobalt (CoSi) layers 23, 26: CoSi2 layer 24: Cover layer 2 3 2: Large two cobalt silicide grains 2 3 1: Discontinuous area of the disilicon drill layer TW1059 (050401) CRF .ptc Page 14

Claims (1)

1244141 __9211 ^ 700 year 1 case 6. Application for Lai Fan * ^ 'The implementation temperature of a thermal process is about 4 $ 〇 ~ 5 5 ℃. 8. The manufacturing method described in item 7 of the scope of patent application, wherein the execution time of the first thermal process is in the range of 30 seconds to 90 seconds. ', 9 · The manufacturing method as described in item 1 of the scope of patent application, wherein the implementation temperature of the second thermal process is about 75 (rc ~ 88 (TC range.) 10., as described in item 8 of the scope of patent application In the manufacturing method, the execution time of the second thermal process is in the range of 30 seconds to 90 seconds. 11. The manufacturing method described in the first item of the patent application scope, wherein the first thermal process is being implemented. Before the manufacturing process, a titanium layer is formed above the metallic cobalt layer. 〇1 2 · The manufacturing method described in the first item of the scope of patent application, wherein before the far first thermal process is performed, the metal is first started. A titanium nitride layer is formed above the layer. 1 3. The manufacturing method as described in item 1 of the scope of patent application, wherein the cover is removed after the Shixihua starting layer is transformed into the cobalt disilicide layer. 14. A manufacturing method for reducing the resistance value of a two-layered starting layer in a semiconductor device, comprising the steps of: providing a substrate; forming a cobalt layer on the substrate; At the first heating temperature Heating, turning the metal layer into a cobalt silicide (CoSi) layer; removing an unreacted metal cobalt layer remaining on the cobalt silicide layer by selective etching; forming a cap layer on the Above the cobalt silicide layer, the overlay TW1059 (050726) CRF.ptc Page 16 1241441 ------ Case No. 92112760_year a month amendment ____ Sixth, the scope of the patent application covers the thickness of the cover layer is between 100 and 300 Å, and the coverage The material of the layer is silicon oxide or silicon nitride; and the element is heated at a second heating temperature to transform the cobalt silicide layer into cobalt silicide (CoSi2). )Floor. 15. The manufacturing method according to item 14 of the scope of patent application, wherein the thickness of the cover layer is preferably about 2000 A. 16. The manufacturing method according to item 14 of the scope of patent application, wherein the second heating temperature is higher than the first heating temperature. 17. The manufacturing method as described in item 14 of the scope of the patent application, wherein the first heating temperature is in a range of about 450 ° C to 55 ° C. 18. The manufacturing method according to item 17 in the scope of the patent application, wherein the heating step of converting the metallic cobalt layer into the cobalt silicide layer is performed for about 30 seconds to 90 seconds. 19. The manufacturing method as described in item 14 of the scope of patent application, wherein the second heating temperature is in a range of about 750 ° C to 880 ° C. 20. The manufacturing method according to item 19 of the scope of patent application, wherein the heating step of transforming the cobalt silicide layer into the cobalt disilicide layer is performed for about 30 seconds to 90 seconds. 21. The manufacturing method according to item 14 of the scope of application for a patent, wherein after the step of forming the metallic cobalt layer, a titanium layer or a titanium nitride layer is further formed over the metallic cobalt layer ( titanium nitride layer) 〇 TW1059 (050726) CRF.ptc Page 17 1241441 Case No. 92112760 Amendment VI. Patent Application 22. The manufacturing method as described in Item 14 of the Patent Application, wherein after the cobalt silicide layer is transformed into the cobalt disilicide layer To remove the overlay. TW1059 (050726) CRF.ptc Page 18