CN116344364A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN116344364A CN116344364A CN202310631093.7A CN202310631093A CN116344364A CN 116344364 A CN116344364 A CN 116344364A CN 202310631093 A CN202310631093 A CN 202310631093A CN 116344364 A CN116344364 A CN 116344364A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 178
- 239000000758 substrate Substances 0.000 claims abstract description 139
- 239000002184 metal Substances 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 239000011241 protective layer Substances 0.000 claims abstract description 96
- 238000002360 preparation method Methods 0.000 claims abstract description 36
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 230000002829 reductive effect Effects 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- -1 region Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The application provides a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: first, a base including a substrate and a gate structure on the substrate is provided; then, forming a preparation metal layer and a protection layer which are sequentially stacked on the exposed surfaces of the substrate and the grid structure to obtain the preparation structure, wherein the protection layer is provided with preset elements, and the proportion of the preset elements in the protection layer is gradually increased along the direction of the protection layer away from the substrate and the grid structure; finally, a predetermined treatment is performed on the preliminary structure such that the preliminary metal layer forms a metal layer, the predetermined treatment including an annealing treatment. The proportion of the predetermined elements is gradually increased along the direction of the protective layer away from the substrate and the gate structure, so that the stress of the protective layer is reduced, the quantity of the elements in the metal layer diffused into the substrate is reduced, the problem that the performance of the semiconductor device is poor due to the stress of the protective layer in the prior art is solved, and the good performance of the semiconductor device is ensured.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
The prior metal silicide process mainly comprises the following steps: metal coating deposition, tiN protection structure deposition and rapid thermal annealing (Rapid Thermal Processing, RTP for short), wherein the TiN protection structure has the advantages of protecting the metal coating and inhibiting an interface oxide layer.
As shown in fig. 1, the current semiconductor structure mainly includes a silicon substrate 200, a dielectric layer 300, a metal gate 400, a metal cap layer 500 and a TiN protection structure 600, wherein the dielectric layer 300 and the metal gate 400 are located on a part of the surface of the silicon substrate 200, the metal cap layer 500 covers the surface and the side surfaces of the silicon substrate 200, the dielectric layer 300 and the metal gate 400, and the TiN protection structure 600 covers the surface of the metal cap layer 500. However, since the TiN protection structure 600 has a stress problem, the TiN protection structure 600 may squeeze the metal cap layer 500, so that the elements in the metal cap layer 500 diffuse into the silicon substrate 200, causing transitional silicidation of source and drain regions, and further causing defects in the device, and the elements in the metal cap layer 500 diffuse into the silicon substrate 200, which may cause shorting of source and drain regions, and even leakage, thereby affecting the performance of the device.
Therefore, how to solve the stress problem of the protection layer to improve the performance of the device is a problem to be solved at present.
Disclosure of Invention
The main objective of the present application is to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem in the prior art that the performance of the semiconductor device is poor due to the stress of the protective layer.
According to an aspect of an embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: providing a substrate, wherein the substrate comprises a substrate and a gate structure positioned on the substrate; forming a preparation metal layer and a protection layer which are sequentially stacked on the exposed surfaces of the substrate and the gate structure to obtain a preparation structure, wherein the protection layer is provided with preset elements, and the proportion of the preset elements in the protection layer is gradually increased along the direction of the protection layer away from the substrate and the gate structure; and performing a predetermined process on the preliminary structure so that the preliminary metal layer forms a metal layer, wherein the predetermined process comprises an annealing process.
Optionally, forming a preliminary metal layer and a protective layer sequentially stacked on the exposed surfaces of the substrate and the gate structure to obtain a preliminary structure, including: forming the preparation metal layer on the exposed surfaces of the substrate and the gate structure; and forming the protective layer on the exposed surface of the preparation metal layer far away from the substrate by using a preset process, introducing preset gas into a reaction chamber in the process of forming the protective layer, and controlling the flow of the preset gas to gradually increase, wherein the preset process comprises a sputtering process, and the reaction chamber contains the substrate and the structure formed by the preparation metal layer.
Optionally, the predetermined gas is nitrogen.
Optionally, the step of performing a predetermined process on the preliminary structure so that the preliminary metal layer forms a metal layer includes: and carrying out the annealing treatment on the preparation structure, so that the preparation metal layer reacts with the substrate through the annealing treatment and forms the metal layer.
Optionally, the step of providing a substrate comprises: providing the substrate, the preparation gate oxide layer and the preparation gate electrode which are sequentially stacked; and removing part of the preparation gate oxide layer and part of the preparation gate electrode, exposing part of the substrate to obtain the base, forming a gate oxide layer by the rest of the preparation gate oxide layer, and forming a gate by the rest of the preparation gate electrode.
Optionally, the material of the protective layer includes TiN, and the predetermined element includes nitrogen.
Optionally, the thickness of the protective layer ranges from 1nm to 50nm, and the ratio of the predetermined element in the protective layer ranges from 20% to 70%.
Optionally, the material of the preliminary metal layer comprises NiPt, the material of the substrate comprises Si, and the material of the metal layer comprises Ni x Si y 。
According to another aspect of the present application, there is also provided a semiconductor device including a base, a metal layer, and a protective layer, wherein the base includes a substrate and a gate structure on the substrate; the metal layer is positioned on the surface of the substrate and the gate structure; the protective layer is positioned on the surface of the metal layer, which is far away from the substrate, wherein the protective layer is provided with a preset element, and the proportion of the preset element in the protective layer is gradually increased along the direction of the protective layer, which is far away from the substrate and the grid structure.
Optionally, the gate structure includes a gate oxide layer and a gate, wherein the gate oxide layer is located on a portion of a surface of the substrate; the gate electrode is located on a surface of the gate oxide layer remote from the substrate.
By applying the technical scheme, the substrate and the base of the gate structure are provided, the prepared metal layer and the protective layer which are sequentially stacked are formed on the exposed surfaces of the substrate and the gate structure, the stress of the protective layer is reduced due to the fact that the proportion of the predetermined element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure, and the quantity of the element in the metal layer diffused into the substrate is reduced due to the fact that the stress of the protective layer is reduced, the problems that in the prior art, due to the fact that the element in the metal layer is diffused into the substrate, source-drain regions in the substrate are short-circuited and electric leakage are caused are solved, the problem that in the prior art, the performance of a semiconductor device is poor due to the stress of the protective layer is solved, and the performance of the semiconductor device is guaranteed to be good.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a schematic structure of a semiconductor device of the prior art;
fig. 2 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 3 shows a schematic structural diagram of a semiconductor device after providing a substrate, a preliminary gate oxide layer, and a preliminary gate according to an embodiment of the present application;
FIG. 4 shows a schematic structural view of a substrate according to an embodiment of the present application;
FIG. 5 shows a schematic structural diagram of a preliminary structure according to an embodiment of the present application;
fig. 6 shows a schematic structural diagram of a semiconductor device after an annealing treatment according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. preparing a metal layer; 30. a protective layer; 40. preparing a structure; 50. a metal layer; 101. a substrate; 102. a gate structure; 103. preparing a gate oxide layer; 104. a preliminary gate; 105. a gate oxide layer; 106. a gate; 200. a silicon substrate; 300. a dielectric layer; 400. a metal gate; 500. a metal cover layer; 600. TiN protection structure.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in order to solve the problem that the performance of the semiconductor device is poor due to the stress of the protective layer in the prior art, in an exemplary embodiment of the present application, a method for manufacturing the semiconductor device and the semiconductor device are provided.
According to an exemplary embodiment of the present application, a method of fabricating a semiconductor device is provided.
Fig. 2 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
step S201, as shown in FIG. 4, a base 10 is provided, wherein the base 10 includes a substrate 101 and a gate structure 102 on the substrate 101;
step S202, as shown in fig. 5, of forming a preliminary metal layer 20 and a protective layer 30 sequentially stacked on exposed surfaces of the substrate 101 and the gate structure 102, to obtain a preliminary structure 40, wherein the protective layer 30 has a predetermined element, and a ratio of the predetermined element in the protective layer 30 gradually increases along a direction of the protective layer away from the substrate and the gate structure;
specifically, the above-mentioned duty ratio is a duty ratio of the content of the above-mentioned predetermined element in the above-mentioned protective layer.
In step S203, as shown in fig. 5 to 6, the preliminary structure 40 is subjected to a predetermined process, including an annealing process, so that the preliminary metal layer 20 forms the metal layer 50.
In the method for manufacturing the semiconductor device, firstly, a substrate comprising the substrate and a grid structure arranged on the substrate is provided; then, forming a preliminary metal layer and a protective layer which are sequentially stacked on the exposed surfaces of the substrate and the gate structure to obtain a preliminary structure, wherein the protective layer is provided with a predetermined element, and the ratio of the predetermined element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure; finally, the preliminary structure is subjected to a predetermined process, which includes an annealing process, so that the preliminary metal layer forms a metal layer. Compared with the problem of poor performance of a semiconductor device caused by stress of a protective layer in the prior art, the manufacturing method of the semiconductor device of the application solves the problem of poor performance of the semiconductor device caused by stress of the protective layer in the prior art by providing the substrate comprising the substrate and the substrate of the gate structure and forming the preparation metal layer and the protective layer which are sequentially stacked on the exposed surfaces of the substrate and the gate structure, wherein the proportion of the preset element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure, so that the stress of the protective layer is reduced, and the quantity of the element in the metal layer diffused into the substrate is reduced due to the stress reduction of the protective layer, thereby avoiding the problem of source-drain region short circuit and electric leakage in the substrate caused by the diffusion of the element in the metal layer into the substrate in the prior art, solving the problem of poor performance of the semiconductor device caused by stress of the protective layer in the prior art, and ensuring good performance of the semiconductor device.
In the prior art, under the condition that the element proportion in the protection layer is uniform, the stress of the protection layer is larger, and the protection layer presses the metal layer, so that the element in the metal layer is diffused to a source region and a drain region in the substrate, the channel region of the semiconductor device is shorter, the source drain region is short-circuited and even leaked, the performance of the semiconductor device is poorer, in the manufacturing method of the semiconductor device, the stress of the protection layer is smaller, the influence of the protection layer on the pressing of the metal layer is smaller, the number of the metal layers is further reduced, and the number of the metal layers in the semiconductor device is further reduced, namely the defect number of the metal layers in the semiconductor device is further reduced, because the proportion of the predetermined element in the protection layer increases along the direction of the protection layer away from the substrate and the gate structure, namely the proportion of the predetermined element in the substrate and the gate structure is relatively larger, and the element in the protection layer is separated from the substrate and the gate structure because of the proportion of the predetermined element is smaller, the stress of the protection layer is smaller, and the protection layer is less influenced on the metal layer is further influenced, and the number of the metal layers in the semiconductor device is further reduced.
In addition, the protective layer can protect the metal layer to avoid oxidation of the metal layer, on the other hand, due to the existence of the protective layer, the probability of diffusing elements in the metal layer into the substrate is ensured to be smaller, on the other hand, due to the oxygen-philic characteristic of the protective layer, the protective layer is facilitated to absorb oxygen remained at the interface between the metal layer and the substrate, the existence of an interface oxidation layer is restrained, and the better performance of the semiconductor device is further ensured.
Of course, since the ratio of nitrogen in the predetermined element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure, that is, the ratio of Ti in the other element in the protective layer is gradually decreased along the direction of the protective layer away from the substrate and the gate structure, the ratio of Ti near the substrate and the gate structure is relatively large, and the wettability of the other Ti and the metal layer is relatively good, so that the connectivity between the protective layer and the metal layer is relatively good, in addition, the Ti can also better adsorb oxygen between the metal layer and the substrate, so that the interface oxide is reduced, and the performance of the semiconductor device is further ensured to be relatively good.
In order to further ensure better performance of the semiconductor device, according to an embodiment of the present application, a preliminary metal layer and a protective layer are formed on the exposed surfaces of the substrate and the gate structure, where the preliminary metal layer and the protective layer are sequentially stacked, to obtain a preliminary structure, including: as shown in fig. 5, the preliminary metal layer 20 is formed on the exposed surfaces of the substrate 101 and the gate structure 102; the protective layer 30 is formed on the exposed surface of the preliminary metal layer 20 away from the substrate 101 using a predetermined process including a sputtering process, and a predetermined gas is introduced into a reaction chamber accommodating the structure formed by the base 10 and the preliminary metal layer 20 during the formation of the protective layer 30 and the flow rate of the predetermined gas is controlled to be gradually increased. The preparation metal layer is formed on the exposed surface of the substrate and the gate structure, the protection layer is formed on the exposed surface of the preparation metal layer far away from the substrate through the preset process, and the flow of the preset gas which is introduced into the reaction chamber is gradually increased in the forming process of the protection layer, so that the proportion of the preset element in the formed protection layer is increased along the direction of the protection layer far away from the substrate and the gate structure, the stress of the protection layer is further ensured to be smaller, the diffusion of the metal layer into the substrate is avoided, the problems of short circuit and electric leakage of a source region and a drain region in the substrate due to the diffusion of the element in the metal layer into the substrate in the prior art are solved, namely the problem of poor performance of a semiconductor device due to the stress of the protection layer in the prior art is solved, and the performance of the semiconductor device is further ensured to be better.
In a specific embodiment, the predetermined process includes PVD (Physical Vapor Deposition ), and the protective layer may be formed by CVD (Chemical Vapor Deposition ).
Specifically, the sputtering temperature in the above sputtering process ranges from 200 degrees to 280 degrees.
According to another embodiment of the present application, the predetermined gas is nitrogen. The predetermined gas is nitrogen, and the predetermined element is nitrogen, that is, the ratio of the nitrogen is gradually increased along the direction away from the substrate and the gate structure, so that the stress of the protective layer is further ensured to be smaller, and the performance of the semiconductor device is further ensured to be better.
According to another embodiment of the present application, the step of performing a predetermined process on the preliminary structure to form a metal layer on the preliminary metal layer includes: as shown in fig. 5 to 6, the preliminary structure 40 is subjected to the annealing treatment, so that the preliminary metal layer 20 reacts with the substrate 101 through the annealing treatment and the metal layer 50 is formed. By carrying out the annealing treatment on the preparation structure, the preparation metal layer can react with the substrate, the metal layer can be obtained more simply, and the manufacturing process of the semiconductor device is simpler.
According to a specific embodiment of the present application, the step of providing a substrate comprises: as shown in fig. 3, the substrate 101, the preliminary gate oxide layer 103, and the preliminary gate 104 are provided to be stacked in this order; as shown in fig. 3 to 4, a part of the preliminary gate oxide layer 103 and a part of the preliminary gate 104 are removed, so that a part of the substrate 101 is exposed, thereby obtaining the base 10, the remaining preliminary gate oxide layer 103 forms a gate oxide layer 105, and the remaining preliminary gate 104 forms a gate 106. By providing the substrate, the preliminary gate oxide layer and the preliminary gate electrode which are sequentially stacked, and removing part of the preliminary gate oxide layer and part of the preliminary gate electrode, the substrate can be obtained more simply, and the manufacturing process of the semiconductor device is further ensured to be simpler.
According to another embodiment of the present application, the material of the protective layer includes TiN, and the predetermined element includes nitrogen.
Specifically, the material of the protective layer is TiN, the predetermined element is nitrogen, and because Ti is an oxygen-related element, the protective layer can adsorb oxygen remained at the interface between the metal layer and the substrate, so that the existence of an interface oxidation layer is inhibited, and the better performance of the semiconductor device is further ensured.
According to a further embodiment of the present application, the thickness of the protective layer ranges from 1nm to 50nm, and the ratio of the predetermined element in the protective layer ranges from 20% to 70%.
Specifically, the content of the predetermined element in the protective layer is in the range of 20% to 70%.
In a specific embodiment, in the predetermined process, the flow rate of the predetermined gas nitrogen ranges from 20sccm to 100sccm.
According to one embodiment of the present application, the material of the preliminary metal layer includes NiPt, the material of the substrate includes Si, and the material of the metal layer includes Ni x Si y 。
Specifically, in the manufacturing process of the semiconductor device, a gradient is mainly formed by the nitrogen element in the protection layer, the element occupation ratio of the protection layer in the prior art is relatively uniform, namely, the element occupation ratio difference in the TiN layer is smaller, so that the wettability of the protection layer and the metal layer NiPt is poorer, namely, the contact property of the protection layer and the metal layer is poorer, in the manufacturing process of the semiconductor device, the corresponding problem is solved by adopting the TiN gradient, on one hand, the TiN of the protection layer close to the preparation metal layer NiPt has lower N content and higher Ti content, namely, the protection layer and the preparation metal layer can be better adhered due to the attraction effect of Ti and the metal layer; on the other hand, the Ti content in the protective layer close to the metal layer is higher, so that oxygen existing between the metal layer NiPt and the substrate Si can be better absorbed, and the existence of an interface layer oxide is reduced; on the other hand, in the prior art, as the protective layer TiN covers the grid electrode and the source drain region, the grid electrode and the source drain region are not at the same height, and are of a vertical hillock structure, so that the stress at the two end regions of the grid electrode is larger, the metal layer NiPt of the side wall can move to the source drain region, so that the source drain region is excessively silicided to cause short circuit and electric leakage, and the semiconductor of the application can better even the stress due to the characteristic of the protective layer TiN gradient material, so that the problem that the metal layer moves to the source drain region and the source drain region is avoided, and the performance of the semiconductor device is further ensured to be better.
In addition, in the nickel-silicon process, ni is a main diffusion element, if the protective layer TiN is not arranged, nickel on the side wall and the shallow trench isolation table is easy to diffuse into the source and drain regions, nickel silicide on the edge of the source and drain regions is too thick, short circuit and electric leakage are caused, and the semiconductor device of the application has the advantages that the stress of the protective layer is small, the nickel on the side wall and the shallow trench isolation table is prevented from diffusing into the source and drain regions, and the better performance of the semiconductor device is further ensured.
There is further provided, according to an embodiment of the present application, a semiconductor device, as shown in fig. 6, the semiconductor device including a base 10, a metal layer 50, and a protective layer 30, wherein the base 10 includes a substrate 101 and a gate structure 102 on the substrate 101; the metal layer 50 is located on the surface of the substrate 101 and the gate structure 102; the protective layer 30 is located on a surface of the metal layer 50 away from the substrate 10, wherein the protective layer 30 has a predetermined element therein, and a ratio of the predetermined element in the protective layer 30 gradually increases along a direction of the protective layer 30 away from the substrate 101 and the gate structure 102.
The semiconductor device comprises a substrate, a metal layer and a protective layer, wherein the substrate comprises a substrate and a grid structure positioned on the substrate; the metal layer is positioned on the surface of the substrate and the grid structure; the protective layer is positioned on the surface of the metal layer away from the substrate, wherein the protective layer is provided with a predetermined element, and the proportion of the predetermined element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure. Compared with the problem that the performance of the semiconductor device is poor due to the stress of the protective layer in the prior art, the semiconductor device provided by the application solves the problem that the performance of the semiconductor device is poor due to the fact that the proportion of the predetermined element in the protective layer is gradually increased along the direction of the protective layer away from the substrate and the gate structure by providing the substrate comprising the substrate and the substrate of the gate structure and forming the preparation metal layer and the protective layer which are sequentially stacked on the exposed surfaces of the substrate and the gate structure, reduces the stress of the protective layer, reduces the quantity of the element in the metal layer diffused into the substrate due to the stress of the protective layer, avoids the problem that the element in the metal layer diffuses into the substrate, and causes source-drain regions in the substrate to be short circuited and electric leakage in the prior art, and ensures the good performance of the semiconductor device due to the stress of the protective layer.
According to one embodiment of the present application, as shown in fig. 6, the gate structure 102 includes a gate oxide layer 105 and a gate 106, where the gate oxide layer 105 is located on a portion of the surface of the substrate 101; the gate electrode 106 is located on a surface of the gate oxide layer 105 remote from the substrate 101.
In a specific embodiment, the material of the gate oxide layer is a high K dielectric, and the material of the substrate is silicon.
Specifically, as the N in the protective layer gradually increases along the direction away from the substrate and the gate structure, the Ti in the protective layer gradually decreases along the direction away from the substrate and the gate structure, which ensures that the stress of the protective layer is smaller, avoids excessive silicidation of the source drain region, ensures that the defects of the semiconductor device are fewer, and ensures that the yield of the semiconductor device is better.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate, wherein the substrate comprises a substrate and a gate structure positioned on the substrate;
forming a preparation metal layer and a protection layer which are sequentially stacked on the exposed surfaces of the substrate and the gate structure to obtain a preparation structure, wherein the protection layer is provided with preset elements, and the proportion of the preset elements in the protection layer is gradually increased along the direction of the protection layer away from the substrate and the gate structure;
and performing a predetermined process on the preliminary structure so that the preliminary metal layer forms a metal layer, wherein the predetermined process comprises an annealing process.
2. The method of claim 1, wherein the step of forming a preliminary metal layer and a protective layer sequentially stacked on the exposed surfaces of the substrate and the gate structure to obtain a preliminary structure, comprises:
forming the preparation metal layer on the exposed surfaces of the substrate and the gate structure;
and forming the protective layer on the exposed surface of the preparation metal layer far away from the substrate by using a preset process, introducing preset gas into a reaction chamber in the process of forming the protective layer, and controlling the flow of the preset gas to gradually increase, wherein the preset process comprises a sputtering process, and the reaction chamber contains the substrate and the structure formed by the preparation metal layer.
3. The method of claim 2, wherein the predetermined gas is nitrogen.
4. The method of claim 1, wherein the step of performing a predetermined process on the preliminary structure such that the preliminary metal layer forms a metal layer comprises:
and carrying out the annealing treatment on the preparation structure, so that the preparation metal layer reacts with the substrate through the annealing treatment and forms the metal layer.
5. The method of claim 1, wherein the step of providing a substrate comprises:
providing the substrate, the preparation gate oxide layer and the preparation gate electrode which are sequentially stacked;
and removing part of the preparation gate oxide layer and part of the preparation gate electrode, exposing part of the substrate to obtain the base, forming a gate oxide layer by the rest of the preparation gate oxide layer, and forming a gate by the rest of the preparation gate electrode.
6. The method according to any one of claims 1 to 5, wherein the material of the protective layer comprises TiN and the predetermined element comprises nitrogen.
7. The method according to any one of claims 1 to 5, wherein the protective layer has a thickness in the range of 1nm to 50nm, and the predetermined element in the protective layer has a ratio in the range of 20% to 70%.
8. The method according to any one of claims 1 to 5, wherein the material of the preliminary metal layer comprises NiPt, the material of the substrate comprises Si, and the material of the metal layer comprises Ni x Si y 。
9. A semiconductor device, the semiconductor device comprising:
a base including a substrate and a gate structure on the substrate;
a metal layer on the surface of the substrate and the gate structure;
and the protective layer is positioned on the surface of the metal layer, which is far away from the substrate, wherein the protective layer is provided with a preset element, and the proportion of the preset element in the protective layer is gradually increased along the direction of the protective layer, which is far away from the substrate and the grid structure.
10. The semiconductor device of claim 9, wherein the gate structure comprises:
a gate oxide layer on a portion of a surface of the substrate;
and the grid electrode is positioned on the surface of the grid oxide layer, which is far away from the substrate.
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| CN117613003A (en) * | 2024-01-23 | 2024-02-27 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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