TWI242801B - Method for forming bit line contact - Google Patents

Abstract

The present invention discloses a method for forming bit line contact, which at least includes the following steps of providing a substrate that contains a plurality of transistors having a gate and a doped zone for forming a drain and a source; forming a first dielectric layer on the surface of the substrate; forming a second dielectric layer on the first dielectric layer; removing the second dielectric layer intended to form the bit line contact zone and part of the first dielectric layer; forming a passivation layer on the second dielectric layer, part of the gate and the first dielectric layer; ion-doping a passivation layer on the second dielectric layer and the gate and removing the passivation layer free of doped ion; removing the first dielectric layer on the doped zone intended to form bit line contact between gates to form a bit line contact; and lastly filling a conductor layer in the bit line contact as a bit line contact plug.

Description

1242801

0548-A50011TWF (Nl) · 92151: vyhsu.ptd Page 5 1242801 ------ —___________ 5. Description of the invention (2) ^ ^ meters, 4 〇 n m). Therefore, when a six-conductive layer is formed in the above-mentioned bit line contact window as a bit line contact (CB), a bit line contact open circuit (CB 0pen) or a word line-bit is easily generated. A defect of a word line-bit line short occurs. As long as the defects of the above-mentioned bit line contact or the word line-bit line short circuit occur, it will cause the manufactured semiconductor device to fail, which will adversely affect the yield and cost of the semiconductor process. To further investigate the problem, the following explains the manufacturing of conventional technologies: 辁.凊 Micau's Figures 1 A to 1 F are a series of cross-sectional views showing how a manufacturing method of a self-aligned bit line contact window can cause the above-mentioned bit 70 line to contact an open circuit or word line. -The lack of bit line short circuit First, a substrate 10 is provided, which has a transistor structure. The drain region 12 and the source region 1 4 arranged on the substrate 10 have a multilayer structure that protrudes from the surface of the substrate 10. For example, on the surface, a gate dielectric silicide layer 23 and a hard mask layer 2 4 are fossils and a spacer 25 in this order. Due to the gap, when the design line width of the semiconductor device is reduced to about 0.99 microns, the width of the exposed drain region 12 is ^ Please refer to FIG. 1B, and sequentially pattern the resist layer 60. Please refer to FIG. 1A for the patterning. The active surface of the substrate 10 is staggered at an interval; the pole 20 is between the non-electrode region 12 and the source region 14 and the gate electrode 20 is based on various requirements. In the gate electrode 20 of FIG. 1A, the substrate 10 includes an electrical layer 21, a conductive layer 22, and a metal, and a sidewall of the gate 20 has a nitrogen wall 25 on the side wall of the intermediate electrode 20. (Design rule) As described above, the gap 25 between adjacent gate electrodes 20 is only about 0.04 micrometers. A dielectric layer 30 and an agent layer 60 are formed on the substrate 10 and have an opening 600a.

I2428〇L V. Description of the invention (3) The exposed part of 6 〇a is 浐 ^ The next step is to remove the position of the% ^ line contact window. As far as the surface of the pole region 12, the dielectric layer 30 exposed by the opening 60a to the drain region 12, is not exposed and is a dielectric window of the bit line contact window, which is used as a bit line contact plug. . ^ A conductive layer is filled in the interlayer window. How to create the step in the step ::: D The steps shown in the above diagram 1E ~ 1F are the defects of the upper second line contact open circuit, and Di Yuanjun #-含 4 * How to cause the short-circuit of the word-line-bit 7G line in the above steps.卞 Please refer to Figure 1C, under the phase of the phase + main, mouth ^ ^ etch mask 对 μΪ Γ, using the patterned resist layer 60 as Ή, I + g 〇 anisotropic etching To form an interlayer window 31, and expose it; and the polar region 12, .L Bp ^ 1. ,, ^ This is the process of making the bit line contact window. However, as mentioned above, when the line width is about 0.99 micrometers, the width of the drain region 12 of the storm window 31 is only about 0.04 micrometers, and the via window 31 is quite south. Therefore, in practical cases, the dielectric layer 3 0 at the bottom of the dielectric window 3 丨 is closer to the dielectric layer 3 of the drain region 2 and the harder it is to be etched. When the etching reaction is terminated, a small amount of the remaining dielectric layer 30 a ′, which has not been etched or not completely etched, is left at the bottom of the interlayer window 31 without exposing the surface of the non-polar region η. Because part of the remaining dielectric layer 30a on the bottom of the interlayer window 31 prevents the surface of the drain region 12 from being exposed, please refer to FIG. 1D, even if a barrier layer 4 is subsequently formed in the interlayer window 31 〇, and fill in a conductive layer 50 as a bit line contact. In the case where the remaining dielectric layer 30 a is not a conductor, the conductive layer 50 cannot be electrically connected to the drain region 12. This causes the defect that the bit line contacts are open.

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V. Description of the invention (4) To avoid the use of etch with a lower row contact window, in order to avoid the occurrence of a petrified layer between the contacts 2 3 Bits formed of polycrystalline silicon with a coin-selection layer Line-short circuit will choose to lower the ratio to expose this. In addition to the interlayer and the spacer 25, the metal layer 23 will be exposed. The defect that causes the bit line to open is known as F 6: choose the self-aligned contact window etching process parameters to enter κ, and in the process of forming the line contact window, set the leaf as the gate of the line. The polycrystalline silicon layer of the conductive layer in the electrode 20 and the subsequent bit, circuit, and gate 20 is protected by a U-type hard cover curtain layer 24 and a spacer 25, and is etched with a selectable parameter In order to avoid the short-circuit between the gate electrode 20 and the metal layer 22 and the metal silicide layer 23 being exposed and contacting with the subsequent contacts. However, the difficulty is that if you take a job or a road, please refer to Section ㈣. On the one hand, you need to etch: Choose the dielectric layer 30 that may be left at the bottom of the two-layer window 31a, and the width of the window 31a will be enlarged. Part of the hard cover curtain layer 2 4 will be removed to form the partition wall 25a, so that the gold "stone xi comes out" and even the polycrystalline silicon layer 2 2 may be exposed. Please refer to Figure 1F. In the case where the metal silicide layer 23 of the conductive layer 20 is exposed, a barrier layer 40 is formed after forming a barrier layer 40 ′ in the interlayer window 3a and filled with a conductive layer 50 which is a bit line contact. After the step, the conductive layer 50 as the bit line contact is electrically connected with the metal silicide layer 23 of the conductive layer of the gate 20, which causes the defect of the word line-bit line short circuit described above. In the conventional practice, a way of using | worm engraving (0 v e r e t c h i n g) is also used to avoid the defect of causing the bit line to contact the open circuit.

0548-A50011TWP (N1): 92151-yyhsu.ptd Page 8 1242801 V. Description of the invention (5) In the process of making the contact line of the element wire, like P 7 · / τ A, the two use "emulsified stone as the hard tamper layer" 2 4 Healing wall 25 and silicon oxide as A intermediary 厣 π 丄 勹 丄 勹 桊 桊 Μ Μ Μ Μ Μ Μ 间 间 M M M M M M M M 为 为 为 包 30 30 cladding 30, so the dielectric layer 30 pairs the hard mask potential Z 4 In the P sequence, the I of the wall 2 5 engraved i T n 屮, and said that W π buried u +, the choice is about 10. However, such a low Qian Hai j Ting selection ratio is in the rhyme (10 f. Π u〇ver etchlng), it will also cause the hard cover layer 24 and the spacer 25 to be etched away, so that all the members are removed and the metal silicide layer 2 3 and complex are removed. The crystal silicon 2 * circuit comes out, causing the above-mentioned defect of the word line _ bit line short circuit.: This J plus process steps to protect the semiconductor surface from causing the above = 疋 Although: ,, if necessary, increase The problems of production cost and production schedule caused by the process steps are unavoidable. [Summary of the Invention] In view of Λ, the present invention provides a method of "bit-line contact solid method" to avoid Because the gap between the gate electrodes is getting smaller and smaller, the inner dielectric layer (ILD) cannot be etched completely to avoid the defect of the bit line contact open. Another object of the present invention is to provide a A method for forming a bit line contact window to avoid the gap width between the gate electrodes becoming smaller and smaller, which can easily cause the bit line contact window to etch through the gate conductive layer and the metal silicide layer during the etching, so as to avoid the word The problem of short circuits between the element line and the bit line. In addition, it is different from the conventional Qian Qian'an process. It is manufactured in the bit line contact window. Bit line contact_etching process to reduce gate gate loss due to dry etching, thereby avoiding short-circuit problems between word lines and bit lines. Another object of the present invention is to use a polycrystalline silicon Spacer to shrink bits

0548-A50011TWF (Nl): 92151 1242801 V. Description of the invention (, 6 :) The macro of the line contact window (CD), to avoid the excessive macro distance of the top of the bit line contact window caused by the wet etching process, which will affect the subsequent process. Tolerance. In order to achieve the above object, the present invention proposes a method for manufacturing a contact window opening. The self-aligned (SAC) bit line contact window is etched in two steps (2 steps) to form a bit line contact window, thereby reducing the contact window. Aspect ratio. The main steps include: providing a substrate having a plurality of transistors, and the transistor includes a gate and a doped region constituting a drain and a source. An inner liner layer is formed on the silicon substrate and the MOS transistor, a first dielectric layer is formed on the inner layer and the MOS transistors are filled. Then, a mask layer is formed on the inner liner layer and the first dielectric layer, wherein the mask layer has an opening to expose the first dielectric layer on the doped region. A spacer is formed on the side wall of the opening; using the mask layer and the spacer as a mask, the first dielectric layer and the inner lining layer exposed on the doped region are removed to form a contact window. A conductive plug is formed in the contact window, and the cover layer is removed. A second dielectric layer is formed on the inner layer and the conductive plug, and the second dielectric layer is engraved to form a one-bit line contact window to expose the conductive plug. Finally, a barrier layer and a metal layer are formed to fill the bit line contact window as a bit line contact plug. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings in detail, as follows: [Performance Mode] Please refer to Section 2 Figures A ~ 2J are a series of cross-sectional views showing a method for forming a bit line contact window in a preferred embodiment of the present invention.

0548-A50011T \ VF (Nl): 92151: yyhsu.ptd Page 10 1242801__ V. Description of the invention (7) Please refer to Figure 2A. First, provide a substrate, such as the substrate of a single crystal eve. The substrate 丨 〇〇 has the structure of a transistor, and on the active surface of the substrate 丨 〇 there is a doped region 1 10 that constitutes an electrode and a source; between the doped region 1 1 〇 there is a protruding substrate 1 〇 〇Gate on the surface 丨 2 〇a ～ 12 〇d, the gate is an ordinary line, according to various requirements, usually has a multilayer structure, for example, in the gates 120a ~ 120d in Figure 2a, the base 1〇 The surface of 〇 is sequentially arranged as a gate dielectric layer 1 2 1 such as an oxide layer, a polycrystalline silicon layer as a conductive layer 1 2 2, a metal silicide layer as a conductive layer 丨 2 3 such as silicidation The crane layer is used to reduce the contact resistance between the metal layer and each pole of the MOS device. A hard mask layer 1 2 4 is, for example, a silicon nitride layer, and the gate height is about 8000 angstroms. The structure composed of the above-mentioned polycrystalline stone layer and metal silicide layer is also called polycide metal. And on the side of the gate 丨 20a ~ 12〇 (i there are _ for example the gate gap formed by silicon nitride 丨 25. Among them, the above-mentioned gate structure is only an example of the conventional gate structure The features of the present invention are not related to the scope of the present invention. Afterwards, please refer to FIG. 2B, and conformally deposit a thickness of about 丨 〇〇 ～ 丨 by low pressure chemical vapor deposition (LP ^ C VD). An inner liner layer of 30 Angstroms, such as a silicon nitride layer, on the silicon substrate 10 () and Mos transistor, the purpose of which is to avoid the formation of the inner dielectric layer (ILD) which is continuously formed. The boron-phosphorus dopant of the BpSG layer diffuses into the silicon substrate due to the subsequent thermal process, which affects the characteristics of the device. This will protect the sidewalls when it is engraved. After the inner liner layer is deposited, The width of the gap (sH t) between the two gates is about 40 °. Next, please refer to Figure 2C, using the plasma enhanced chemical vapor deposition method (? £ (^ 0) > A first dielectric layer 127 having a thickness of about 1000 to 2000 angstroms, for example

1242801

1242801_ 5. Description of the invention (9) After removing ′, the inner liner layer 2 6 is etched and removed by a dry method to form a contact window 1 3 1. Please refer to FIG. 2H. A low-pressure chemical vapor deposition (LPCVD) method is used to form a conductive layer with a thickness of about 1000-500 angstroms. For example, a polycrystalline silicon layer is filled into the contact window 131 and is etched back. The conductive layer and the cover layer 128 are simultaneously removed to form a conductive plug 132. Then, referring to FIG. 21, a second dielectric layer 133, such as tetraethoxysilane, is deposited by plasma enhanced chemical vapor deposition (PECVD) to a thickness of about 2 0 0 to 4 0 0 0 angstroms. (TEOS) a silicon oxide layer on the inner lining layer 1 2 6 and the conductive plug 1 2 3, and then form a photoresist layer on the second dielectric layer 1 3 3 by coating, for example, to pattern the light. The resist layer defines a contact window pattern corresponding to the doped region 110. The second dielectric layer 1 3 3 is etched by anisotropic dry etching to perform a second contact window etching process' to form a one-bit line contact window 1 3 7 to expose the conductive plug 1 3 2. Before the second dielectric layer 1 3 3 is formed, the first contact window engraving process has been performed and a conductive plug 1 3 2 has been formed to fill part of the contact window, so the subsequent second dielectric layer 1 3 3 Deposition can be thinned as a result, reducing the aspect ratio of the contact window (aspect rat io), and therefore can improve the open contact of the bit line or the short circuit between the word line / bit line. Qing Cang's test 2 J Figure 'Yuan Hou' formed a barrier layer 134 with a thickness of about 100 to 200 angstroms, such as a Ti / TiN layer, and a low pressure chemical vapor deposition (LPCVD) method using a coin bond method. A metal layer 135 having a thickness of about 2500 to 3500 angstroms is deposited, such as a crane metal layer to fill the bit line contact window 'to serve as a bit line contact plug. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to

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0548-A50011TWF (N1); 92151: yyhsu.ptd Page 14 1248201_ Brief description of the drawings In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment is given below, in conjunction with the attached The drawings are described in detail as follows: Figures 1 A to 1 F are a series of cross-sectional views showing how a conventional method of manufacturing a bit line contact window causes the above-mentioned bit line to contact an open circuit or a word line. -Defects in bit line shorts. Figures 2A to 2J are cross-sectional views of 歹 d, showing detailed steps of a method for forming a bit line contact window in a preferred embodiment of the present invention. [Symbol description] Known technology targets: 1 0 ~ substrate; 1 2 ~ drain region; 1 4 ~ source region; 2 0 ~ gate; 2 1 ~ gate dielectric layer; 2 2 ~ polycrystalline Xi layer; 2 3 ~ metal silicide layer; 2 4 ~ hard cover curtain layer; 2 5 ~ gate spacer; 30 ~ dielectric layer; 31, 31a ~ dielectric window; 50 ~ conductive layer; 60 ~ photoresist Layer (cover layer);

0548-A50011TWF (Nl): 92151; yyhsu.ptd page 15 1242801 Simple illustration of the pattern 6 0a ~ patterned resist layer opening. The technology of the present invention: 1 0 0 ~ substrate; 1 1 0 ~ miscellaneous region (and polar region), 1 2 0 a, 1 2 0 b, 1 2 0 c, 1 2 0 d ~ gate; 1 2 1 ~ Gate dielectric layer; 1 2 2 ~ polycrystalline silicon layer; 1 2 3 ~ metal silicide layer; 124 ~ hard cover curtain layer; 1 2 5 ~ gate spacer; 1 2 6 ~ inner layer; 127 ~ First dielectric layer; 128 ~ mask layer; 1 2 9 ~ opening; 1 3 0 ~ spacer; 1 3 1 ~ contact window; 1 3 2 ~ conductive plug; 133 ~ second dielectric layer; 1 3 4 ~ barrier layer; 1 3 5 ~ metal layer; 1 3 6 ~ photoresist layer; 1 3 7 ~ bit line contact window.

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Claims (1)

1242801 The steps listed below include the method of forming the window contact wiring elements of the method. Fan Lizhuan, please 1 Shen Λ 6: Miscellaneous ο The adjacent poles of the reference M are combined with the number of poles and the structure is included. The pole bottom gate base cuts the body-contained conductor semi-crystal and provides electricity for the lifted bulk crystal region. The bulk crystal region should be filled and the upper layer MO :, the liner and the inner bottom. The first-in-line formation of the liner should be covered with a shuntan crystal. Some of its upper dielectrics, the first and the layers, and the liner should be formed on the extra layer of the crystal; the layer should be filled with electricity, and the dielectric. The first region of the first layer and the first layer and the impurity layer are doped with silicon and the crystals are exposed. The opening is separated from the open layer with a layer of silicon-shaped crystals and multiple D βπ portions are engraved with the money in the layer compartment. For the material compartment and the layer curtain; the dew storms the room apart to form a carved money wall, the side curtain masks the # which make the layer., The electrical window guides the recessed and shaped, and the middle window Inner contact and the dielectric filling layer A region-shaped doped layer is formed on one of the first conductors; a silicon plug is inserted on the silicon to remove and merge the layers, and the plug is inserted and inserted into the conductive layer. In the connection, the conductive contact element of the exposed window should be formed with a layer of dielectric two and should be engraved with 0; plug two 15 as the window contact connection element should be filled with a layer of gold and plug plugged. The barrier contact is connected to a line of element shape. The first is to include the order in which the bottom surface of the surface is covered by the structure. The dielectric gate and the layer of the first layer, the surrounding range of electric gate special silicon, please Jingshen Fu as a 3-layer materialized nitrogen window contact wiring element formation described 0548-A50011TWF (Nl): 92151: ^ hsu.ptd page 17 1242801 6. Application for a patent method The first lining layer is a nitrided layer. 4. The method for forming a bit line contact window as described in item 1 of the patent application scope, wherein the first dielectric layer is a borofill glass (BPSG) layer. 5. The method for forming a bit line contact window as described in item 1 of the scope of the patent application, wherein the first dielectric layer of the recessed coin is an isotropic wet coin engraving method. 6. The method for forming a bit line contact window as described in item 1 of the patent application scope, wherein the first conductive layer is a polycrystalline silicon layer. 7. The method for forming a bit line contact window as described in item 1 of the patent application scope, wherein the first conductive layer is formed by a low pressure chemical vapor deposition (LPCVD) method. 8. The method for forming a bit line contact window as described in item 1 of the scope of the patent application, wherein the second inner layer is a polycrystalline stone layer. 9. The method for forming a bit line contact window as described in item 8 of the patent application scope, wherein the second lining layer further comprises a silicon nitride layer. 10. The method of forming a bit line contact window as described in item 1 of the scope of patent application, wherein the first dielectric layer on the doped region is removed to form an opening using an isotropic wet etching method. Π. The method for forming a bit line contact window as described in item 1 of the patent application scope, wherein the second conductive layer is a polycrystalline silicon layer. 1 2. The method for forming a bit line contact window as described in item 1 of the scope of the patent application, wherein the second dielectric layer is a tetraethoxysilane (TEOS) layer. 1 3. A method for forming a bit line contact window, including the following steps: providing a semiconductor substrate including a plurality of adjacent MOS transistors, and the transistor including a gate and a drain and a source; Doped region 0548-.A50011TWF (N1): 92151: yyhsu.ptd Page 18 1242801 6. The scope of the application for a patent forms ^ 2 on the above substrate and MOS transistor where the cover layer liner and the -dielectric layer = : Sidewall two, first dielectric layer, dielectric layer and inner :::::! ::, the mask 'removes the exposed first —: to make the window conductive-plug, and remove the mask layer; The second 2 is on the inner lining layer and the conductive plug at a later time; the plug; and; | said that the conductive is exposed by forming a line contact window: ί line: the metal layer fills the bit line contact Window to make the bit line contact as described in / Λ Patent Range Item 13 *, W is different 丨 AJ flying layer is 荽 1 6 · As in the patent application range 丨 3 __________ ^ ^ Health, Gan Shi * & 'Phosphorus-silicone slope (BPSG) layer electric layer, -multi-crystal "electrode, a silicon oxide layer and _nitrogen; ^ Intermediate 15 · As described in the scope of patent application No. 丨 3 Method for forming a bit line connection 'wherein the first inner lining layer is a silicon nitride layer. Since the method, wherein the first dielectric layer is a milk _____. 1 7 · As for item 13 of the scope of patent application The method for forming a bit line contact window described in the above, wherein the first dielectric layer is recessed by an isotropic wet etching method. 1 8 · The bit line contact window is formed as described in item 13 of the scope of patent application. Method, wherein the first conductive layer is a polycrystalline stone layer 1 " forming a bit line contact window B 0548-A50011T \ VF (Nl): 92151; yyhsu.ptd Page 19 1242801__ 6. Application for patent scope 1 9. The method for forming a bit line contact window as described in item 13 of the scope of patent application, wherein the first A conductive layer is formed by a low pressure chemical vapor deposition (LPCVD) method. 20. The method for forming a bit line contact window as described in item 13 of the scope of the patent application, wherein the second lining layer is a polycrystalline silicon layer. 2 1. The method for forming a bit line contact window as described in item 20 of the patent application scope, wherein the second inner liner layer further comprises a silicon nitride layer. 22. The method for forming a bit line contact window as described in item 13 of the scope of the patent application, wherein the first dielectric layer on the doped region is removed to form an opening using an isotropic wet etching method. 2 3. The method for forming a bit line contact window as described in item 13 of the scope of patent application, wherein the second conductive layer is a polycrystalline silicon layer ^ 2 4. The bit formation as described in item 13 of the scope of patent application The method of contacting the element line with the window, wherein the second dielectric layer is a tetraethoxysilane (TEOS) layer. 0548-. ^ 50011TWF (Nl); 92151: yyhsu.ptd page 20