JPH0325930A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0325930A JPH0325930A JP1161415A JP16141589A JPH0325930A JP H0325930 A JPH0325930 A JP H0325930A JP 1161415 A JP1161415 A JP 1161415A JP 16141589 A JP16141589 A JP 16141589A JP H0325930 A JPH0325930 A JP H0325930A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching barrier
- contact hole
- insulating film
- barrier film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 239000012298 atmosphere Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 24
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は半導体装置の製造方法に関し、更に詳しくは
スタックトタイプやプレーナタイブなどのダイナミック
・ランダムアクセスメモリのコンタクトホール形成方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming contact holes in dynamic random access memories such as stacked type and planar type.
（口）従来の技術
従来のこの種スタックト型（積層型）ダイナミックラン
ダムアクセスメモリの製造方法を第２図を用いて説明す
る。(BACKGROUND) A conventional method for manufacturing this type of stacked dynamic random access memory will be described with reference to FIG.
まず、第２図（ａ）に示すように、ＬＯＧＯＳ酸化膜ｌ
４、不純物拡散層２およびゲート電擾４を有する単結晶
ＳｔＪ！ｆ仮ｌ上に、Ｓｈｏｗ膜５を介してコンタクト
ホール形成領域（Ａ）を除く領域全面にノードボリＳｔ
膜６、キャパノタ絶嫁膜７およびプレートボリＳｔ膜（
プレート電極）８を順次積層してなるキャパノタ電匝層
が形成され、
次に、全面に、ＣｖＤ法によりＳｉｆｔを１．５００Ａ
堆積して、ＳｊＯｔ膜９を形威し、更に全面にＢＰＳＧ
を５，０００人堆積し、８５０℃〜９５０℃の温度で、
Ｎ２雰囲気あるいは、水蒸気雰囲気でメルトを行ってＢ
ＰＳＧ膜ｌＯを形戊する［第２図（ｂ）参照〕。First, as shown in FIG. 2(a), the LOGOS oxide film l
4. Single crystal StJ with impurity diffusion layer 2 and gate electrode 4! Node holes St are formed on the entire surface of the area except for the contact hole forming area (A) via the Show film 5 on the f temporary L.
Membrane 6, Capanota barrier membrane 7 and plate-bore St membrane (
A capacitor electrode layer is formed by sequentially laminating plate electrodes 8, and then a Sift of 1.500A is applied to the entire surface by CvD method.
The SjOt film 9 is deposited, and BPSG is then deposited on the entire surface.
was deposited by 5,000 people at a temperature of 850℃ to 950℃,
B by performing melting in N2 atmosphere or water vapor atmosphere.
A PSG film IO is formed [see FIG. 2(b)].
その後、フォト工程により、レジスト膜ｌ１のビットラ
インコンタクト穴１１ａをコンタクトホール形成領域（
Ａ）上に開口し、ｓＨＦ液あるいは、等方性プラズマ等
により、テーパーエッチを行ってコンタクト開口部１ｌ
ｂを形成する［第２図（Ｃ）参照］。この際、テーパー
エッチを行うのは、コンタクト開口部１ｌｂをなめらか
にし、かつ、以後に積層されるメタル等の配線のカバレ
ッジを向上させ、信頼性をあげるためである。Thereafter, by a photo process, the bit line contact hole 11a of the resist film l1 is formed in the contact hole forming area (
A) Open the contact opening 1l by performing taper etching using sHF liquid or isotropic plasma.
b [see FIG. 2(C)]. At this time, the reason why the taper etch is performed is to make the contact opening 1lb smooth and to improve the coverage of wiring such as metal that will be laminated later, thereby increasing reliability.
次に、ＲＩＥ等により、コンタクト穴１１ａを介してコ
ンタクトホール形戊領域（Ａ）の中央部分に残存するＢ
ＰＳＧ膜１ ０ ａ ｓ その直下のＳｉＯｔ！９、さ
らに直下のＳ＋Ｏ，膜５のコンタクトエッチを行い、コ
ンタクトｌ５を開口する。その後、残存するレジスト１
１を除去し、コンタクトホールｌ５を含む全面にメタル
をデボし、パターニングしてメタルのビット線ｌ２を形
成する［第２図（ｄ）参照］。Next, by RIE or the like, B remaining in the center part of the contact hole-shaped area (A) is removed through the contact hole 11a.
PSG film 1 0 a s SiOt directly below it! 9. Further, contact etching is performed on the S+O film 5 immediately below to open a contact 15. After that, the remaining resist 1
1 is removed, metal is deposited on the entire surface including the contact hole 15, and patterned to form a metal bit line 12 [see FIG. 2(d)].
（ハ）発明が解決しようとする課題
しかしながら、素子の微細化が進むにつれコンタクトホ
ール１５の側壁において、ＢＰＳＧ膜ｌＯがエッチング
され、かつその直下のＳｉＯｚ膜９ら上部が除去されて
測壁部分ではこれら層間絶縁膜の膜厚が減少するから、
ビット線］２とプレート電極８間の距離が縮まり、ビッ
ト線ｌ２とプレート電極８間のリーク電流が増大したり
、耐圧低下が生じたりして信頼性が低下するおそれがあ
る。また、ビット線ｌ２とワード線４間にも、同様の減
少が生じるのを避け難い。(c) Problems to be Solved by the Invention However, as the miniaturization of devices progresses, the BPSG film 1O is etched on the side wall of the contact hole 15, and the upper part of the SiOz film 9 immediately below it is removed, causing the wall measurement area to become Since the thickness of these interlayer insulating films decreases,
The distance between the bit line [12] 2 and the plate electrode 8 is shortened, and there is a risk that the leakage current between the bit line 12 and the plate electrode 8 will increase, the withstand voltage will decrease, and reliability will decrease. Furthermore, it is difficult to avoid a similar decrease occurring between the bit line l2 and the word line 4 as well.
本発明は、上記問題を解決するためになされたものであ
り、配線の信頼性を向上できる眉間絶縁膜を形成できる
半導体装置の製造方法を提供しようとするものである。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a glabellar insulating film that can improve the reliability of wiring.
（二）課題を解決するための手段
この発明は、半導体基板上に、ゲート電極間のコンタク
トホール形成領域を除く領域全面に、キャパシタ電極層
を形戊し、続いて、コンタクトホール形成領域を含む全
面に第ｌ絶縁膜、対エッチングバリア膜、平坦化のため
の第２絶縁膜およびフォトレジスト膜を順次積層し、次
に、コンタクトホール形成領域上のフォトレジスト膜を
除去してコンタクトを開口し、そのコンタクトを介して
エッチングによりコンタクトホール形或領域上の第２絶
縁膜を除去してコンタクトホール形成領域上に対エッチ
ングバリア膜を露出させ、さらに残存するフォトレジス
ト膜を除去した後、露出された対エッチングバリア膜の
表面を水蒸気雰囲気で酸化し、しかる後上記露出された
対エッチングバリア膜のうちコンタクトホール形戊領域
中央部分の対エッチングバリア膜およびその直下の第１
絶縁膜を除去してコンタクトホールを形戊し、コンタク
トホールを含む全面に配線層を形成することを特徴とす
る半導体装置の製造方法である。(2) Means for Solving the Problems This invention forms a capacitor electrode layer on the entire surface of a semiconductor substrate except for a contact hole formation region between gate electrodes, and then forms a capacitor electrode layer on the entire surface of the semiconductor substrate except for a contact hole formation region. A first insulating film, an anti-etching barrier film, a second insulating film for planarization, and a photoresist film are sequentially laminated on the entire surface, and then the photoresist film on the contact hole formation area is removed to open a contact. The second insulating film on a certain area of the contact hole shape is removed by etching through the contact to expose an anti-etching barrier film on the contact hole forming area, and the remaining photoresist film is removed. The surface of the etching barrier film is then oxidized in a water vapor atmosphere, and then the etching barrier film in the central part of the contact hole-shaped region and the first layer immediately below the exposed etching barrier film are oxidized in a water vapor atmosphere.
This method of manufacturing a semiconductor device is characterized by removing an insulating film to form a contact hole, and forming a wiring layer over the entire surface including the contact hole.
すなわち、この発明は、キャパシタ電極層上の、第１，
第２絶縁膜間に対エッチングバリア膜を形成し、コンタ
クトホールを形成する際に、まず、第２絶縁膜をエッチ
ングしてコンタクトホール形成領域上に対エッチングバ
リア膜を露出させ、次に、この膜の表面を水蒸気雰囲気
で酸化した後コンタクトホール底部位置にあたる上記バ
リア膜および第１絶縁膜を除去するようにしたものであ
る。That is, the present invention provides the first,
When forming an anti-etching barrier film between the second insulating films and forming a contact hole, first, the second insulating film is etched to expose the anti-etching barrier film on the contact hole formation region, and then this After the surface of the film is oxidized in a steam atmosphere, the barrier film and the first insulating film located at the bottom of the contact hole are removed.
この発明における対エッチングバリア膜は周知の方法で
形成される。すなわち、高温下で減圧ＣＶＤ法を用いて
形戊されるＳｉＪａ膜や低温下でプラズマ法により形成
されるプラズマＳｉＮ膜などのＳｉＮ系絶縁膜が好まし
いものとして挙げられる。The anti-etching barrier film in this invention is formed by a well-known method. That is, preferred examples include SiN-based insulating films such as a SiJa film formed using a low-pressure CVD method at high temperatures and a plasma SiN film formed by a plasma method at low temperatures.
また、ボリＳｉ膜やＷＳｉｔなどのシリサイド膜を直上
の第２絶縁膜をエッチングする際の対エッチングストッ
パーとして用いても良い。Further, a silicide film such as a poly-Si film or WSit may be used as an etching stopper when etching the second insulating film directly above it.
この発明における第２絶縁膜としては、ＢＰＳＧやＢＳ
Ｇなどの平坦化のためのＳｉｎ，の絶縁膜が好ましい。As the second insulating film in this invention, BPSG or BS
It is preferable to use an insulating film such as G for flattening the film.
例えば、上記ｓｉ−Ｊ４膜とＢＰＳＧ膜とのエッチング
レート比はｌ：６であり、ＳｌｓＮａ膜はエッチングス
トッパーとしての役割を有する。また、上述したポリＳ
ｉ膜やシリサイド膜などを用いても同様のエッチングレ
ート比を有ずる。For example, the etching rate ratio between the si-J4 film and the BPSG film is 1:6, and the SlsNa film has a role as an etching stopper. In addition, the above-mentioned polyS
A similar etching rate ratio can be obtained even if an i film or a silicide film is used.
この発明における第ｌ絶縁膜としては、Ｓｉｎ．のちの
が好ましいものとして挙げられる。As the first insulating film in this invention, Sin. The latter is listed as preferred.
また、ＰＳＧ膜やＳＯＧ膜などを用いても良い。Alternatively, a PSG film, an SOG film, or the like may be used.
そして、これ与絶縁膜は公知の方法を用いて容易に形成
される。This insulating film can be easily formed using a known method.
（ホ）作用
第【．第２絶縁膜間に第２絶縁膜をエッチングする際の
対エッチングバリア膜を形成したので、これがコンタク
トフォト後の第２絶縁膜のエッチングの際に、エッチン
グストッパーとして作用するから、下層の第１絶縁膜を
その膜厚を維持しながらコンタクトホールを形成できる
とともに、上記エッチ時に露出した対エッチングバリア
膜の表面を水蒸気雰囲気で酸化したので、上記バリア膜
および第２絶縁膜の膜質そのらのを向上しながら、ビッ
ト線とプレート１ｉ極間あるいはビット線とゲート電極
間のリーク電流を抑制でき、配線の信頼性を向上できる
。(e) Effect number [. Since an anti-etching barrier film is formed between the second insulating films when etching the second insulating film, this acts as an etching stopper when etching the second insulating film after contact photo. The contact hole can be formed while maintaining the film thickness of the insulating film, and since the surface of the etching barrier film exposed during the etching is oxidized in a water vapor atmosphere, the film quality of the barrier film and the second insulating film can be improved. It is possible to suppress the leakage current between the bit line and the plate 1i electrode or between the bit line and the gate electrode, and improve the reliability of the wiring.
（へ）実施例 以下図に示す実施例にもとづいてこの発明を詳述する。(f) Example The present invention will be described in detail below based on embodiments shown in the figures.
なお、これによってこの発明は限定を受けるものではな
い。Note that this invention is not limited by this.
第１図（ｃ）において、スタックト型ダイナミックメモ
リは、単結晶Ｓｉ基板２１上に、ゲート電極２２間のコ
ンタクトホール形成領域（Ｂ）を除く全面に、ＳｉＯｔ
＠２ ３および不純物拡散領域２４を介して、ノードボ
リＳｉ膜２５、ＳｘＯｔのキャパシタ絶縁膜２６および
プレートボリＳｉ膜（プレート電極）２７が順次積層さ
れてなるキャパシタ電極部４０が形成され、さらに、コ
ンタクトホール２８の底部を除く全面に第ｌ絶縁膜とし
てのＳｉｎ，膜２９、対エッチングバリア膜としてのＳ
ｉＪ４ＭＵ３０および第２絶縁膜としてのＢＰＳＧ膜３
ｌが順次積層され、コンタクトホール２８を含む全面に
ビット線としてのメタル配線Ｆ！３２が形成されている
。In FIG. 1(c), the stacked dynamic memory has a single-crystal Si substrate 21 with SiOt
A capacitor electrode portion 40 is formed by sequentially stacking a node-bored Si film 25, an SxOt capacitor insulating film 26, and a plate-bored Si film (plate electrode) 27 via @2 3 and the impurity diffusion region 24, and furthermore, a contact The entire surface except the bottom of the hole 28 is covered with a film of Sin as a first insulating film, a film 29, and a film of S as an anti-etching barrier film.
iJ4MU30 and BPSG film 3 as second insulating film
1 are sequentially stacked, and metal wiring F! as a bit line is formed on the entire surface including the contact hole 28. 32 is formed.
なお、３４はＳｒＯｔのＬＯＣＯＳ酸化部、３５は不純
物各酸層、３６はＳｉｎｇのゲート酸化膜である。In addition, 34 is a LOCOS oxidation part of SrOt, 35 is each impurity acid layer, and 36 is a gate oxide film of Sing.
以下製造方法について説明する。The manufacturing method will be explained below.
まず、第ｌ図（ａ）に示すように、Ｓｉ基板２Ｌ上に、
ゲート電極２２間のコンタクトホール形成領域（Ｂ）を
除く領域全面に、キャパシタ電極層４０を形成し、続イ
テ、全面ニＣＶＤ−ＳｉＯｔｇ ２ ９を１，５００人
の膜厚に、ＣＶＤ−ＳｉＪ＊膜３０を２００人の膜厚に
順次堆積し、さらに全面にＢＰＳＧ膜３ｌを５，０００
入堆積し、続いて、８５０℃〜９５０°Ｃの温度で、Ｎ
，雰囲気あるいは水蒸気雰囲気でＢＰＳＧをメルトする
ことにより平坦化を行う。First, as shown in FIG. 1(a), on the Si substrate 2L,
A capacitor electrode layer 40 is formed over the entire area except for the contact hole forming area (B) between the gate electrodes 22, and in a subsequent iteration, CVD-SiOtg 2 9 is deposited on the entire surface to a thickness of 1,500 nm, and CVD-SiJ* is applied. The film 30 was sequentially deposited to a thickness of 200 mm, and then a BPSG film 3 l was deposited on the entire surface to a thickness of 5,000 mm.
N
Flattening is performed by melting the BPSG in a , atmosphere or a steam atmosphere.
その後、全面にフォトレジスト層を形成した後、フォト
工程により、フォトレジスト層のコンタクト形成領域（
Ｂ）に対応する個所にビットラインコンタクト穴３３ａ
を開口し、ＢＨＦ液あるいは、等方性プラズマ等により
、テーパーエッチを行ってコンタクト開口部３１ａを形
成する。この際、テーパーエブチは、コンタクトホール
形戒領域（Ｂ）上ノＢＰＳＧ膜３１のみが除去されテＣ
ＶＤ−Ｓｉ，Ｎ，＠３０でとまり、領域（Ｂ）上の表面
にＳｉ３Ｎ＋膜３０が露出されろ。［第１図（ｂ）参照
］。After that, after forming a photoresist layer on the entire surface, a photo process is performed to form a contact formation area of the photoresist layer (
Bit line contact hole 33a at the location corresponding to B)
A contact opening 31a is formed by performing taper etching using BHF liquid or isotropic plasma. At this time, only the BPSG film 31 on the contact hole shaped area (B) is removed from the taper edge.
Stop at VD-Si,N,@30 and expose the Si3N+ film 30 on the surface above region (B). [See Figure 1(b)].
さらに、残存するレジスト＠３３の除去後、“水蒸気雰
囲気で、８００〜９５０℃の温度で、Ｓｌ ｙＮ＋膜３
０の表面を酸化する。この時、同時にＢＰＳＧ膜３ｌに
メルトがかかり、コンタクトホール形成領域（Ｂ）周縁
のＢＰＳＧ膜面３１ａがなだらかになりＣ第Ｉ図（ｃ）
参照］、以後、積層される配線材料のカバレブジを良好
にできる。Furthermore, after removing the remaining resist@33, the Sl yN+ film 3 was
Oxidize the surface of 0. At this time, the BPSG film 3l is simultaneously melted, and the BPSG film surface 31a at the periphery of the contact hole formation region (B) becomes smooth as shown in Fig. I (c).
[Refer to], it is possible to improve the coverage of the wiring materials to be laminated thereafter.
次に、再度、全面にフォトレジスト層を積層し、フォト
工程により、ビットラインコンタクト穴を開口し（図示
せず）、開口されたレジスト膜をマスクにＲＩＥ等によ
りコンタクトエッチをほどこし、コンタクトホール形成
領域（Ｂ）上のＳＬ３Ｎ４＠ ３ ０ ， Ｓｉｎ，膜
２９さらには不純物拡散層３５上のＳＥ（ｈＨ ２ ３
を除去してＳｉ基１１ｉ５２１にまで至るコンタクトホ
ール２８を開口する。その後、レジストを除去し、ＡＩ
− Ｓｉのメタル合金膜あるいはＷＳｉｙのシリサイ
ド膜をデボし、パターニングして、ビット線３２を形成
する［第１図（ｃ）参照コ。Next, a photoresist layer is laminated on the entire surface again, a bit line contact hole is opened by a photo process (not shown), and a contact etching is performed by RIE etc. using the opened resist film as a mask to form a contact hole. SL3N4@30, Sin, film 29 on region (B) and SE (hH 2 3
is removed to open a contact hole 28 that reaches the Si base 11i521. After that, the resist is removed and the AI
- A metal alloy film of Si or a silicide film of WSiy is deposited and patterned to form a bit line 32 [see FIG. 1(c)].
このように本実施例では、Ｓｉ基仮２＋上に、プレート
電瓶２７を介して層間絶偉膜３ｌを順次積層されてなる
半導体装置において、眉間絶縁膜２９．３１間にＳｉ３
Ｎ．膜３０を形威し、層間絶禄膜３ｌの所定部位（Ｂ）
をエッチング除去した後、Ｓ１３Ｎ４膜３０を露出させ
、さらにＳｊａＮ＊膜３０を水蒸気雰囲気で酸化し、そ
の表面に酸化膜を形戊するようにしたので、絶縁＠３０
．２９の膜質を向上できるとともに、ＳｉＪ４ＩＩ ３
０の表面酸化の際にコンタクトホール側壁周辺のＢＰ
ＳＧＭ面３１ａをなだらかにできメタル配線３２のカバ
レッジを向上できる。As described above, in this embodiment, in a semiconductor device in which the interlayer film 3l is sequentially laminated on the Si-based layer 2+ via the plate capacitor 27, the Si3
N. The film 30 is shaped and a predetermined portion of the interlayer barrier film 3l is formed (B).
After removing the S13N4 film 30 by etching, the S13N4 film 30 was exposed, and the SjaN* film 30 was further oxidized in a water vapor atmosphere to form an oxide film on its surface.
．． In addition to improving the film quality of SiJ4II 3
BP around the sidewall of the contact hole during surface oxidation of
The SGM surface 31a can be made smooth and the coverage of the metal wiring 32 can be improved.
（ト）発明の効果
以上のようにこの発明によれば、半導体基仮上方に形成
されたキャパシタ電極層上に第１および第２絶禄膜を順
次積層してなる層間絶縁層を形成し、ゲート電極間の眉
間絶縁膜を開口して、コンタクトホールを形成するに際
して、第１および第２絶縁膜間に上層の第２絶縁膜をエ
ッチングする時の対エッチングバリア層を挿入し、コン
タクトホール形成領域の第２絶縁膜を除去した後、その
直下の露出されたバリア層の表面を酸化し、しかる後そ
のバリア層および下層の第ｌ絶縁膜を除去してコンタク
トホールを形成するようにしたので、層間絶禄膜の膜質
を向上させながら第１絶縁膜のコンタクトホール側壁に
おける部分の膜厚を除去することなく維持でき、これに
より高耐圧で高信頼性の眉間絶縁膜を形或できて眉間絶
縁膜上に形成される配線層とキャパシタ電極層間のリー
ク電流を抑制できろとともに、配線層とゲート電極間の
リーク電流も減少できる効果がある。(G) Effects of the Invention As described above, according to the present invention, an interlayer insulating layer is formed by sequentially laminating the first and second isolation films on the capacitor electrode layer formed temporarily above the semiconductor substrate, When forming a contact hole by opening the insulating film between the eyebrows between the gate electrodes, an etching barrier layer is inserted between the first and second insulating films for etching the upper second insulating film to form a contact hole. After removing the second insulating film in the region, the exposed surface of the barrier layer immediately below it is oxidized, and then the barrier layer and the underlying first insulating film are removed to form a contact hole. , while improving the film quality of the interlayer isolation film, the film thickness of the first insulating film on the side wall of the contact hole can be maintained without removing it, thereby forming a high-voltage and highly reliable glabellar insulating film. This has the effect of suppressing leakage current between the wiring layer formed on the insulating film and the capacitor electrode layer, as well as reducing leakage current between the wiring layer and the gate electrode.
第１図はこの発明の一実施例を説明するための製造工程
説明図、第２図は従来例を説明するための製造工程説明
図である。
ｌ・・・・・・ＳＬ基板、
２・・・・・・ゲート電極、
５・・・・・・ノードボリＳｉ膜、
６・・・・・・Ｓｉｎｓのキャパシタ絶縁膜、７・・・
・・・プレートポリＳｉ膜、
８・・・・・・コンタクトホール、
９・・・・・・Ｓｉｆｔ膜（第ｌ絶縁膜）、Ｏ・・・・
・・ＳｔＪ＊膜（対エッチングバリア膜）、３１・・・
・・・ＢＰＳＧ膜（第２絶縁膜）、３２・・・・・・Ａ
Ｉ−Ｓｉの配線層、３３・・・・・・フォトレジスト膜
、
３３ａ・・・・・・ビットラインコンタクト穴、４０・
・・・・・キヤパンク電極層、
（Ｂ）・・・・・・コンタクトホール形成領域。
剪 １ 防
ＣＢ’）FIG. 1 is a manufacturing process explanatory diagram for explaining an embodiment of the present invention, and FIG. 2 is a manufacturing process explanatory diagram for explaining a conventional example. 1...SL substrate, 2...Gate electrode, 5...Node polygon Si film, 6...Sins capacitor insulating film, 7...
...Plate poly-Si film, 8...Contact hole, 9...Sift film (lth insulating film), O...
...StJ* film (anti-etching barrier film), 31...
...BPSG film (second insulating film), 32...A
I-Si wiring layer, 33... Photoresist film, 33a... Bit line contact hole, 40.
... Capacity electrode layer, (B) ... Contact hole formation region. Shearing 1 Anti-CB')
Claims (1)
形成領域を除く領域全面に、キャパシタ電極層を形成し
、続いて、コンタクトホール形成領域を含む全面に第１
絶縁膜、対エッチングバリア膜、平坦化のための第２絶
縁膜およびフォトレジスト膜を順次積層し、次に、コン
タクトホール形成領域上のフォトレジスト膜を除去して
コンタクトを開口し、そのコンタクトを介してエッチン
グによりコンタクトホール形成領域上の第２絶縁膜を除
去してコンタクトホール形成領域上に対エッチングバリ
ア膜を露出させ、さらに残存するフォトレジスト膜を除
去した後、露出された対エッチングバリア膜の表面を水
蒸気雰囲気で酸化し、しかる後上記露出された対エッチ
ングバリア膜のうちコンタクトホール形成領域中央部分
の対エッチングバリア膜およびその直下の第１絶縁膜を
除去してコンタクトホールを形成し、コンタクトホール
を含む全面に配線層を形成することを特徴とする半導体
装置の製造方法。1. A capacitor electrode layer is formed on the entire surface of the semiconductor substrate except for the contact hole formation region between the gate electrodes, and then a first capacitor electrode layer is formed on the entire surface including the contact hole formation region.
An insulating film, an anti-etching barrier film, a second insulating film for planarization, and a photoresist film are sequentially laminated, and then the photoresist film on the contact hole formation area is removed to open a contact. After removing the second insulating film on the contact hole forming region through etching to expose the anti-etching barrier film on the contact hole forming region, and further removing the remaining photoresist film, the exposed anti-etching barrier film is removed. oxidizing the surface of the etching barrier film in a water vapor atmosphere, and then removing the etching barrier film in the central part of the contact hole formation region and the first insulating film immediately below the exposed etching barrier film to form a contact hole; A method for manufacturing a semiconductor device, comprising forming a wiring layer over the entire surface including contact holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1161415A JPH0325930A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1161415A JPH0325930A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0325930A true JPH0325930A (en) | 1991-02-04 |
Family
ID=15734664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1161415A Pending JPH0325930A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325930A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0574958A (en) * | 1991-09-13 | 1993-03-26 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2007081250A (en) * | 2005-09-15 | 2007-03-29 | Tdk Corp | Face mounted electronic component |
| US7922060B2 (en) | 2004-01-13 | 2011-04-12 | Max Co., Ltd. | Stapler |
| JP4734906B2 (en) * | 2004-12-07 | 2011-07-27 | ソニー株式会社 | Information processing apparatus, information recording medium, information processing method, and computer program |
| JP4750038B2 (en) * | 2003-11-26 | 2011-08-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | System, method, and service for distributing and playing multimedia content on physical media |
-
1989
- 1989-06-23 JP JP1161415A patent/JPH0325930A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0574958A (en) * | 1991-09-13 | 1993-03-26 | Nec Corp | Semiconductor device and manufacture thereof |
| JP4750038B2 (en) * | 2003-11-26 | 2011-08-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | System, method, and service for distributing and playing multimedia content on physical media |
| US7922060B2 (en) | 2004-01-13 | 2011-04-12 | Max Co., Ltd. | Stapler |
| US8348121B2 (en) | 2004-01-13 | 2013-01-08 | Max Co., Ltd. | Stapler |
| JP4734906B2 (en) * | 2004-12-07 | 2011-07-27 | ソニー株式会社 | Information processing apparatus, information recording medium, information processing method, and computer program |
| JP2007081250A (en) * | 2005-09-15 | 2007-03-29 | Tdk Corp | Face mounted electronic component |
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