1242279 l4265twf.doc/m 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構及其製程，且特 別是有關於一種覆晶式四方扁平無接腳封裝(FHp chip Quad Flat Non-leaded package，fC-QFN package)結構及 其製程。 【先前技術】 半導體工業是近年來發展速度最快的高科技工業之 -’隨著電子技術的日新月異，高科技電子產業的相繼 問世，使得更人性化、功能更佳的電子產品不斷地推陳 出新，並朝向輕、薄、短、小的趨勢設計。目前在半導 體製程當中，晶片尺寸封裝(Chip Scale Package，csp)結 構為兼具薄型化財、高紐表現與高散鮮之封裝結 構。其中，四方扁平無接腳封裝結構即屬於晶片尺寸封 裝結構。此種晶片尺寸封裝結構非常適合於需要高頻傳 輸、重量輕與微小尺寸之電子產品，例如通訊產品與可 攜式電子產品。 圖1緣示為-習知四料平錢腳封裝結構之剖面 圖。請參照圖1 ’習知四方扁平無接聊封裝結構1〇〇係 由一導線架（lead frame)110、一晶片12〇、多個凸塊 (bump)130及一封裝膠體(m〇Iding c〇mp〇如仙所構 成其中’日日片120之主動表面（active surface)122上且 有多個焊塾(b〇nding pad)! 24，且晶片！ 2〇係藉由凸塊π〇 以覆晶方式與導線架110電性連接。封裝膠體140包覆 晶片120,且填充於導線架11〇、晶片12〇與凸塊13〇 1242279 l4265twf.doc/m 之門仁"卩刀‘線架110係暴露於封裝膠體140外。 在習知四方扁平無接腳封裝結構100中，係以錫錯 合金為四塊m之主要材質。由於在以石夕為主要材質之 晶片120與金屬材質之導線架11G g，存在著極大的敎 膨脹係數(Coefficient of Thermal Expansi〇n，cte)差異， 再加上錫㈣質之凸塊13G的炫點為183χ：，而所需的 迴焊_〇W)溫度更高達22(rc，因此凸塊13〇在迴焊後 由熔點183C降至室溫的過程中，就會累積極大的殘留 應力（residual stress)於凸塊130内。如此一來，凸塊13〇 將極易在承受數次熱循環後產生破裂（crack)，進而導致 四方扁平無接腳封裝結構100之可靠度的下降。此外， 由於錫錯材質之凸塊130的形成需使用微影 (photolithography)、蝕刻（etching)及網版印刷(stencil print) 等製程，因此存在凸塊130成本過高的缺點。 【發明内容】 本發明的目的就是在提供一種覆晶式四方扁平無接 腳封裝結構，適於降低製作成本並提升產品可靠度。 本發明的再一目的是提供一種覆晶式四方扁平無接 腳封裝製程，適於降低製作成本並提升產品可靠度。 本發明提出一種覆晶式四方扁平無接腳封裝結構， 其係由一導線架、一晶片、多個柱狀金凸塊(gold stud bump)、一導電膠及一封裝膠體所構成。其中，晶片配 置於導線架上方，且具有一背面與對應背面之一主動表 面。柱狀金凸塊配置於晶片之主動表面與導線架之間。 導電膠配置於柱狀金凸塊接觸導線架處。封裝膠體包覆 1242279 l4265twf.doc/m 晶片、柱狀金凸塊與部分導線架。 本發明再提出-種覆晶式四方扁平無接腳封裝結 構’其係由一導線架、一晶片、多個凸塊、一 -封裝膠體所構成。其中，晶片配置於導線架上方:且 具有-背©與對應背面之—絲表面。凸塊配置於晶片 之主動表面與導線架之間。導電膠配置於凸塊接觸導線 4處且$電膠具有奈米級尺寸的多個導電顆粒。導電 顆粒之雜低於凸塊之㈣。封㈣體包覆 與部分導線架。 本發明另提出一種覆晶式四方扁平無接腳封裝製 私’其係先提供-晶片。晶片具有—背面與對應背面之 一主動表面。接著，形成多個柱狀金凸塊於晶片之主動 表面上。之後，沾附(dipping)一導電膠於柱狀金凸塊上。 然後，使晶片藉由柱狀金凸塊與導電膠而電性連接至一 導線架。最後，填充一封裝膠體，以使其包覆晶片、柱 狀金凸塊與部分導線架。 本發明又提出一種覆晶式四方扁平無接腳封裝製 耘，其係先提供一晶片，晶片具有一背面與對應背面之 一主動表面。接著，形成多個凸塊於晶片之主動表面上。 之後，沾附一導電膠於凸塊上。其中，導電膠具有奈米 級尺寸的多個導電顆粒，且導電顆粒之熔點低於凸塊之 炫點。然後，使晶片藉由凸塊與導電膠而電性連接至一 導線架。最後，填充一封裝膠體，以使其包覆晶片、凸 塊與部分導線架。 綜上所述，在本發明之覆晶式四方扁平無接腳封裝 1242279 l4265twf.doc/m :構:打線製程所形成之柱狀金凸 之錫錯凸塊。再者、I㈣微影、㈣與印刷所形成 =點較低，因此經==以= 平無接腳封I结構的可靠性。 升復曰曰式四方爲 顯易ΐ讓，優點能更明 細說明如下。例’並配合所關式，作詳 【實施方式】 正此f 2A〜2G緣示為本發明—實施例之覆晶式四方扁 平無接腳封裝製程的流程剖面圖。 明先參照圖2A，本發明一實施例之覆晶式四方扁 平，接腳封裝製程係先提供一晶片210。晶片210具有 一月面212與對應背面212之一主動表面214。晶片21〇 之主動表面214上例如配置有多個焊墊2ΐό。 接著請參照圖2B，形成多個柱狀金凸塊22〇於焊 墊216上。其中’形成柱狀金凸塊220之方法例如係使 用一打線設備（圖未示）所進行。此外，亦可在同一個焊 墊216上進行兩次打線，以形成如圖2B所示之堆疊式 柱狀金凸塊220。當然，每個柱狀金凸塊220亦可僅以 一次打線而形成。 接著請參照圖2C，例如將晶片210翻覆，以使主 動表面214朝下而沾附一導電膠230於柱狀金凸塊220 上0 接著請參照圖2D，例如更形成一導熱連接件240 1242279 l4265twf.doc/m 於晶片2川之主動表面214上。在本實施例中，導熱連 接件240係以具有高導熱係數之導熱膠為佳，而導熱連 接件240具有導電性或不具導電性皆可。 、接著請參照圖2E，使晶片210藉由柱狀金凸塊22〇 與導電膠230而電性連接至一導線架25〇。圖中導線 架250以虛線繪示部分係表示將於封裝完成後切除。在 本實施例中，導電膠230可為一般常見之銀膠⑽· epoxy)。當導電膠230為一般常見之銀膠時，則使晶片 210電性連接至導線架250之方法例如係將其置放於一 烤箱（圖未示）中進行烘烤，以使導電膠23〇内的熱固化 膠體固化，進而確保柱狀金凸塊22〇、導電膠、盥 線架250之間的電性連接關係。 > 此外，導電膠230亦可由一溶劑及摻雜於溶 多個導電顆粒（圖未示）所構成。其中，導電顆粒二尺 係屬於奈米級的尺寸，且以小於1〇奈米為佳。經研究 發現，物質在經過奈米化後其物理性質會產生變化。= 銀質的奈米級導電顆粒為例，其熔點僅約3〇〇。匸。另外， 導電顆粒之材質也可使用金、銅、鋁或其他奈米化後熔 點低於柱狀金凸塊220之熔點的導電材質。當導電膠ί 為溶劑及摻雜於溶劑内之奈米級尺寸的導電顆粒所才 時，使晶片210電性連接至導線架25〇之方法例如 其先置放於一烤箱（圖未示）中進行烘烤以去除溶劑，' 著再以一迴焊爐（圖未示）進行加熱，以使導電膠 奈米級尺寸的導電顆粒能互相熔接。當然，溶劑之去陝 及導電顆粒之互相熔接亦可於同一製程設備中—"二 1242279 14265twf.doc/m 成。如此一來，即可在柱狀金凸塊220與導線架250之 間獲得可靠度極佳的電性連接關係。 另外’本實施例之導線架250例如包括一散熱塊 與圍繞散熱塊254之多個接腳部252，且散熱塊254與 接腳部252係彼此分離。當晶片210配置於導線架25〇 上後，柱狀金凸塊220係位於晶片210之主動表^ 與接腳部252之間，導熱連接件24〇係位於晶片21〇之 主動表面214與散熱塊254之間。換言之，晶片21〇在 做動時所產生的熱量可經由導熱連接件24〇而傳遞 熱塊254，進而增強晶片21〇之散熱效率。 月 接著請參照圖2F，填充—封⑽體26()，以使並勺 覆晶片210、柱狀金凸塊22〇與部分導線架25〇。在= 充封裝膠體260後，即完成覆晶式四 = 200 „ t , a ,a ^ ^ 之外觀例如為爲平的四邊形立方體。此外， 背面加可暴露於外界或被封裝膠體260所Ϊ蓋。之 更配ί者^照圖2G ’在填充封褒膠體260後，例如 更配置一散熱片27〇於晶片2〗〇 匕例如 例如係藉由—導熱黏著層28q 212日上。政熱片 於背面212上。或者，鸯埶m 而黏者於晶片21〇之 的同時，藉由封裝膠體26 ^*於填充封裝膠體260 片210之背面212上。、政熱片270依附配置於晶 接著請再參照圖2(}，本 方扁平無接腳封裝結構2Θ。幺例之覆晶式四 加、多個柱狀金凸塊22〇、導線架㈣、晶片 蛉電膠230及封裝膠體26〇 1242279 所構成。其中’晶片210配置於導線架250上方。晶片 210具有一背面212與對應背面212之一主動表面214。 柱狀金凸塊220配置於晶片21〇之主動表面214與導線 架250之間。導電膠230配置於柱狀金凸塊22〇接觸導 線架250處。封裝膠體260包覆晶片210、柱狀金凸塊 220與部分導線架250。 此外，導電膠230例如為一般常見之銀膠。或者， 導電膠230具有奈米級尺寸的多個導電顆粒（圖未示）， 且導電顆粒之熔點低於柱狀金凸塊22〇之熔點。同時， 奈米級尺寸的導電顆粒之材質可為金、銀、銅、鋁或其 他導電材質。 另外其中柱狀金凸塊220例如為堆疊式柱狀金凸 塊。覆晶式四方扁平無接腳封裝結構2〇〇可更包括導埶 連接件240 ’且導線架25〇例如包括散熱塊254與圍^ 散熱塊254之多個接腳部252。散熱塊254與接腳部况 係彼此分離。柱狀金凸塊22〇係位於晶片2ig之主動表 面214與接腳部252之間，導熱連接件240係、位於晶片 210之主動表面214與散熱塊254之間。 包括散熱片270 外，晶片210夕 其配置於晶片 再者，覆晶式四方扁平無接腳封裝結構2〇〇例如更 21〇之背面212上。此 片270之間例如配置有 外，晶片210之背面212與散熱片 一導熱黏著層280。1242279 l4265twf.doc / m IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a chip packaging structure and process, and more particularly to a flip-chip quad flat no-pin package (FHp chip Quad Flat Non-leaded package (fC-QFN package) structure and its process. [Previous technology] The semiconductor industry is one of the fastest-growing high-tech industries in recent years-'With the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products continue to be introduced. And towards the trend of light, thin, short, small design. At present, in the semiconductor system process, the chip scale package (CSP) structure is a package structure that combines thinness, high performance, and high freshness. Among them, the square flat pinless package structure belongs to the chip size package structure. This chip-size package structure is very suitable for electronic products that require high-frequency transmission, light weight and tiny size, such as communication products and portable electronic products. Fig. 1 is a cross-sectional view of a conventional four-pin flat-pin package structure. Please refer to FIG. 1 'The conventional Sifang flat contactless packaging structure 100 is composed of a lead frame 110, a chip 120, a plurality of bumps 130, and a packaging gel (m〇Iding c). 〇mp〇 As shown in the figure, the active surface 122 of the daily film 120 has a plurality of bonding pads! 24, and the wafer! 2 is formed by the bump π〇 The chip-on-chip method is electrically connected to the lead frame 110. The encapsulant 140 covers the chip 120, and is filled in the lead frame 110, the chip 120, and the bumps 13〇1242279 l4265twf.doc / m. The frame 110 is exposed to the packaging colloid 140. In the conventional square flat pinless packaging structure 100, the tin is used as the main material of four m. Because the wafer 120 and the metal material are mainly made of Shixi There is a huge difference in Coefficient of Thermal Expansion (cte) of the lead frame 11G g. In addition, the dazzling point of the 13G solder bump 13G is 183 × :, and the required re-soldering_〇 W) The temperature is as high as 22 (rc), so the bump 13 will decrease from the melting point of 183C to room temperature after reflow. Positive residual stress is in the bump 130. In this way, the bump 13 will easily crack after being subjected to several thermal cycles, which in turn leads to the square flat pinless packaging structure 100. Reliability is reduced. In addition, since the formation of the bump 130 of tin-tin material requires the use of processes such as photolithography, etching, and stencil print, there is a disadvantage that the cost of the bump 130 is too high [Summary of the Invention] The object of the present invention is to provide a flip-chip tetragonal flat contactless packaging structure, which is suitable for reducing manufacturing costs and improving product reliability. Another object of the present invention is to provide a flip-chip tetragonal flat contactless packaging structure. The pin packaging process is suitable for reducing manufacturing costs and improving product reliability. The present invention provides a flip-chip tetragonal flat pinless packaging structure, which consists of a lead frame, a chip, and a plurality of columnar gold bumps (gold). Stud bump), a conductive adhesive and a packaging gel. The chip is arranged above the lead frame and has an active surface on the back and the corresponding back. Columnar gold The bump is arranged between the active surface of the chip and the lead frame. The conductive glue is arranged at the position where the columnar gold bumps contact the lead frame. The encapsulating gel covers the 1242279 l4265twf.doc / m wafer, the columnar gold bumps and part of the lead frame. The present invention further proposes a flip-chip type tetragonal flat pinless packaging structure, which is composed of a lead frame, a chip, a plurality of bumps, and a packaging encapsulant. Wherein, the chip is arranged above the lead frame and has a silk surface with a back surface and a corresponding back surface. The bump is disposed between the active surface of the chip and the lead frame. The conductive adhesive is arranged at the bump contact wires 4 and the conductive adhesive has a plurality of conductive particles with a nanometer size. The impurities of conductive particles are lower than those of bumps. The enclosure is covered with a part of the lead frame. The present invention also proposes a flip-chip quad flat flat pinless packaging system, which is provided first-chip. The wafer has an active surface with a back surface and a corresponding back surface. Next, a plurality of columnar gold bumps are formed on the active surface of the wafer. After that, a conductive adhesive is dipping on the pillar-shaped gold bumps. Then, the chip is electrically connected to a lead frame through the columnar gold bumps and the conductive adhesive. Finally, an encapsulant is filled so that it covers the wafer, the columnar gold bumps, and part of the lead frame. The present invention also proposes a flip-chip rectangular flat contactless package, which first provides a wafer, and the wafer has an active surface on a back surface and a corresponding back surface. Next, a plurality of bumps are formed on the active surface of the wafer. After that, a conductive adhesive is attached to the bump. Among them, the conductive adhesive has a plurality of nanometer-sized conductive particles, and the melting point of the conductive particles is lower than the dazzling point of the bump. Then, the chip is electrically connected to a lead frame through the bump and the conductive adhesive. Finally, an encapsulant is filled so that it covers the wafer, bumps and some lead frames. To sum up, in the flip-chip tetragonal flat no-lead package of the present invention 1242279 l4265twf.doc / m: Structure: a columnar gold convex tin error bump formed by a wire bonding process. Furthermore, the dots formed by I ㈣ lithography, ㈣, and printing are low, so the reliability of the I structure is sealed by the == to = flat. Sheng Fu said that the Quartet is easy to yield, the advantages can be explained in more detail as follows. Example ’and the related formula for details. [Embodiment] The f 2A ~ 2G edge is shown as a cross-sectional view of the process of the flip-chip tetragonal flat contactless packaging process of the present invention—the embodiment. Referring to FIG. 2A next, a flip-chip tetragonal flat panel according to an embodiment of the present invention. The pin packaging process first provides a chip 210. The wafer 210 has an active surface 214 having a meniscus 212 and a corresponding back surface 212. The active surface 214 of the wafer 21 is configured with, for example, a plurality of pads 2. Referring to FIG. 2B, a plurality of columnar gold bumps 22 are formed on the bonding pad 216. Among them, the method of forming the columnar gold bumps 220 is performed using, for example, a wiring device (not shown). In addition, two wire bonding operations can be performed on the same pad 216 to form a stacked columnar gold bump 220 as shown in FIG. 2B. Of course, each of the columnar gold bumps 220 can also be formed with only one wire. 2C, for example, the chip 210 is turned over so that the active surface 214 faces downward and a conductive adhesive 230 is attached to the columnar gold bump 220. Then, referring to FIG. 2D, for example, a thermally conductive connection member 240 1242279 is formed. l4265twf.doc / m is on the active surface 214 of the chip. In this embodiment, the thermally conductive connection member 240 is preferably a thermally conductive adhesive having a high thermal conductivity, and the thermally conductive connection member 240 may be conductive or non-conductive. 2. Next, referring to FIG. 2E, the chip 210 is electrically connected to a lead frame 25 through a columnar gold bump 22 and a conductive adhesive 230. The part of the lead frame 250 shown by the dotted line in the figure indicates that it will be cut off after the packaging is completed. In this embodiment, the conductive adhesive 230 may be a common silver adhesive (epoxy). When the conductive adhesive 230 is a common silver adhesive, the method for electrically connecting the chip 210 to the lead frame 250 is, for example, placing it in an oven (not shown) and baking to make the conductive adhesive 23 °. The internal thermal curing gel is solidified, thereby ensuring the electrical connection relationship between the columnar gold bumps 22, the conductive adhesive, and the wire rack 250. > In addition, the conductive paste 230 may be composed of a solvent and a plurality of conductive particles (not shown) doped in the solvent. Among them, the two-foot conductive particles belong to the nanometer size, and it is preferably less than 10 nanometers. It has been found through research that the physical properties of a substance will change after it is nanometerized. = Silver nano-scale conductive particles as an example, its melting point is only about 300. Alas. In addition, as the material of the conductive particles, gold, copper, aluminum, or other conductive materials having a melting point lower than the melting point of the columnar gold bumps 220 after nanometerization can also be used. When the conductive adhesive is made of a solvent and nanometer-sized conductive particles doped in the solvent, a method for electrically connecting the chip 210 to the lead frame 25 is placed in an oven (not shown). Baking is performed in order to remove the solvent, and then heating is performed in a reflow oven (not shown) so that conductive particles of nanometer size of conductive rubber can be welded to each other. Of course, the removal of the solvent and the welding of the conductive particles can also be performed in the same process equipment— " 1242279 14265twf.doc / m. In this way, a highly reliable electrical connection relationship can be obtained between the columnar gold bump 220 and the lead frame 250. In addition, the lead frame 250 of this embodiment includes, for example, a heat dissipation block and a plurality of pin portions 252 surrounding the heat dissipation block 254, and the heat dissipation block 254 and the pin portions 252 are separated from each other. When the chip 210 is disposed on the lead frame 25 °, the columnar gold bump 220 is located between the active surface ^ and the pin portion 252 of the wafer 210, and the thermally conductive connector 24 ° is located on the active surface 214 of the wafer 21 and dissipates heat. Between blocks 254. In other words, the heat generated by the wafer 21o during operation can be transferred to the thermal block 254 via the thermally conductive connection 24o, thereby enhancing the heat dissipation efficiency of the wafer 21o. Next, please refer to FIG. 2F, filling-sealing body 26 (), so as to cover the wafer 210, the columnar gold bump 22, and a part of the lead frame 25. After the encapsulation gel 260 is filled, the flip-chip four = 200 „t, a, a ^ ^ is, for example, a flat rectangular cube. In addition, the back surface can be exposed to the outside or covered by the encapsulation gel 260. It is more suitable as shown in FIG. 2G. After filling the sealing colloid 260, for example, a heat sink 27 ° is further arranged on the wafer 2. For example, the heat conductive adhesive layer 28q 212 is used. On the back surface 212. Alternatively, at the same time as 鸯 埶 m and sticking to the wafer 21, the packaging gel 26 ^ * is filled on the back surface 212 of the filling packaging gel 260 sheet 210. The thermal sheet 270 is attached to the crystal Please refer to FIG. 2 (} again, this side flat pinless package structure 2Θ. For example, a flip-chip four plus, a plurality of columnar gold bumps 22, lead frame ㈣, chip 蛉 electric glue 230 and packaging gel 26 〇1242279. Among them, the wafer 210 is disposed above the lead frame 250. The wafer 210 has a back surface 212 and an active surface 214 corresponding to the back surface 212. The columnar gold bump 220 is disposed on the active surface 214 of the wafer 21 and the lead frame. 250. The conductive adhesive 230 is arranged on the columnar gold bumps 22 At the frame 250. The encapsulation gel 260 covers the chip 210, the columnar gold bump 220, and a part of the lead frame 250. In addition, the conductive paste 230 is, for example, a common silver paste. Alternatively, the conductive paste 230 has a plurality of nanometer-sized sizes. The conductive particles (not shown), and the melting point of the conductive particles are lower than the melting point of the columnar gold bumps 22. At the same time, the nano-sized conductive particles can be made of gold, silver, copper, aluminum or other conductive materials. In addition, the pillar-shaped gold bump 220 is, for example, a stacked pillar-shaped gold bump. The flip-chip tetragonal flat pinless package structure 2000 may further include a conductive connector 240 ′ and the lead frame 25 includes a heat sink 254, for example. A plurality of pin portions 252 surrounding the heat dissipation block 254. The heat dissipation block 254 and the pin portions are separated from each other. The columnar gold bump 22 is located between the active surface 214 of the chip 2ig and the pin portion 252, and conducts heat. The connecting member 240 is located between the active surface 214 and the heat sink 254 of the chip 210. In addition to the heat sink 270, the chip 210 is arranged on the chip, and the flip-chip rectangular flat no-lead package structure 200, for example, more 21〇 on the back 212. This piece of 270 of For example arranged outside the rear surface 210 of the wafer 212 with a thermally conductive adhesive layer heat sink 280.
1242279 l4265twf.doc/m 裝結構200的差異在於，導線架25〇之散熱塊254與晶 片210之連接方式的不同。在本實施例中，導線架mo 之散熱塊254係藉由至少一個柱狀金凸塊220及導電膠 230而連接至晶片21〇之主動表面214。換言之晶片210 在作動時所產生的熱量可經由柱狀金凸塊22〇而傳遞至 月欠熱塊254，進而增強晶片210之散熱效率。這些連接 散熱塊254之柱狀金凸塊220及導電膠230係與連接接 腳部252之柱狀金凸塊22〇及導電膠23〇同步形成。 圖4繪示為本發明再一實施例之覆晶式四方扁平無 接腳封裝結構的剖面圖。請參照圖4，覆晶式四方扁平 無接腳封裝結構400與圖2之覆晶式四方扁平無接腳封 裝結構200的差異有下列幾點： (1) ·凸塊420並不限定於以打線設備所形成之柱狀 凸塊，亦可利用其他製程來形成凸塊42〇。 (2) ·導電膠430必須具有奈米級尺寸的多個導電顆 粒（圖未示），且導電顆粒之熔點必須低於凸塊42〇之 點。 (3)·凸塊420之材質並不限定於金，亦可使用苴他 熔點高於導電膠43G中導電顆粒之熔點的材f。/、 在覆晶式四方扁平無接腳封裝結構400中，晶片41〇 可如圖3之覆晶細方扁平無接腳封裝結構細般，將 ::::產生之ί量藉由凸塊420而傳遞至導線架450 棚二㈤然，覆晶式四方扁平無接腳封裝結構 棚中，晶片做動時所產生之熱量亦可藉由一導】 連接件(圖未7F)而傳遞至導線架之散熱塊物。 1242279 14265twf.d〇c/n 構件=圖 構200树以，此處即不再贅^式彳扁平無接腳封裝結 Γ20 ^^ta00 再贅述。請參照圖4，x二相似’因此相似處在此亦不 腳封裝製程與圖2A〜2G;施式四方扁平無接 的形成並不限定於以打線H之差；在於’凸塊420 來形成凸塊42G。 又備細’亦可利用其他製程 結構:中在::;月之覆晶式四方扁平無接腳封裝 塊，因此成本可低於之枝狀仏 =，，，若採 加大’因此可降低熱膨脹係數 響:、同時復==平無接腳封裝結構之可靠度的影 在電Γ接晶片與導線架時僅需固 ί==:内尺寸之導電顆粒燒結，會產 另外’右㈣具奈米級尺寸之導電難的導電勝， 2可用低溫製程將導電顆粒燒結，因此可提高晶片盘 ^線架間電性連接關係的可靠度。再者，散執片及 采之散熱塊的設計1可提高覆晶式四方扁平無接腳封 1242279 l4265twf.doc/m 裝結構的散熱效率。 構及其製程!4明之覆晶式四方扁平無接腳封裝結 不僅可降低成本，更可提高 雖然本發明已以較佳恭 產口口良率。 以限定本發明^ 貝例揭路如上，然其並非用 精神和範圍内，當可；：脫:本發明之 ，保護範㈣視後社申請專因此本發明 【圖式簡單_】τ "刊”所界定者為準。 圖。圖】•為-習知四方扁平無接腳封裝結構之剖面 圖 平無接圖二2製 ，為本發明另1施例之覆晶式四方扁平無 圖3繪 接腳封裝結構的剖面圖 施例之覆晶式四方扁平無 圖4綠示為本發明再一 接腳封裝結構的剖面圖 【主要元件符號說明】 100 110 120 122 124 130 ： 140 ： 200、 四方扁平無接腳金 導線架 晶片 主動表面 焊墊 凸塊 封裝膠體 300 寸裝結構 、400 :覆晶 + ^ 曰式四方扁平無接腳封裝結 構 14 1242279 l4265twf.doc/m 210、410 :晶片 212、412 :背面 214、414 :主動表面 216 :焊墊 220 :柱狀金凸塊 230、430 :導電膠 240 :導熱連接件 250、450 :導線架 252、452 :接腳部 254、454 :散熱塊 260、460 :封裝膠體 270、470 :散熱片 280、480 :導熱黏著層 420 :凸塊 151242279 l4265twf.doc / m The difference between the mounting structure 200 is that the connection method between the heat sink 254 of the lead frame 25 and the wafer 210 is different. In this embodiment, the heat dissipation block 254 of the lead frame mo is connected to the active surface 214 of the chip 21 through at least one columnar gold bump 220 and a conductive adhesive 230. In other words, the heat generated by the wafer 210 during operation can be transferred to the moon underheating block 254 through the columnar gold bumps 22, thereby enhancing the heat dissipation efficiency of the wafer 210. The columnar gold bumps 220 and the conductive paste 230 connected to the heat sink 254 are formed in synchronization with the columnar gold bumps 22 and the conductive paste 23o connected to the pin 252. FIG. 4 is a cross-sectional view of a flip-chip tetragonal flat contactless package structure according to another embodiment of the present invention. Please refer to FIG. 4. The difference between the flip-chip tetragonal flat contactless package structure 400 and the flip-chip quadrilateral flat contactless package structure 200 of FIG. 2 is as follows: (1) The bump 420 is not limited to The columnar bumps formed by the wire bonding equipment can also be formed by other processes. (2) The conductive adhesive 430 must have a plurality of nano-sized conductive particles (not shown), and the melting point of the conductive particles must be lower than the bump 42 °. (3) The material of the bump 420 is not limited to gold, and a material f whose melting point is higher than that of the conductive particles in the conductive adhesive 43G may be used. /. In the flip-chip tetragonal flat contactless package structure 400, the chip 41 can be as thin as the flip-chip thin rectangular flat contactless package structure of FIG. 3, and the amount of :::: generated is raised by the bump 420 is transferred to the lead frame 450. The second shed is sturdy. In the flip chip type quad flat flat no-pin package structure shed, the heat generated when the chip is operated can also be transferred to the lead through the connector (Figure 7F). Cooling block of lead frame. 1242279 14265twf.d〇c / n Component = 200 tree structure, it will not be repeated here ^ flat flat pinless package Γ20 ^^ ta00 Repeated description. Please refer to FIG. 4, x is similar, so the similarity is not included here. The packaging process is not the same as that shown in FIGS. 2A to 2G. The formation of the Shi Qufang flat connection is not limited to the difference of the wire H; Bump 42G. You can also prepare it in detail. Other process structures can also be used: in the ::; moon-covered quartet flat flat no-pin package, so the cost can be lower than the dendrite 仏 =, if it is increased, it can be reduced Coefficient of thermal expansion: At the same time, the reliability of the package structure without flat pins is only required to be fixed when connecting the chip to the lead frame. ==: The conductive particles of the internal size are sintered, which will produce another Nanometer-sized conductive is difficult to conduct. 2 The conductive particles can be sintered at a low temperature process, so the reliability of the electrical connection relationship between the wafer and the wire frame can be improved. In addition, the design of the heat sink and the heat sink block 1 can improve the heat dissipation efficiency of the flip-chip tetragonal flat footless seal 1242279 l4265twf.doc / m. The structure and its process! The chip-on-chip tetragonal flat no-pin package structure of Ming will not only reduce the cost, but also increase the yield. To limit the present invention ^ Example is to uncover the road as above, but it is not within the spirit and scope, when it is available; The definition in the "Journal" shall prevail. Figure. Figure] • is a cross-sectional view of the known Sifang flat flat pinless package structure. Figure 2 is a system, which is a flip-chip tetragonal flat figure of another embodiment of the present invention. 3 is a cross-sectional view of the pin package structure. The example of the flip-chip tetragonal flat is shown in FIG. 4. Green is a cross-sectional view of another pin package structure of the present invention. [Description of main component symbols] 100 110 120 122 124 130: 140: 200 , Sifang flat pinless gold lead frame chip active surface pad bump package colloid 300-inch package structure, 400: flip chip + ^ rectangular square flat pinless package structure 14 1242279 l4265twf.doc / m 210, 410: wafer 212, 412: Back surface 214, 414: Active surface 216: Pad 220: Columnar gold bumps 230, 430: Conductive glue 240: Thermally conductive connector 250, 450: Lead frame 252, 452: Pins 254, 454: Heat sinks 260, 460: Encapsulants 270, 470: Heat sinks 280, 48 0: thermally conductive adhesive layer 420: bump 15