1242257 九、發明說明： 【發明所屬之技術領域】 本發明係概括關於一種可變電容(varactor)，尤指一種门日卞具有 南品質因數(Q factor)之PN接面可變電容。 【先前技術】 在現代化資訊產業中，各種數據、資料、訊息、影像等都是以 電子訊號的形式來傳遞，而用來處理電子訊號的處理電路，^就 成為現代資訊產業中最重要的基礎。舉例來說，在—般的資％系 統(像是電腦)中，都要以一時脈來協調數位系統中的各個數 -起運作，因此用來產生時脈的震盛器是現代數位系、统中不^或 缺的重要·構築方塊之-。此外，要協調不同科脈同步(譬如 說在傳輸訊號的it訊系統中），還需要使用鎖相電路；而鎖相電路 中則需要精密的壓控震㈣，以電壓來控制壓控震i器震藍出頻 率不同的震盡訊號，以協調各時脈同步。财，像是在某些精密 的濾波器中，也常使用能調整濾波頻率的電阻_電容(Rc)濾波界。 不論是電阻-電容(RQ遽波器的遽波特性(像是遽波器的通帶頻 寬），或是贼·電容(LC)壓控震魅、的震盪躲(像是震舰號的 頻率）’都可關改變電容值咐絲純。目前已發展出多 種可變電容可朗於積體電路元件中，例如pN二極體、肖基二極 體(Schottky diode)以及金氧半導體(_丨Qxide MOS)電晶體二極體等均為f見制於雙載子電晶體㈣心 1242257 juneticm—，mT)' 互補式金氧半導體（c〇mpi__metai ⑽de semiconductor，CM〇s)電晶體以及雙載子互補式金氧半導 體黾曰曰體(BiCMOS)荨電子元件中之可變電容。 、 請參考第1圖’其繪示的是習知接面可變電容的剖面結構示意 圖。如第1圖所示，在P型基底1〇内形成有N型離子井12以及 複數個隔離結構14，例域溝隔離(shallGwt職h isdatiGn，ST辑 構。隔離結構14係於N型離子井12表面定義出複數個預定區域， 分別用來製作N型摻雜區16以及p型摻雜區18，以形成一具有 PN接面之二鋪結構。當施加—逆向偏壓時，二極體之接面 S產生可視為介電層之空乏區(吻純⑽邮⑽），並使二極體能 在N型摻雜區16、p型摻雜區18等陰極、陽極之二傳導區間等效 為電谷。隨著二極體之陽極、陰極間的跨壓大小調整，空乏區 之寬度會隨之改變，進而達到改變二極體於陽極、陰極間提供的 等效電容值之目的。 請參考第2圖，其繪示的是習知金氧半導體(M〇s)可變電容之 口J面、、^構示思圖。如第2圖所示，習知可變電容形成於N 里井22上’包括多晶矽閘極結構26、設於多晶矽閘極結構26與 N型井22之間閘極介電層28、設於多晶矽閘極結構％兩側之n 型井22内的N+摻雜區24，以及設於多晶矽閘極結構％兩侧之n 型井22内並與N+摻雜區24相鄰接的輕摻雜汲極(lightly doped dram’LDD)25。操作日寺，可使多晶石夕問極結構％作為可變電容之 1242257 陽極㈣e)，而N+摻雜區24作為陰極㈣〇岭 如 項技藝者所知，第丨圖所示之習知接面可變雨 有較見的調頻範_ning 电合，、 品質因數Q值脸。rn A _#瑪，因而 右圖所示之習知_8可變電容則是且 乂 -、禮值，亦即較高的品質因數 ^ 窄的調頻範圍。由上可知，门士、 疋/、缺2為具較 及品質隨⑽、， ° _錢顧可變電容之調頻範圍以 °口 .' ，亚且提供良好之電容-電壓線性關係(c-v Γ改善可_容之紐纽，已絲目«界努力的方 【發明内容】 電 〜士因此，本㈣之目的即在提供—鶴有結構之接面可變 U冓’可以改善可變電容之電性表現。 2明之另-目的在於提供—種可與CMQS製軸容之接面 可受電容及其製法，朗時具備純品質隨Q值。 —依據本發明之較佳實施例，係提供—種接面可㈣容，包含有 ，極’ δ又於-半導體基底的離子井± ; 一問極介電層，設於該 ^與該離子井之間；一第—摻雜區，其具有第-電性，設於該 離子_，作為簡面可魏容之陽極(_如）；以 及-第二摻雜區’其具有與該第—電性相反之第二電性，設於該 1242257 間極與該第-摻雜區相反之一側的該離子井内，作為該州接面可 變電容之陰極其中在操作該接面可變電容時，該間極係 接一閘極電壓VG，例如Vcc或者Vss電壓。 本發明在陽贿_之間並無鱗絕龍域略，因此可以降 低接面可變電容之電阻值，藉此提高品f因數Μ。而在操作時， 閘極接至閘極 vG，使閘極下方的通道累積電子或電洞，更能 進一步降低電阻，改善品質因數Q值。 ，、、、了使貴審查委貞能更近-步瞭解本㈣之舰及技術内 容’請參_下錢本發明之詳細朗與關。細賴圖式僅 供參考與輔職日賴，並_來縣發明加以限制者。 【實施方式】 以下即藉由第3圖至第7 _細朗本㈣之特徵。熟習該項 技六者應在理解本發日狀技術特徵後，瞭解下文情揭露之本發 明較佳實施财解之猶電性(⑽ 及使用材料皆為例示制，柯做均等之變換者 以限制本發明之保護範疇。 〜^用 ^先、參閱第3圖以及第4圖，其中第3圖為本發明較佳實 施例接面可變電容8G之佈局上視示意圖，第4圖為第3圖中沿著 切線AA之接面可變電㈣剖面示意圖。如騎示，本發明較佳 1242257 實施例接面可變電容80係形成於一 N型井100上，而N型井100 了以t成在一 p型石夕基底或石夕覆絕緣(Siiic〇n〇n_insuiat〇r，soi)基 底之表面上(圖未示），型井1〇〇係為淺溝絕緣(shall〇wtrench isolation，STI)區域200所隔離。若n型井1〇〇形成在SOI基底中， 則其下方為一氧化矽絕緣層（圖未示），與811區域2〇〇共同將N 型井100完全電性隔離成為浮置(floating)狀態。 根據本發明較佳實施例，接面可變電容8〇包含有一細長型的 問極101，跨設於N型井1〇〇上方，以及一細長型的閘極1〇2，設 於閘極101 —侧之N型井1〇〇上方。閘極1〇ι以及閘極1〇2可以 為多晶石夕或者金屬所構成。閘極1〇1以及閘極1〇2皆具有兩垂直 侧壁’其上分別形成有側壁子(spacer)1〇la以及1〇2a，且閘極1〇1 以及閘極102與N型井1〇〇分別以閘極介電層101b以及1〇21)做 電性隔離。在閘極1〇1以及閘極1〇2之間的N型井1〇〇内形成有 一 P+摻雜區112，用來作為接面可變電容8〇的陽極(an〇de)。p+摻 雜區 112 可與 P 型輕摻雜汲極(p_^ype iightiy doped drain, PLDD)113 相連，其中P型輕摻雜汲極113係朝向閘極1〇i以及閘極102下 方延伸。 如第4圖所示，在閘極ιοί與P+摻雜區n2相反之一側的n 型井100中形成有一 N+摻雜區114以及一 N型輕摻雜汲極(N-type lightly doped drain，NLDD)121鄰接該N+摻雜區114並橫向延伸至 閘極101側壁子101a下方。在其它實施例中，N型輕摻雜汲極 1242257 (NLDD)121更延伸至閘極ι〇1下方。在閘極i〇2與p+摻雜區ii2 相反之一侧的N型井1〇〇中形成有一 N+摻雜區116以及一 n型輕 摻雜没極(NLDD)122鄰接該N+摻雜區116並橫向延伸至閘極1〇2 的側壁子102a下方，N型輕摻雜汲極(NLDD)122更延伸至閘極 102的正下方。N+摻雜區丨14以及N+摻雜區116係利用内連線做 笔性連接’用以作為接面可變電容⑽的陰極(cathode。此外，為 降低片電阻’在P+摻雜區U2、摻雜區114以及N+摻雜區116 上更形成有自行對準金屬矽化物(salicide)層1〇3。 由圖中可發現，本發明與習知接面可變電容相較，在陽極與陰 極之間並無淺溝絕緣區域阻隔，因此可以降低接面可變電容⑽之 包阻值’藉此提咼品質因數q值。而在操作時，閘極1〇1及搬 係接至-閘極賴Vg。在此實施射，閘極電壓％可以為I 之正電壓。本發明藉由施加正電壓如Vcc於閘極1〇1及1〇2，使閘 極下方的通道積電子，因而可崎低電阻，進而改善品質因數〇 值。而藉由改變陽極⑴與陰極⑴心之間的偏壓(bias)來調整 接面可變電容80之電容值。 厂接著，請參閱第5圖至第8圖，第5圖至第8圖以剖面結構顯 1作如第4圖中本發明較佳實施例接面可變電容80的主要製程 步驟。本發明製作接面可變電容8〇之方法係為cm〇s相容製程。 I先，如第5圖所示，提供一基底，其表面上形成有N型井100， 、由淺溝絕緣區域(圖未示)隔離。接著，於N型井100上形成一 1242257 絕緣層（圖未示）’例如閘極矽氧層。然後於閘極矽氧層上沈積一多 晶矽層（圖未示）’再利用黃光以及蝕刻製程，將多晶矽層以及絕緣 層定義成閘極結構101以及102，其下方分別為絕緣層1〇lb以及 · 102b。 - 接著，如第6圖所示，進rnldd離子佈植，利用適當遮罩 (NLDD imPlantphoto)將閘極結構1〇1以及1〇2之間的區域遮蔽 住，然後進行砷離子佈植，以於閘極結構1〇1以及1〇2之一侧形 成NLDD摻雜區121以及122。 · 如第7圖所示’進行PLDD離子佈植，利用適當遮罩奸dd imPlantph〇to)將閘極結構1〇1以及1〇2之間的區域打開然後進 行侧離子佈植，以於閘極結構1〇1以及1〇2之間的n型井爾中 形成PLDD摻雜區113。 如第8圖所示，接著於閘極1〇1以及1〇2之側壁上形成側壁子 (SPace_la以及隐。然後，利用適當的遮罩⑽如麵沖⑽ 將閘極、、，。構1〇1以及102之間的區域遮蔽住，然後進行&離子佈 ^以於閘極101以及1〇2之一側形成N+換雜區叫以及⑽。 最後，再利用-道光罩以及離子佈植製程於閘極結構_以及脱 之間形成P+摻雜區112。第8圖中之結構繼續進行自行對样化 . 物製程’即形成第4圖巾所示之本發明接面可變電容8G。 ' 12 !242257 此外，請參閱第9圖，其為本發明另一較佳實施例之接面可變 電容800的剖面示意圖。如第9圖所示，本發明另一較佳實施例 接面可變電容800係形成於一 P型井200上。根據本發明另一較 佳貫施例，接面可變電容800包含有一細長型的閘極2〇1，跨設於 P型井200上方，以及一細長型的閘極202，設於閘極2〇1 一側之 P型井200上方。閘極201以及閘極2〇2可以為多晶矽或者金屬所 構成。閘極201以及閘極202皆具有兩垂直側壁，其上分別形成 有側壁子(spacer)201a以及202a，且閘極201以及閘極202與p型 井200分別以閘極介電層2〇ib以及202b做電性隔離。在閘極2〇1 以及閘極202之間的p型井200内形成有一 N+摻雜區212，用來 作為接面可變電容800的陽極(anode)。N+摻雜區212可與N型輕 掺雜汲極(N-type lightly doped drain, NLDD)213 相連，其中 n 型輕 摻雜汲極213係朝向閘極201以及閘極202下方延伸。 在閘極201與N+摻雜區212相反之一侧的P型井200中形成 有一 P+摻雜區214以及一 P型輕摻雜汲極(P-type lightly doped drain，PLDD)221鄰接該P+摻雜區214並橫向延伸至閘極201側壁 子201a下方。在其它實施例中，p型輕摻雜汲極(pldd)221更延 伸至閘極201下方。在閘極202與N+摻雜區212相反之一側的p 型井200中形成有一 P+摻雜區216以及一 P型輕摻雜汲極 (NLDD)222鄰接該P+摻雜區216並橫向延伸至閘極202的侧壁子 202a下方，P型輕摻雜汲極(PLDD)222更延伸至閘極202的正下 方。P+摻雜區214以及P+摻雜區216係利用内連線做電性連接， Ϊ242257 用以作為接面可變電容800的陰極(cathode)。此外，為降低片電 阻，在N+摻雜區212、P+摻雜區214以及P+摻雜區216上更形成 有自行對準金屬石夕化物(salicide)層203。在操作時，閘極2〇1及202 係接至一閘極電壓vG。在此實施例中，閘極電壓Vg可以為v%。 々以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均 等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知接面可變電容的剖面示意圖。 第2圖為習知金氧半導體可變電容之剖面結構示意圖。 第3圖為本發明較佳實施例之接面可變電容之佈局上視示意圖。 第4圖為圖三中沿著切線AA之接面可變電容剖面示意圖: 第5圖至第8圖以剖面結構顯示製作如第4圖中本發明較佳實施 例接面可變電容的主要製程步驟。 土、也 第9圖為本發明另-難實_之接面可變電容剖面示意圖。 【主要元件符號說明】 10 基底 12 離子井 14 隔離結構 16 摻雜區 18 摻雜區 22 N型井 24 N+摻雜區 25 輕摻雜汲極 26 多晶矽閘極結構 28 閘極介電層 80 接面可變電容 100 N型井 12422571242257 IX. Description of the invention: [Technical field to which the invention belongs] The present invention generally relates to a variable capacitor (varactor), especially a PN-junction variable capacitor with a southern quality factor (Q factor). [Previous technology] In the modern information industry, various data, data, messages, images, etc. are transmitted in the form of electronic signals, and the processing circuits used to process the electronic signals have become the most important foundation in the modern information industry. . For example, in a general information system (such as a computer), all clocks in a digital system must be coordinated to operate with a clock. Therefore, the oscillators used to generate clocks are modern digital systems and systems. The important and indispensable in the construction of the box-. In addition, to coordinate the synchronization of different pulses (for example, in an IT signal system transmitting a signal), a phase-locked circuit is also required; in the phase-locked circuit, a precise voltage-controlled oscillator is needed to control the voltage-controlled vibration with voltage i The device shakes out signals at different frequencies to coordinate the synchronization of the clocks. For example, in some precision filters, a resistor-capacitor (Rc) filter world that can adjust the filtering frequency is often used. Whether it is the resistance-capacitance (the wave characteristics of the RQ chirper (such as the passband bandwidth of the chirper), or the thief capacitor (LC) voltage-controlled shock charm, the shock hiding (such as the ship number The frequency) can be changed to change the value of the capacitor, and it is required to change the capacitance value. At present, a variety of variable capacitors have been developed for integrated circuit components, such as pN diodes, Schottky diodes, and metal oxide semiconductors. (_ 丨 Qxide MOS) transistor diodes, etc. are all based on the bipolar transistor 1242257 juneticm-, mT) 'complementary metal-oxide semiconductor (c〇mpi__metai ⑽de semiconductor, CM〇s) transistor And the variable capacitance in the BiCMOS complementary electronic device. Please refer to FIG. 1 ', which shows a schematic cross-sectional structure diagram of a conventional junction variable capacitor. As shown in FIG. 1, an N-type ion well 12 and a plurality of isolation structures 14 are formed in the P-type substrate 10, such as a domain trench isolation (shallGwt, isdatiGn, ST structure. The isolation structure 14 is based on N-type ions. A plurality of predetermined regions are defined on the surface of the well 12 and used to fabricate the N-type doped region 16 and the p-type doped region 18 to form a two-layer structure with a PN junction. When a reverse bias is applied, the two poles The junction S of the body produces a depleted region (kissed pure) which can be regarded as a dielectric layer, and enables the diode to be used in the cathode and anode conduction regions such as the N-type doped region 16, the p-type doped region 18, and the like. The effect is an electric valley. With the adjustment of the voltage across the anode and the cathode of the diode, the width of the empty region will change accordingly, and the purpose of changing the equivalent capacitance value provided by the diode between the anode and the cathode is achieved. Please refer to FIG. 2, which shows a schematic diagram of the structure of a conventional metal oxide semiconductor (M0s) variable capacitor. It is shown in FIG. 2. As shown in FIG. 2, the conventional variable capacitor is formed on The N-well 22 includes a polycrystalline silicon gate structure 26, a gate dielectric layer 28 provided between the polycrystalline silicon gate structure 26 and the N-type well 22, and N + doped regions 24 in the n-type wells 22 on both sides of the polycrystalline silicon gate structure, and lightly doped in the n-type wells 22 on both sides of the polycrystalline silicon gate structure and adjacent to the N + doped regions 24 Drain (lightly doped dram'LDD) 25. By operating Risi, the polycrystalline silicon anode structure% can be used as the 1242257 anode (e) of the variable capacitor, and the N + doped region 24 is used as the cathode. It is known that the conventional interface shown in Figure 丨 has a more common frequency modulation range _ning, a figure of merit Q face. rn A _ # 玛, so the conventional _8 variable capacitor shown on the right is and 乂-, the value, that is, a higher quality factor ^ narrow frequency modulation range. It can be seen from the above that the monk, 疋 /, and missing 2 are compared with the quality, and the frequency modulation range of the variable capacitor of Qian Gu is in °. ', Which provides a good capacitance-voltage linear relationship (cv Γ Improving the capacity _ capacity of the new button, has been the efforts of the world «[Content of the invention] electricity ~, therefore, the purpose of this ㈣ is to provide-the structure of the interface variable U 冓 'can improve the variable capacitor Electrical performance. 2 Another difference-the purpose is to provide-a joint with the CMQS shaft capacity can accept the capacitor and its manufacturing method, Lange has a pure quality with Q value.-According to the preferred embodiment of the present invention, provided -The interface can be contained, including the pole 'δ in the -well of the semiconductor substrate ±; an interlayer dielectric layer is provided between the ^ and the ion well; a first-doped region, which It has the first electrical property, which is provided in the ion _, as a simple anode (_such as); and the second doped region, which has the second electrical property opposite to the first electrical property, is provided in the 1242257. The ion well on the opposite side of the inter-electrode and the first doped region is used as the cathode of the variable capacitor of the state interface. When connecting a variable capacitor, the electrode is connected to a gate voltage VG, such as Vcc or Vss voltage. The present invention does not have scales and scales between the positive and negative electrodes, so the resistance of the variable capacitor at the interface can be reduced. Value, thereby increasing the product f factor M. During operation, the gate is connected to the gate vG, so that the channels below the gate accumulate electrons or holes, which can further reduce the resistance and improve the quality factor Q value. In order to make your review committee more closely-step by step to understand the ship and technical content of this book, please refer to _ under the details of the present invention. The detailed drawings are for reference only and assist the Japanese Lai. The county ’s inventions are limited. [Embodiment] The following is the characteristics of Xilang Benxi by using Figures 3 to 7. Those who are familiar with this technique should understand the technical features of this issue after understanding the technical characteristics of this state of the sun. The electrical properties of the present invention are better implemented (⑽ and the materials used are examples, and Ke does an equivalent transformation to limit the scope of protection of the present invention. ~ ^ Use first, refer to Figure 3 and Figure 4, Figure 3 is a schematic top view of the layout of a variable capacitor 8G in the preferred embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of the variable electrical junction along the tangent line AA in Fig. 3. As shown in the figure, the preferred 1242257 embodiment of the present invention is a variable capacitance 80 formed on an N-type well 100. The N-type well 100 is formed on the surface of a p-type Shixi substrate or a Shixi substrate (Siiiconn_insuiatr, soi) substrate (not shown). The type well 100 is shallow. A trench isolation (STI) region 200 is isolated. If an n-type well 100 is formed in the SOI substrate, a silicon oxide insulating layer (not shown) is formed below it, and it is common with the 811 region 200. The N-type well 100 is completely electrically isolated to a floating state. According to a preferred embodiment of the present invention, the junction variable capacitor 80 includes an elongated question electrode 101 straddling the N-type well 100 and a slim gate 102 arranged on the gate. Above the 101-side N-type well 100. The gate electrode 10m and the gate electrode 102 may be made of polycrystalline stone or metal. Both the gate electrode 101 and the gate electrode 102 have two vertical side walls, and spacers 10a and 102a are formed thereon, respectively, and the gate electrode 101 and the gate electrode 102 and an N-type well are formed. 100 respectively uses gate dielectric layers 101b and 1021) for electrical isolation. A P + doped region 112 is formed in the N-well 100 between the gate electrode 101 and the gate electrode 102, and is used as an anode of the variable capacitor 80. The p + doped region 112 may be connected to a p-type lightly doped drain (PLDD) 113, where the p-type lightly doped drain 113 extends toward the gate 10i and below the gate 102. As shown in FIG. 4, an N + doped region 114 and an N-type lightly doped drain (N-type lightly doped drain) are formed in the n-type well 100 on the opposite side of the gate electrode from the P + doped region n2. NLDD) 121 is adjacent to the N + doped region 114 and extends laterally below the gate electrode 101 sidewall 101a. In other embodiments, the N-type lightly doped drain electrode 1242257 (NLDD) 121 extends below the gate electrode 01. An N + doped region 116 and an n-type lightly doped doped electrode (NLDD) 122 are formed adjacent to the N + doped region in an N-type well 100 on the opposite side of the gate i02 and the p + doped region ii2. 116 extends laterally below the sidewall 102a of the gate 102, and the N-type lightly doped drain (NLDD) 122 extends directly below the gate 102. The N + doped region 丨 14 and the N + doped region 116 are pen-type connections using interconnects to serve as cathodes for the variable capacitance ⑽ at the interface. In addition, in order to reduce the sheet resistance, the P + doped regions U2 and U2 are used. A self-aligned metal silicide layer 10 is further formed on the doped region 114 and the N + doped region 116. As can be seen from the figure, the present invention is compared with the conventional junction variable capacitor. There are no shallow trench insulation areas between the cathodes, so the encapsulation resistance of the variable capacitors at the interface can be reduced, thereby improving the quality factor q. While in operation, the gate electrode 101 and the moving system are connected to- The gate depends on Vg. In this implementation, the gate voltage% can be a positive voltage of I. In the present invention, by applying a positive voltage such as Vcc to the gates 101 and 102, electrons are accumulated in the channels below the gate, Therefore, the resistance can be low, and the quality factor 0 can be improved. By changing the bias between the anode ⑴ and the cathode 可变, the capacitance of the interface variable capacitor 80 can be adjusted. Then, please refer to page Figure 5 to Figure 8, Figures 5 to 8 are shown in cross-section structure 1 as shown in Figure 4 of the preferred embodiment of the present invention variable junction capacitor The main process steps of 80. The method for manufacturing the junction variable capacitor 80 according to the present invention is a cmos compatible process. First, as shown in FIG. 5, a substrate is provided, and an N-type well 100 is formed on the surface. Is isolated by a shallow trench insulation region (not shown). Next, a 1242257 insulation layer (not shown) is formed on the N-type well 100, such as a gate silicon oxide layer. Then, a silicon oxide layer is deposited on the gate silicon oxide layer. Polycrystalline silicon layer (not shown) 'Reusing yellow light and etching processes, the polycrystalline silicon layer and the insulating layer are defined as the gate structures 101 and 102, and the insulating layers are 10 lb and · 102b below them respectively.-Then, as described in Section 6 As shown in the figure, rnldd ion implantation is performed, and the area between the gate structure 101 and 102 is masked with an appropriate mask (NLDD imPlantphoto), and then arsenic ion implantation is performed to the gate structure 10. NLDD doped regions 121 and 122 are formed on one of the sides 1 and 102. · As shown in FIG. 7 ', PLDD ion implantation is performed, and a gate electrode structure 101 and 1 are appropriately masked. The area between 〇2 is opened and then lateral ion implantation is performed for the gate structures 〇1 and 〇 PLDD doped regions 113 are formed in the n-type wells between 2. As shown in FIG. 8, the sidewalls (SPace_la and hidden) are then formed on the sidewalls of the gates 101 and 102. Then, the gates are formed using a suitable mask such as a surface. The area between 〇1 and 102 is masked, and then the & ion cloth ^ is used to form an N + impurity region called ⑽ and ⑽ on one of the gates 101 and 102. Finally, the channel mask and the ion cloth are used again. A P + doped region 112 is formed between the gate structure and the gate electrode. The structure in FIG. 8 continues to be self-matched. The physical process is to form the interface variable capacitor 8G of the present invention shown in FIG. 4. ”12! 242257 In addition, please refer to FIG. 9, which is a schematic cross-sectional view of a junction variable capacitor 800 according to another preferred embodiment of the present invention. As shown in FIG. 9, another preferred embodiment of the present invention connects The area variable capacitor 800 is formed on a P-type well 200. According to another preferred embodiment of the present invention, the area variable capacitor 800 includes an elongated gate electrode 201 that is located across the P-type well 200. The gate electrode 202 and an elongated gate electrode 202 are disposed above the P-well 200 on the gate electrode 201 side. The gate electrode 201 and the gate electrode 202 may It is made of polycrystalline silicon or metal. Gate 201 and gate 202 each have two vertical side walls, and spacers 201a and 202a are formed on them, respectively. Gate 201 and gate 202 and p-type well 200 are gated respectively. The dielectric layers 20ib and 202b are electrically isolated. An N + doped region 212 is formed in the p-type well 200 between the gates 201 and 202, and is used as a junction variable capacitor 800. Anode. The N + doped region 212 may be connected to an N-type lightly doped drain (NLDD) 213, where the n-type lightly doped drain 213 faces the gate 201 and the gate 202 A P + doped region 214 and a P-type lightly doped drain (PLDD) 221 are formed in the P-type well 200 on the opposite side of the gate 201 and the N + doped region 212. It is adjacent to the P + doped region 214 and extends laterally below the side wall 201a of the gate 201. In other embodiments, a p-type lightly doped drain (pldd) 221 extends below the gate 201. Between the gate 202 and N + A p + doped region 216 and a P-type lightly doped drain (NLDD) 222 are formed in the p-type well 200 on the opposite side of the doped region 212. Region 216 extends laterally below sidewall 202a of gate 202, and P-type lightly doped drain (PLDD) 222 extends directly below gate 202. P + doped region 214 and P + doped region 216 are utilized The internal wiring is electrically connected. The Ϊ242257 is used as the cathode of the variable capacitor 800. In addition, in order to reduce the sheet resistance, a self-aligned salicide layer 203 is formed on the N + doped region 212, the P + doped region 214, and the P + doped region 216. In operation, the gates 201 and 202 are connected to a gate voltage vG. In this embodiment, the gate voltage Vg may be v%. 々The above is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention. [Schematic description] Figure 1 is a schematic cross-sectional view of a conventional junction variable capacitor. FIG. 2 is a schematic cross-sectional structure diagram of a conventional metal-oxide semiconductor variable capacitor. FIG. 3 is a schematic top view of a layout of a junction variable capacitor according to a preferred embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of the variable capacitance junction along the tangent line AA in Fig. 3: Figs. 5 to 8 show the cross-sectional structure of the main components of the variable capacitance of the preferred embodiment of the present invention as shown in Fig. 4 Process steps. Figure 9 is a schematic cross-sectional view of another variable capacitor of the present invention. [Description of main component symbols] 10 substrate 12 ion well 14 isolation structure 16 doped region 18 doped region 22 N-type well 24 N + doped region 25 lightly doped drain 26 polycrystalline silicon gate structure 28 gate dielectric layer 80 connection Surface variable capacitor 100 N type well 1242257
101 閘極 101a 侧壁子 101b 閘極介電層 102 閘極 102a 侧壁子 102b 閘極介電層 103 自行對準金屬石夕化物層 112 P+摻雜區 113 PLDD 114 N+摻雜區 116 N+摻雜區 121 NLDD 122 NLDD 200 STI 800 接面可變電容 200 P型井 201 閘極 201a 側壁子 201b 閘極介電層 202 閘極 202a 側壁子 202b 閘極介電層 203 自行對準金屬矽化物層 212 N+摻雜區 213 NLDD 214 P+摻雜區 216 P+摻雜區 221 PLDD 222 PLDD101 Gate 101a Side wall 101b Gate dielectric layer 102 Gate 102a Side wall 102b Gate dielectric layer 103 Self-aligned metal oxide layer 112 P + doped region 113 PLDD 114 N + doped region 116 N + doped Miscellaneous area 121 NLDD 122 NLDD 200 STI 800 Junction variable capacitor 200 P-well 201 Gate 201a Side wall 201b Gate dielectric layer 202 Gate 202a Side wall 202b Gate dielectric layer 203 Self-aligned metal silicide layer 212 N + doped region 213 NLDD 214 P + doped region 216 P + doped region 221 PLDD 222 PLDD