CN104051529B - RF switches on high-impedance substrate - Google Patents

RF switches on high-impedance substrate Download PDF

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Publication number
CN104051529B
CN104051529B CN201310303834.5A CN201310303834A CN104051529B CN 104051529 B CN104051529 B CN 104051529B CN 201310303834 A CN201310303834 A CN 201310303834A CN 104051529 B CN104051529 B CN 104051529B
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semiconductor substrate
well region
gate
drain
source
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CN104051529A (en
Inventor
陈家忠
黄崎峰
傅淑芳
叶子祯
周淳朴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US13/866,886 external-priority patent/US9178058B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a kind of device, including the deep-well region in the Semiconductor substrate with the first conduction type, and the Semiconductor substrate, wherein deep-well region has second conduction type opposite with first conduction type.The device also includes being located at the well region with the first conduction type above deep-well region.Semiconductor substrate has the top being located above well region and the bottom below deep-well region, wherein the top and the bottom have the first conduction type and with high impedance.Gate-dielectric is located on Semiconductor substrate.Gate electrode is located above gate-dielectric.Source area and drain region are extended in the top of Semiconductor substrate.Source area, drain region, gate-dielectric and gate electrode formation radio frequency（RF）Switch.The invention also discloses the switches of the RF on high-impedance substrate.

Description

RF switches on high-impedance substrate
This application claims the priority of following U.S. Provisional Patent Application:Submit on March 13rd, 2013, entitled " RF Switch on High Resistive Subsuate ", Application No. N0.61/780,002, this application is herein by quoting simultaneously Enter herein.
Technical field
The present invention relates to semiconductor applications, switched more particularly, to the RF on a kind of high-impedance substrate.
Background technology
In the application of integrated circuit, increasing function is integrated in the product.For example, it may be desirable to will such as 3G Video component, WiFi elements, the different function element of bluetooth element and audio/video element are integrated to form should With.The known application of these devices is Mobile solution, for example, form the moving device of such as mobile phone.
High-frequency circuit including radio frequency (RF) passive device is widely used in Mobile solution.RF passive devices may include electricity Container, inductor, transformer etc..Due to high frequency, a variety of design problems are frequently observed.It is that designer faces common problem encountered is that in height The loss of signal in substrate under frequency circuit, the loss of signal part is the parasitic capacitance between high-frequency circuit and lower substrate It is caused.Generally, with the increase of signal frequency, the loss of signal becomes more serious.This greatly limits high-frequency circuit Design.
Now, there are several solutions for being used to reduce substrate losses.For example, silicon-on-insulator (SOI) substrate is not by People with colony is using to form high-frequency circuit.Although using this method substrate losses can be reduced, SOI substrate generally compared with It is expensive.In addition, there is third harmonic, and circuit (such as complementary metal oxide being therefore formed thereon in SOI substrate Semiconductor (CMOS) device) it is difficult together with RF passive device integrations.
Further, since the high frequency for the signal that high-frequency circuit is carried, the control circuit of operation RF passive devices needs processing Quick change in signal, and the control circuit needs with the sufficiently small response time to adapt to the change in high-frequency signal Change.
The content of the invention
In order to solve the problems of in the prior art, according to an aspect of the invention, there is provided a kind of device, bag Include:
Semiconductor substrate with the first conduction type;
Deep-well region in the Semiconductor substrate, wherein, the deep-well region has and the first conduction type phase The second anti-conduction type;
The well region with first conduction type above the deep-well region, the Semiconductor substrate includes:
Top above the well region;And
Bottom below the deep-well region, wherein, the top and the bottom have first conduction type And with high impedance;
Positioned at the gate-dielectric of the over top of the Semiconductor substrate;
Gate electrode above the gate-dielectric;And
The source area extended in the top of the Semiconductor substrate and drain region, wherein, the source area and drain region Separated with the well region at the top of the Semiconductor substrate, and the source area, the drain region, grid electricity Jie Matter and gate electrode formation radio frequency (RF) switch, radio frequency (RF) switchgear distribution is into RF frequency operated within range.
In an alternative embodiment, the device also includes:It is electrically connected positioned above RF switches and with RF switches The RF passive devices connect.
In an alternative embodiment, the high impedance of the semiconductor is greater than about 5000ohm-cm.
In an alternative embodiment, the high impedance in about 5000ohm-cm between about 20000ohm-cm.
In an alternative embodiment, the source area and the drain region have the depth less than about 50nm.
In an alternative embodiment, the device also includes:Gate spacer, on the side wall of the gate electrode;Dielectric Layer, including a top in the source area and the drain region and with the institute in the source area and the drain region State the part of a contact;And, source/drain silicide, the edge being aligned with the edge with the dielectric layer, wherein, The dielectric layer is located between the gate spacer and the source/drain silicide.
In an alternative embodiment, also source/drain is lightly doped including what is extended below the gate-dielectric in the device Area, wherein lightly-doped source pole/drain region has the depth less than about 50nm.
According to another aspect of the present invention, a kind of device is additionally provided, including:
Semiconductor substrate;
Deep n well region in the Semiconductor substrate;
The p-type well region contacted above the deep n well region and with the deep n well region, wherein the semiconductor is served as a contrast Bottom includes:
Top above the p-type well region;And
Bottom below the deep n well region, wherein, the top and the bottom are p-type, and the bottom With greater than about 5000ohm-cm impedance;
Radio frequency (RF) is switched, including:
Positioned at the gate-dielectric of the over top of the Semiconductor substrate;
Gate electrode above the gate-dielectric;And
The source area extended in the top of the Semiconductor substrate and drain region, wherein the source area and described Drain region is separated with the p-type well region by the top of the Semiconductor substrate;And,
RF passive devices, switch top positioned at the RF and are electrically connected with RF switches.
In an alternative embodiment, the RF passive devices are electrically connected to the gate electrode.
In an alternative embodiment, described partly led what the source area and the drain region and the p-type well region were separated The top of body substrate has about 5000ohm-cm to the impedance between about 20000ohm-cm.
In an alternative embodiment, the device also includes:Gate spacer, on the side wall of the gate electrode;Dielectric Layer, including a top in the source area and the drain region and with the institute in the source area and the drain region State the part of a contact;And, source/drain silicide, the edge being aligned with the edge with the dielectric layer.
In an alternative embodiment, the RF passive devices be selected from substantially by capacitor, inductor, transformer, transmission line, The group that waveguide and combinations thereof are constituted.
In an alternative embodiment, the impedance of the bottom of the substrate is in about 5000ohm-cm to about 20000ohm-cm Between.
In an alternative embodiment, the device also includes extending to the shallow trench isolation in the Semiconductor substrate（STI） Area, wherein the STI region has the first depth, and the source area and the drain region have and are less than than first depth About 5% the second depth.
According to another aspect of the invention, a kind of method is yet forms both, including：
Implement to inject Semiconductor substrate to form the first injection of deep-well region, wherein, the Semiconductor substrate tool Have the first conduction type and with greater than about 5000ohm-cm impedance, and in described first injects, injection with it is described The impurity of the second opposite conduction type of first conduction type；
Implement the second injection injected to the Semiconductor substrate, the well region formation with the first conduction type is in institute State above deep-well region, and after the described first injection and the described second injection, the Semiconductor substrate includes：
Top above the well region；And
Bottom below the deep-well region, wherein, the top and the bottom are injected and described described first Substantially it is not implanted in second injection；
In the over top formation gate-dielectric of the Semiconductor substrate；
Gate electrode is formed above the gate-dielectric；And
Implement to inject to form the 3rd injection of source area and drain region the top of the Semiconductor substrate, Wherein described source area and the drain region are separated with the well region by the remaining top of the Semiconductor substrate, and described Source area, the drain region, the gate-dielectric and gate electrode formation are configured in radio frequency（RF）In frequency range The RF switches of work.
In an alternative embodiment, forming the step of RF is switched does not include the injection of any channel doping.
In an alternative embodiment, the 3rd injection is carried out using about 2KeV to the energy between about 10KeV.
In an alternative embodiment, methods described also includes：Gate spacer is formed on the side wall of the gate electrode；Formed Dielectric layer, the dielectric layer include be located at the source area and the drain region in a top and with the source area and institute State the part of one contact in drain region；And, formed the dielectric layer the step of after, formed have with it is described The source/drain silicide of the edge alignment edges of dielectric layer.
In an alternative embodiment, methods described, which also includes being formed, is located at RF switches top and is electrically connected with RF switches The RF passive devices connect.
In an alternative embodiment, methods described is also including the use of about 2KeV to the Implantation Energy pair between about 10KeV The top of the Semiconductor substrate is injected is lightly doped source/drain regions to be formed.
Brief description of the drawings
For the more complete understanding embodiment of the present invention and its advantage, now ginseng is used as with reference to the following description that accompanying drawing is carried out Examine, wherein
Fig. 1 to Fig. 8 is that the cross section in the interstage switched according to the manufacture radio frequency (RF) of some exemplary embodiments shows Figure.
Embodiment
Below, the manufacture of various embodiments of the present invention is discussed in detail and uses.It should be appreciated, however, that the invention provides permitted The applicable concept that can be realized more in various specific environments.The specific embodiment discussed illustrate only manufacture and make With the concrete mode of the present invention, rather than limitation the scope of the present invention.
The radio frequency (RF) formed by metal-oxide semiconductor (MOS) (MOS) transistor is provided according to multiple exemplary embodiments Switch and forming method thereof.Show the interstage to form RF switches.The deformation of embodiment is discussed.In multiple diagrams in the whole text and In exemplary embodiment, identical reference numeral is used to refer to identical element.
With reference to Fig. 1, there is provided substrate 20.Substrate 20 may include the semi-conducting material of such as silicon, although such as silicon can be used Other semi-conducting materials of germanium.Substrate 20 can lightly doped p-type impurity, such as boron, indium or combinations thereof.Substrate 20 has height Impedance, the impedance is greater than about 3000ohm-cm (volume resistance) or greater than about 5000ohm-cm.The impedance also can be about 3000ohm-cm, and can be in about 5000ohm-cm between about 20,000ohm-cm between about 250,000ohm-cm. The impedance of substrate 20 is significantly more than the impedance of typical silicon substrate, and the impedance value of the typical silicon substrate is close to about 10ohm- cm.Therefore, hereinafter, substrate 20 is referred to as high-impedance substrate.According to some embodiments, corresponding p-type doping concentration can be with In about 5x106/cm3To about 5x1010/cm3Between.The p-type doping concentration of substrate 20 is also markedly inferior to the p-type of typical silicon substrate Doping concentration, typical silicon substrate can have in about lx1012/cm3To about lxl015/cm3Between p-type doping concentration.
With reference also to Fig. 1, carry out n-type injection p-type impurity is injected into Semiconductor substrate 20.Arrow 21 shows this Injection.Therefore, deep n-type trap is formed in the by-level position of substrate 20（DNW) 22, and substrate 20 is including being located on DNW22 Side unimplanted substrate portions 20A, and the substrate 20 below DNW22 unimplanted part.P-type impurity may be selected from Phosphorus, arsenic, antimony or combinations thereof.Implantation Energy can be in about 1000KeV between about 2500KeV.The dosage of p-type impurity Can be in about lxl013/cm2To about 1xl014/cm2Between.The DNW22 finally obtained doping concentration can be in about lx1013/ cm3To about lx1014/cm3。
Extended to as shown in figure 1, forming isolated area 24 with the top surface from Semiconductor substrate 20 in Semiconductor substrate 20.One In a little embodiments, isolated area 24 is that shallow trench isolates (STl) area.In certain embodiments, the depth of STI region 24 can be aboutTo aboutBetween.In an alternative embodiment, isolated area 24 is formed by the selective oxidation thing of substrate 20 Zoneofoxidation.In certain embodiments, isolated area 24 may include Si oxide.A part for substrate 20 is defined to use by isolated area 24 In the active area for forming metal-oxide semiconductor (MOS) (CMOS) transistor.
With reference to Fig. 2, p-type injection is carried out so that n-type impurity is injected into Semiconductor substrate 20, and therefore form p-type trap Area 26.Arrow 25 shows the injection.In certain embodiments, p-type trap 26 is on DNW22, and can be in contact with DNW22.p The top surface of type trap 26 is less than the top surface of substrate 20.Therefore, the part 20A positioned at the substrate 20 of the top of p-well region 26 keeps unimplanted p Type impurity.It should be understood that in injection to be formed in DNW22 and p-type trap 26, implanted dopant can leave some ions in substrate portions In 20A.However, it is not intended to substrate portions 20A is injected, therefore it is a small amount of to be retained in ion therein.Pass through injection 25 introduced n-type impurities may be selected from indium, boron or combinations thereof.In certain embodiments, indium is injected, and Implantation Energy is About 100KeV is between about 130KeV.The dosage of n-type impurity can be in about lxl012/cm2To about lxl014/cm2Between. The doping concentration of the p-type trap 26 finally obtained may be about lxl011/cm3To about lxl014/cm3Between.
According to embodiments herein, formed STI region 24, DNW22 and p-type trap 26 order can with exemplary embodiment Difference, and different orders can be changed into.For example, DNW22 and p-type trap 26 can be formed before the formation of STI region 24. Also, in certain embodiments, DNW22 can be formed after the formation of p-type trap 26.
Fig. 3 shows the formation of gate stack, and gate stack includes gate-dielectric 30 and gate electrode 32.Grid electricity Medium 30 can be by selected from Si oxide, silicon nitride, silicon carbide, silicon nitrogen oxides and combinations thereof and their sandwich construction Material formed.Such as hafnium base oxide, aluminium base oxide, lanthanum base oxide and the high-g value of their combinations can also be wrapped It is contained in gate-dielectric 30.Gate electrode 32 can be formed by DOPOS doped polycrystalline silicon.Alternatively, metal, metal nitride, metal silication Thing and/or other conductive materials can be used for forming gate electrode 32.The formation of gate-dielectric 30 and gate electrode 32 includes being formed Thick gate dielectric and the formation thickness gate electrode layer on equal thick gate dielectric, then pattern thickness gate dielectric and equal Thick gate electrode layer.According to some embodiments, the grid length Lg of gate electrode 32 is less than about 0.3 μm.
Embodiments in accordance with the present invention, without channel doping.It should be understood that in traditional MOS transistor is formed, can enter Row channel doping is to increase the doping concentration of the raceway groove of corresponding MOS transistor.Forming the conventional channel doping of nmos pass transistor In, by n-type impurity being injected into the raceway groove of nmos pass transistor can carry out p-type channel doping.For forming PMOS crystal Pipe, can carry out n-type channel doping by being injected into p-type impurity in the raceway groove of PMOS transistor.In embodiments of the present invention, Injected without channel doping.This causes the channel dopant concentration of the raceway groove 29 covered by gate electrode 32 very low.According to one A little embodiments, channel region 29, which has, is less than about 1013/cm3P-type doping concentration.Therefore, the threshold value electricity of resulting transistor Pressure is very low.Thus, the MOS transistor formed according to embodiment has very fast switch time, and is adapted to be used as RF Switch.
With reference to Fig. 4, enter line tilt injection to form lightly doped drain/source electrode (LDD) area 36, wherein it is from grid to tilt injection The opposite side of electrode 32 is inclined.Implanted dopant may include such as phosphorus, arsenic or the p-type impurity of combinations thereof.Tilting injection can Carried out with inclined angle alpha, for example, less than about 15 degree of the angle.Due to tilting injection, therefore LDD region 36 is in gate-dielectric 30 and grid The lower section of electrode 32 extends, and the part of each LDD region 36 is overlapping with gate-dielectric 30 and gate electrode 32.N for injecting such as arsenic The energy of type impurity may be about 2KeV between about l0KeV.Therefore, LDD region 36 is very shallow, and the depth D1 of LDD region 36 can Less than about 50nm.
With reference to Fig. 5, formed gate spacer 38 and heavy-doped source polar region and drain region 40 (hereinafter referred to as source electrode/ Drain region).According to some embodiments, gate spacer 38 is initially formed, is then injected to form source/drain regions 40. Therefore, source/drain regions 40 have the internal edge being aligned with the external margin of gate spacer 38.In an alternative embodiment, Injected to form source/drain regions 40, be subsequently formed gate spacer 38.Therefore, source/drain regions 40 have and grid The internal edge of the edge alignment of electrode 32.During the formation of source/drain regions 40, the n-type of injection arsenic, phosphorus etc. is miscellaneous Matter.In the embodiment of injection arsenic, Implantation Energy may be about 2KeV between about 10KeV.Therefore, source/drain regions 40 Also it is very shallow, and the depth D2 of source/drain regions 40 is smaller than about 50nm.In certain embodiments, the depth of LDD region 36 Dl and the depth D2 of source/drain regions 40 are substantially mutually the same.In a particular embodiment, depth Dl and D2 difference is smaller than about 5%, and may be about between 3% to about 5%.
Separated between the top surface of the bottom and p-type trap 26 of LDD region 36 and source/drain regions 40 by substrate portions 20A.Cause This, LDD region 36 and source/drain regions 40 and substrate portions 20A formation are tied, and it has low-down p-type doping concentration.
Fig. 6 shows the formation of dielectric layer 42, dielectric layer 42 be formed as overlapping with source/drain regions 40 and contact source electrode/ Drain region 40.According to some embodiments, each dielectric layer 42 is in contact with one in gate spacer 38, and away from corresponding Gate spacer 38 extends.The material of dielectric layer 42 may include oxide, nitride, carbide, nitrogen oxides and/or similar Thing, and the chemical vapors such as plasma enhanced chemical gas deposition (PECVD), ald (ALD) can be used to sink Product (CVD) method is formed.The thickness Tl of dielectric layer 42 may be about 10nm between about 50nm.In certain embodiments, The top surface of dielectric layer 42 can be less than the top surface of gate electrode 32.The formation of dielectric layer 42 may include to be formed thick dielectric layer and (not show Go out), patterned in equal thick dielectric layer formation photoresist and to photoresist and then etch equal thickness dielectric layer to form Jie Electric layer 42.Therefore, unlike the gate spacer 38 with sloped top face, dielectric layer 42 can have substantially flat surface.
Then, with reference to Fig. 7, gate silicide area 44 and source/drain suicide areas 46 are formed.The He of gate silicide area 44 The formation of source/drain suicide areas 46 may include to form metal level (not shown), metal level on substrate shown in figure 6 It may include nickel, cobalt etc..Then annealed, during annealing, exposed silicon is reacted to form silicide area with metal level 44 and 46.The metal layer part not reacted with metal level is removed, so as to leave gate silicide area 44 and source/drain Silicide area 46.Due to foring dielectric layer 42 so that source/drain suicide areas 46 increases further from gate electrode 32, and therefore The breakdown voltage between such as gate electrode 32 and drain region 40 is added.Thus form MOS transistor 100.MOS transistor 100 It can be used as RF switches.
Fig. 8 shows back-end process (BEOL) technique, is inserted which has been formed gate contact connector 48, source/drain contact Plug 50 and interlayer dielectric (ILD) 52.Gate contact connector 48 and source/drain contact plunger 50 are respectively electrically connected to grid electricity Pole 32 and source/drain regions 40.Then, interconnection structure 54 is formed.Interconnection structure 54 may include multiple dielectric layers 56.In some realities Apply in example, dielectric layer 56 is the low k dielectric less than about 3.5 with such as dielectric constant (k values).The k values of low k dielectric 56 3.0 can be below about.Metal wire 58 and through hole 60 are formed in dielectric layer 56.Some metal wires 58 and through hole 60 are electrically connected to MOS Transistor 100.Metal wire in same layer is collectively known as metal level.
Also as shown in figure 8, forming RF passive devices 62 in BEOL techniques.RF passive devices 62 can be capacitor, inductance Device, transformer, transmission line, waveguide etc., their characteristic (such as frequency response and quality factor) are adapted to operate in RF frequency model Enclose in (about 500MHz is higher).Fig. 8 shows the cross sectional view of a part for RF passive devices 62.In some implementations In example, RF passive devices 62 are extended in one or more metal levels of interconnection structure 54, wherein the thickness T2 of each metal level Can be to be greater than about 1 μm, and can be between about 1 μm to about 5 μm.Passive device 62 also may extend to aluminous layer (such as Aluminum bronze layer) in 64.By the stacking to multiple metal levels and aluminous layer, the thickness of RF passive devices 62 is sufficiently large, and therefore RF Passive device 62 can work in high frequency.
Although embodiment previously discussed provides the method for forming the RF switches including nmos device, but in this implementation The method taught provided in example can be readily used to form the method for the RF switches including PMOS device, along with corresponding substrate Conduction type, well region, LDD region and/or the reversion of source/drain regions.
Embodiments in accordance with the present invention, MOS transistor 100 is switched as RF, the letter that can be provided by RF passive devices 62 Number operate.Due to switching 100 based on the formation of substrate 20 RF with high impedance, therefore the insertion loss of RF switches is very low. Simulation result shows that the insertion loss of the RF formed according to embodiments of the present invention switches is about 0.34dB, and this is substantially less than rule Lattice requirement (is less than ldB).In addition, the switch time of the RF switches formed according to embodiments of the present invention was about 60 nanoseconds, this Substantially less than specification requirement (about 500 nanoseconds）.Therefore, the RF switches formed according to embodiments of the present invention can significantly expire Sufficient specification requirement.
According to some embodiments, device includes the Semiconductor substrate with the first conduction type, and in Semiconductor substrate Deep-well region, wherein the deep-well region have second conduction type opposite with the first conduction type.The device is additionally included in deep trap The well region with the first conduction type above area.Semiconductor substrate is with the top being covered in above the well region and by deep trap The bottom of area's covering, the wherein top and bottom have the first conduction type and with high impedance.Gate-dielectric is in semiconductor The over top of substrate.Gate electrode is on gate-dielectric.Source area and drain region are extended in the top of Semiconductor substrate, its The top of middle Semiconductor substrate separates the source area and drain region with the well region.Source area, drain region, gate-dielectric And gate electrode formation is switched in the RF of RF frequency operated within range.
According to other embodiment, device includes Semiconductor substrate, deep n well region in the semiconductor substrate, and in deep n The p-type trap being in contact on type well region and with deep n well region.Semiconductor substrate includes being located at the top and position above p-type trap Bottom below deep n well region.Top and bottom are p-type.Bottom has greater than about 5000ohm-cm impedance.Device is also wrapped Include RF switches, RF switches include the gate-dielectric of over top positioned at Semiconductor substrate, the gate electrode on gate-dielectric, And the source area extended in the top of Semiconductor substrate and drain region.Source area and drain region are with p-type well region by semiconductor Separated at the top of substrate.RF passive devices are located at RF and switch top and electrically connected with RF switches.
According to another other embodiment, a kind of method includes implementing that Semiconductor substrate is injected to form deep-well region First injection, wherein Semiconductor substrate have the first conduction type, and with greater than about 5000ohm-cm impedance.First In injection, injection has second conductive type impurity opposite with the first conduction type.Implementation is injected to Semiconductor substrate To form the second injection of well region, wherein the formation of the well region with the first conduction type is on deep-well region.First injection and After second injection, Semiconductor substrate includes being located at the top above well region and the bottom below deep-well region, wherein pushing up Portion and bottom are substantially not implanted in the first injection and the second injection.This method is additionally included on the top of Semiconductor substrate It is square that gate electrode is formed on gate-dielectric into gate-dielectric, and implement to inject the top of Semiconductor substrate To form the 3rd injection of source area and drain region.Source area and drain region and well region by the remaining top of Semiconductor substrate every Open.Source area, drain region, gate-dielectric and gate electrode formation are configured to the RF switches in RF frequency operated within range.
Although the invention has been described in detail and its advantage, it is to be understood that can be will without departing substantially from appended right In the case of the spirit and scope of the present invention for asking restriction, a variety of changes are made, replaces and changes.Moreover, the model of the application Enclose and be not limited in technique described in this specification, machine, manufacture, material component, device, the particular implementation of method and steps Example.As it will be recognized by one of ordinary skill in the art that by the present invention, it is existing or Future Development be used to performing with according to this Invent the essentially identical function of the corresponding embodiment that is used or obtain the technique of essentially identical result, machine, manufacture, material Material component, device, method or step can be used according to the present invention.Therefore, appended claims should by such technique, In the range of machine, manufacture, material component, device, method or step are included in.In addition, every claim is constituted individually in fact Apply example, and multiple claims and embodiment combination within the scope of the invention.

Claims (20)

1. a kind of semiconductor devices, including：
Semiconductor substrate with the first conduction type；
Deep-well region in the Semiconductor substrate, the deep-well region has opposite with first conduction type second to lead Electric type；
The well region with first conduction type above the deep-well region, wherein, the Semiconductor substrate includes：
Top above the well region；And
Bottom below the deep-well region, wherein, the top and the bottom have first conduction type and With high impedance；
Positioned at the gate-dielectric of the over top of the Semiconductor substrate；
Gate electrode above the gate-dielectric；
Gate spacer on the side wall of the gate electrode；And
The source area extended in the top of the Semiconductor substrate and drain region, wherein, the source area and drain region and institute Well region is stated to be separated at the top of the Semiconductor substrate, and the source area, the drain region, the gate-dielectric with And the gate electrode formation radio frequency switch, the radio frequency switchgear distribution is into RF frequency operated within range；
Dielectric layer, including a top in the source area and the drain region and with the source area and the drain electrode The part of one contact in area, wherein, the dielectric layer is contacted with the gate spacer and away from the grid Distance piece extends.
2. device according to claim 1, in addition to：
The RF passive devices electrically connected are switched positioned above RF switches and with the RF.
3. device according to claim 1, wherein, the high impedance of the semiconductor is more than 5000ohm-cm.
4. device according to claim 1, wherein, the high impedance is in 5000ohm-cm between 20000ohm-cm.
5. device according to claim 1, wherein, the source area and the drain region have the depth for being less than 50nm.
6. device according to claim 1, in addition to：
Source/drain silicide, the edge being aligned with the edge with the dielectric layer, wherein, the dielectric layer is located at described Between gate spacer and the source/drain silicide.
7. extension is lightly doped source/drain below device according to claim 1, in addition to the gate-dielectric Area, wherein lightly-doped source pole/drain region has the depth less than 50nm.
8. a kind of semiconductor devices, including：
Semiconductor substrate；
Deep n well region in the Semiconductor substrate；
The p-type well region contacted above the deep n well region and with the deep n well region, wherein the semiconductor substrate Include：
Top above the p-type well region；And
Bottom below the deep n well region, wherein, the top and the bottom are p-type, and the bottom has Impedance more than 5000ohm-cm；
Radio frequency is switched, including：
Positioned at the gate-dielectric of the over top of the Semiconductor substrate；
Gate electrode above the gate-dielectric；
Gate spacer on the side wall of the gate electrode；And
The source area extended in the top of the Semiconductor substrate and drain region, wherein the source area and the drain electrode Area is separated with the p-type well region by the top of the Semiconductor substrate；
Dielectric layer, including a top in the source area and the drain region and with the source area and the drain electrode The part of one contact in area, wherein, the dielectric layer is contacted with the gate spacer and away from the grid Distance piece extends；And,
RF passive devices, switch top positioned at the RF and are electrically connected with RF switches.
9. device according to claim 8, wherein, the RF passive devices are electrically connected to the gate electrode.
10. device according to claim 8, wherein, the source area and the drain region are separated with the p-type well region The top for the Semiconductor substrate opened has 5000ohm-cm to the impedance between 20000ohm-cm.
11. device according to claim 8, in addition to：
Source/drain silicide, the edge being aligned with the edge with the dielectric layer.
12. device according to claim 8, wherein, the RF passive devices be selected from by capacitor, inductor, transformer, The group that transmission line, waveguide and combinations thereof are constituted.
13. device according to claim 8, wherein, the impedance of the bottom of the substrate in 5000ohm-cm extremely Between 20000ohm-cm.
14. device according to claim 8, in addition to the shallow trench isolation STI area extended in the Semiconductor substrate, Wherein described STI region has the first depth, and the source area and the drain region have than first depth small 5% Second depth.
15. a kind of method for forming semiconductor devices, including：
Implement to inject Semiconductor substrate to form the first injection of deep-well region, wherein, the Semiconductor substrate is with the One conduction type and with more than 5000ohm-cm impedance, and described first inject in, injection led with described first The impurity of the second opposite conduction type of electric type；
Implement the second injection injected to the Semiconductor substrate, the well region formation with the first conduction type is in the depth Above well region, and after the described first injection and the described second injection, the Semiconductor substrate includes：
Top above the well region；And
Bottom below the deep-well region, wherein, the top and the bottom are in the described first injection and described second Substantially it is not implanted in injection；
In the over top formation gate-dielectric of the Semiconductor substrate；
Gate electrode is formed above the gate-dielectric；
Gate spacer is formed on the side wall of the gate electrode；
Implement to inject to form the 3rd injection of source area and drain region the top of the Semiconductor substrate, wherein The source area and the drain region are separated with the well region by the remaining top of the Semiconductor substrate, and the source electrode Area, the drain region, the gate-dielectric and gate electrode formation are configured in radio frequency frequency ranges of operation RF is switched；And
Formed dielectric layer, the dielectric layer include be located at the source area and the drain region in a top and with the source The part of one contact in polar region and the drain region, wherein, the dielectric layer is contacted with the gate spacer And away from gate spacer extension.
16. method according to claim 15, wherein, forming the step of RF is switched does not include any channel doping note Enter.
17. method according to claim 15, wherein, carry out the 3rd note using 2KeV to the energy between 10KeV Enter.
18. method according to claim 15, in addition to：
After the step of forming the dielectric layer, the source/drain with the edge being aligned with the edge of the dielectric layer is formed Pole silicide.
19. method according to claim 15, in addition to formed positioned at RF switches top and switch electricity with the RF The RF passive devices of connection.
20. method according to claim 15, also partly leads including the use of 2KeV to the Implantation Energy between 10KeV to described The top of body substrate is injected is lightly doped source/drain regions to be formed.
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