CN105405890A - Semiconductor device comprising charged body spacer and manufacturing method thereof - Google Patents
Semiconductor device comprising charged body spacer and manufacturing method thereof Download PDFInfo
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- CN105405890A CN105405890A CN201510746438.9A CN201510746438A CN105405890A CN 105405890 A CN105405890 A CN 105405890A CN 201510746438 A CN201510746438 A CN 201510746438A CN 105405890 A CN105405890 A CN 105405890A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 158
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 title abstract 5
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 19
- 239000000203 mixture Substances 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 124
- 239000004020 conductor Substances 0.000 description 17
- 238000005530 etching Methods 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003292 diminished effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- -1 SiCOH Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a semiconductor device comprising a charged body spacer and a manufacturing method thereof. The semiconductor device can be an n-type device or a p-type device which can respectively comprises a patterned first semiconductor layer and a second semiconductor layer which are formed on a substrate in turn, wherein the first semiconductor layer and the second semiconductor layer are patterned into a fin structure, and the first semiconductor layer is transversely recessed relative to the second semiconductor layer; a body spacer which is formed in the transverse recess and comprises dielectric material; an insolation layer which is formed on the substrate, wherein the top surface of the isolation layer is arranged between the top surface and the bottom surface of the first semiconductor layer, and the part above the isolation layer of the fin structure acts as the fins of the semiconductor device ; and gate stacks which are formed on the isolation layer and intersected with the fins. As for the n-type device, the body spacer can carry net negative charges so that the first semiconductor layer is enabled to present p-type; and as for the p-type device, the body spacer can carry net positive charges so that the first semiconductor layer is enabled to present n-type.
Description
Technical field
The disclosure relates to semiconductor applications, more specifically, relates to a kind of semiconductor device and the manufacture method thereof that comprise electrically charged side wall.
Background technology
Along with the size of planar-type semiconductor device is more and more less, short-channel effect is further obvious.For this reason, solid type semiconductor device is proposed as FinFET (fin formula field effect transistor).Generally speaking, FinFET is included in fin and the grid crossing with fin that substrate is vertically formed.Therefore, channel region is formed in fin, and its width determines primarily of the height of fin.But in integrated circuit fabrication process, the height being difficult to control the fin that wafer is formed is identical, thus causes the inconsistency of device performance on wafer.
Particularly, in body FinFET (that is, being formed at the FinFET in body Semiconductor substrate), may there is the leakage via fin lower substrate portion between source-drain area, this also can be called break-through (punch-through).At present, be difficult to form high-quality break-through trapping layer.
Summary of the invention
Object of the present disclosure is to provide a kind of semiconductor device and the manufacture method thereof with novel break-through trapping layer structure at least in part.
According to an aspect of the present disclosure, provide a kind of N-type semiconductor device, comprise: the first semiconductor layer of the composition formed successively on substrate and the second semiconductor layer, wherein, first semiconductor layer and the second semiconductor layer are patterned to fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer; The side wall formed in described transverse direction is recessed into, side wall comprises dielectric substance; The separator that substrate is formed, the end face of described separator is between the end face and bottom surface of the first semiconductor layer, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And the grid crossing with fin formed on separator are stacking, wherein, side wall, with net negative charge, makes the first semiconductor layer present p-type.
According to another aspect of the present disclosure, provide a kind of P-type semiconductor device, comprise: the first semiconductor layer of the composition formed successively on substrate and the second semiconductor layer, wherein, first semiconductor layer and the second semiconductor layer are patterned to fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer; The side wall formed in described transverse direction is recessed into, side wall comprises dielectric substance; The separator that substrate is formed, the end face of described separator is between the end face and bottom surface of the first semiconductor layer, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And the grid crossing with fin formed on separator are stacking, wherein, side wall, with clean positive charge, makes the first semiconductor layer present N-shaped.
According to another aspect of the present disclosure, provide a kind of method manufacturing N-type semiconductor device, comprising: on substrate, form the first semiconductor layer and the second semiconductor layer successively; Composition is carried out, to form fin structure to the second semiconductor layer, the first semiconductor layer; The first semiconductor layer in selective etch fin structure, makes it laterally recessed; The dielectric of middle filling tape net negative charge is recessed into, with organizator side wall in described transverse direction; Substrate forms separator, and described separator exposes a part for described side wall, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And it is stacking to form the grid crossing with fin on separator.
According to another aspect of the present disclosure, provide a kind of method manufacturing P-type semiconductor device, comprising: on substrate, form the first semiconductor layer and the second semiconductor layer successively; Composition is carried out, to form fin structure to the second semiconductor layer, the first semiconductor layer; The first semiconductor layer in selective etch fin structure, makes it laterally recessed; The dielectric of the clean positive charge of middle filling tape is recessed into, with organizator side wall in described transverse direction; Substrate forms separator, and described separator exposes a part for described side wall, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And it is stacking to form the grid crossing with fin on separator.
According to embodiment of the present disclosure, fin structure comprises the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is recessed relative to the second semiconductor layer.In this transverse direction of the first semiconductor layer is recessed, form charged side wall.Particularly, for N-shaped device, side wall with negative electrical charge, thus introduces hole in the first semiconductor layer, makes the first semiconductor layer present p-type; For p-type device, side wall with positive charge, thus introduces electronics in the first semiconductor layer, makes the first semiconductor layer present N-shaped.Therefore, the first semiconductor layer can serve as the break-through trapping layer of this semiconductor device well.Compared with the conventional break-through trapping layer formed by the mode such as ion implantation or thermal diffusion, more precipitous break-through trapping layer electronics or hole distribution can be realized in the short transverse of fin, and therefore reduce Random Dopant Fluctuation.
Accompanying drawing explanation
By referring to the description of accompanying drawing to disclosure embodiment, above-mentioned and other objects of the present disclosure, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-10 shows the schematic diagram of the manufacture semiconductor device flow process according to disclosure embodiment.
Embodiment
Below, with reference to the accompanying drawings embodiment of the present disclosure is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the present disclosure.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present disclosure.
Various structural representations according to disclosure embodiment shown in the drawings.These figure not draw in proportion, wherein in order to the object of clear expression, are exaggerated some details, and may eliminate some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, in reality may due to manufacturing tolerance or technical limitations deviation to some extent, and those skilled in the art can design the regions/layers with difformity, size, relative position in addition needed for actual.
In context of the present disclosure, when one deck/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can there is intermediate layer/element between them.In addition, if one to be positioned at towards middle one deck/element another layer/element " on ", so when turn towards time, this layer/element can be positioned at this another layer/element D score.
According to embodiment of the present disclosure, on substrate, such as at least one semiconductor layer can be formed by extension.Like this, when such as carrying out composition fin structure by etching, for forming mutually level fin structure, the etching degree of depth entered in substrate can reduce (can be even zero relative to routine techniques, in this case, fin structure is formed completely by least one semiconductor layer described), thus the consistency controlling etching depth can be more prone to.In addition, the consistency of thickness of epitaxial loayer can relatively easily control, result, can improve the consistency of the height of the final fin structure formed.
Basic disclosed preferred embodiment, at least one semiconductor layer described comprises two or more semiconductor layer.In these semiconductor layers, adjacent semiconductor layer relative to each other can have Etch selectivity, thus can the every semi-conductor layer of selective etch.After formation fin structure, can selective etch certain one deck (or multilayer) wherein, make it laterally narrow (being recessed into).Middle filling dielectric can be recessed into, with organizator side wall (bodyspacer) in this transverse direction.In addition, so form separator, make separator expose a part for side wall.Thus side wall is positioned at the final bottom (the initial fin structure formed is isolated part that layer surrounds and no longer serves as real fin for forming raceway groove) forming fin.
Like this, in the final bottom forming fin, due to side wall, the dielectric layer between the grid formed subsequently and fin is thicker, thus the parasitic capacitance formed is relatively little.
According to embodiment of the present disclosure, side wall can be electrically charged.Particularly, for N-shaped device, side wall with negative electrical charge, thus introduces hole in the first semiconductor layer, makes the first semiconductor layer present p-type; For p-type device, side wall with positive charge, thus introduces electronics in the first semiconductor layer, makes the first semiconductor layer present N-shaped.Therefore, the first semiconductor layer can serve as break-through trapping layer.
The disclosure can present in a variety of manners, below will describe some of them example.
As shown in Figure 1, substrate 1002 is provided.This substrate 1002 can be various forms of substrate, such as but not limited to bulk semiconductor material substrate as body Si substrate, semiconductor-on-insulator (SOI) substrate, SiGe substrate etc.In the following description, for convenience of description, be described for body Si substrate.
In substrate 1002, N-shaped trap or p-type trap 1002-1 can be formed, for forming p-type device or N-shaped device respectively thereon subsequently.Such as, N-shaped trap can be formed by such as P or As of implant n-type impurity in substrate 1002, and p-type trap can be formed by such as the B of implanted with p-type impurity in substrate 1002.If needed, can also anneal after injection it.Those skilled in the art can expect that various ways is to form N-shaped trap, p-type trap, does not repeat them here.
On substrate 1002, such as, by epitaxial growth, form the first semiconductor layer 1004.Such as, the first semiconductor layer 1004 can comprise SiGe (Ge atomic percent is such as about 5-20%), and thickness is about 10-50nm.
Next, on the first semiconductor layer 1004, such as, by epitaxial growth, form the second semiconductor layer 1006.Such as, the second semiconductor layer 1006 can comprise Si, and thickness is about 20-100nm.
On the second semiconductor layer 1006, protective layer 1008 can be formed.Protective layer 1008 such as can comprise oxide (such as, silica), and thickness is about 10-50nm.This protective layer 1008 can protect the end of fin in process subsequently.In this example, protective layer 1008 patterned (such as, passing through photoetching) is the shape corresponding with the fin that will be formed afterwards.
Then, as shown in Figure 2, with the protective layer 1008 of composition for mask, selective etch such as reactive ion etching (RIE) second semiconductor layer 1006 and the first semiconductor layer 1004 successively, thus form fin structure F1.Although it is pointed out that etching stopping is in substrate 1002 in this embodiment at this, the disclosure is not limited thereto.Such as, etching can also proceed in substrate 1002 further, thus the fin structure obtained also comprises a part of trap 1002-1 in bottom.
Here it is pointed out that the regular rectangular shape of shape not necessarily shown in Fig. 2 of (between the fin structure) groove formed by etching, can be the taper type such as diminished gradually from top to bottom.
Then; as shown in Figure 3; can relative to protective layer 1008 (such as; silica), substrate 1002 and the second semiconductor layer 1006 (such as; Si); selective etch first semiconductor layer 1004 (such as, SiGe), makes the first semiconductor layer 1004 laterally recessed.Therefore, the part be made up of the first semiconductor layer in fin structure narrows.This laterally recessed width (dimension in figure in horizontal direction) can be about 3 ~ 10nm.
Then, as shown in Figure 4, filling dielectric in being laterally recessed into, with organizator side wall 1010.Such as, this filling such as can pass through deposit dielectric, then eat-back (such as, RIE) with the dielectric of selective removal deposit be positioned at laterally recessed outside part realize.Side wall 1010 can comprise nitride (such as, silicon nitride) or low-K dielectric as SiOF, SiCOH, SiO, SiCO, SiCON or high-k dielectrics etc.Comprise in the example of nitride at the dielectric of deposit, before deposit dielectric, alternatively can deposit one deck thin-oxide (not shown) as bed course, to alleviate the stress of nitride.
According to embodiment of the present disclosure, side wall 1010 can with electric charge, to introduce hole or electronics in the first semiconductor layer 1002.Particularly, (namely charged side wall 1010 can change the part that corresponds in fin structure, first semiconductor layer 1002) in electric potential field, this electric potential field can make thermogenetic electronics or hole draw in or pull out wherein, thus electronics or hole are hoarded in this part of fin structure.
Electric charge in the wall of side can by organizator side wall dielectric at least partially in the electric charge that comprises realize.Such as, be in the example of oxide/nitride lamination at side wall, nitride, or oxide, or can electric charge be contained both nitride and oxide.Such as, surface plasma process (such as, being limited to surface, within apart from surface about 1 ~ 2nm) can be carried out, electric charge is incorporated in dielectric.Particularly, plasma bombardment dielectric layer surface thus produce defect state wherein, this defect state can electronegative or positive charge.
Particularly, for the p-type device that will be formed on N-shaped trap 1002-1, the first semiconductor layer 1004 should present N-shaped on the whole; Or for the N-shaped device that will be formed on p-type trap 1001-1, the first semiconductor layer 1004 should present p-type on the whole.Like this, the first semiconductor layer 1004 can serve as break-through trapping layer subsequently.
For this reason, for p-type device side wall 1010 can (such as, density be about 1 × 10 with relatively high clean positive charge
17~ 1 × 10
21cm
-3), thus (such as, density is about 1 × 10 can to introduce relatively high electron concentration in the first semiconductor layer 1004
17~ 5 × 10
18cm
-3).Or, for n-type device side wall 1010 can (such as, density be about 1 × 10 with relatively high net negative charge
17~ 1 × 10
21cm
-3), thus (such as, density is about 1 × 10 can to introduce relatively high hole concentration in the first semiconductor layer 1004
17~ 5 × 10
18cm
-3).
After there is the fin structure of electrically charged side wall by above-mentioned process formation, the grid crossing with fin can be formed stacking, and form final semiconductor device (such as, FinFET).
In order to isolated gate heap superimposition substrate, first substrate forms separator 1012, as shown in Figure 5.Then this separator such as can by deposit dielectric material on substrate, and carry out eat-backing to be formed.In etch back process, control etch-back depths, make the separator after eat-backing that a part for side wall can be made to expose (giving prominence to relative to the end face of separator).Like this, separator 1012 just defines the fin F of the side of being located thereon.The part of fin structure F1 below fin F surrounded owing to being isolated layer 1012, thus in resulting devices, do not serve as the real fin for forming channel region
In one example, protective layer 1008 and dielectric substance 1012 comprise identical material, as oxide.Therefore, in the process that dielectric substance 1012 is eat-back, protective layer 1008 may be eliminated, as shown in Figure 5 simultaneously.
Subsequently, the grid crossing with fin can be formed on separator 1012 stacking.Such as, this can carry out as follows.Particularly, as shown in Figure 6 (Fig. 6 (b) shows the sectional view along AA ' line in Fig. 6 (a)), such as, by deposit, sacrificial gate dielectric layer 1014 is formed.Such as, sacrificial gate dielectric layer 1014 can comprise oxide, and thickness is about 0.8-1.5nm.In the example depicted in fig. 6, illustrate only the sacrificial gate dielectric layer 1014 of " ∏ " shape.But sacrificial gate dielectric layer 1014 also can be included in the part that the end face of separator 1012 extends.Then, such as, by deposit, form sacrificial gate conductor layer 1016.Such as, sacrificial gate conductor layer 1016 can comprise polysilicon.Sacrificial gate conductor layer 1016 can cover fin completely, and can carry out planarization such as chemico-mechanical polishing (CMP).Afterwards, composition is carried out to sacrificial gate conductor layer 1016, stacking to form grid.In the example of fig. 6, sacrificial gate conductor layer 1016 is patterned to the bar shaped crossing with fin.In addition, can also the sacrificial gate conductor layer 1016 after composition be mask, further composition be carried out to gate dielectric layer 1014.
As shown in the dotted-line ellipse circle in Fig. 6 (b), in the bottom of fin F, body side wall 1010 between the grid conductor formed subsequently and fin (in this example, the first semiconductor layer), thus the parasitic capacitance produced is relatively little.
After the grid conductor forming composition, such as, can grid conductor be mask, carry out haloing (halo) and inject and extension area (extension) injection.
Next, as shown in Fig. 7 (Fig. 7 (b) shows the sectional view along BB ' line in Fig. 7 (a)), side wall 1018 can be formed on the sidewall of sacrificial gate conductor layer 1016.Such as, can form by deposit the nitride that thickness is about 5-30nm, then RIE be carried out to nitride, form side wall 1018.Those skilled in the art will know that various ways is to form this side wall, does not repeat them here.
(due to the characteristic of etching, be generally such situation) when groove between fin is the taper type diminished gradually from top to bottom, side wall 1018 can not be formed on the sidewall of fin substantially.
After formation side wall, can grid conductor and side wall be mask, carry out source/drain (S/D) and inject.Subsequently, by annealing, the ion injected can be activated, to form source/drain region.
Next, as shown in Figure 8, such as, by deposit, dielectric layer 1020 is formed.This dielectric layer 1020 such as can comprise oxide.Subsequently, planarization such as CMP is carried out to this dielectric layer 1020.This CMP can stop at side wall 1018, thus exposes sacrificial gate conductor 1016.
Subsequently, as shown in Figure 9, such as, by TMAH solution, selective removal sacrificial gate conductor 1016, and sacrificial gate dielectric layer 1014 can be removed further, thus space is defined inside side wall 1018.
Then, as shown in Figure 10 (Figure 10 (b) shows the sectional view along BB ' line in Figure 10 (a)), by forming gate dielectric layer 1022 and grid conductor layer 1024 in space, final grid are formed stacking.Gate dielectric layer 1022 can comprise high-K gate dielectric such as HfO
2, thickness is about 1-5nm.Grid conductor layer 1024 can comprise metal gate conductor.Preferably, work function regulating course (not shown) can also be formed between gate dielectric layer 1022 and grid conductor layer 1024.
Like this, the semiconductor device according to this embodiment is just obtained.As shown in Figure 10, this semiconductor device can comprise: the first semiconductor layer 1004 and the second semiconductor layer 1006 of the composition formed successively on substrate 1002, wherein, first semiconductor layer 1004 and the second semiconductor layer 1006 are patterned to fin structure, and the first semiconductor layer 1004 is laterally recessed relative to the second semiconductor layer 1006; At the charged side wall 1010 of laterally recessed middle formation; 1002 separators 1012 formed on substrate, the end face of separator 1012 is between the end face and bottom surface of the first semiconductor layer 1004, and wherein fin structure serves as the fin of this semiconductor device in the part of separator 1012 (end face) top; And the grid crossing with fin formed on separator are stacking.
As mentioned above, for p-type device, the first semiconductor layer 1004 can present N-shaped; And for N-shaped device, the first semiconductor layer 1004 can present p-type.This first semiconductor layer can serve as break-through barrier layer.And this first semiconductor layer can reduce B diffusion, thus can tie clearly being formed between channel region and substrate bulk.
In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiment of the present disclosure is described.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the present disclosure.The scope of the present disclosure is by claims and equivalents thereof.Do not depart from the scope of the present disclosure, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.
Claims (10)
1. a N-type semiconductor device, comprising:
First semiconductor layer of the composition that substrate is formed successively and the second semiconductor layer, wherein, the first semiconductor layer and the second semiconductor layer are patterned to fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer;
The side wall formed in described transverse direction is recessed into, side wall comprises dielectric substance;
The separator that substrate is formed, the end face of described separator is between the end face and bottom surface of the first semiconductor layer, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And
The grid crossing with fin that separator is formed are stacking,
Wherein, side wall, with net negative charge, makes the first semiconductor layer present p-type.
2. N-type semiconductor device according to claim 1, wherein, in the wall of side, the density of negative electrical charge is about 1 × 10
17~ 1 × 10
21cm
-3, and in the first semiconductor layer, the concentration in hole is about 1 × 10
17~ 5 × 10
18cm
-3.
3. a P-type semiconductor device, comprising:
First semiconductor layer of the composition that substrate is formed successively and the second semiconductor layer, wherein, the first semiconductor layer and the second semiconductor layer are patterned to fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer;
The side wall formed in described transverse direction is recessed into, side wall comprises dielectric substance;
The separator that substrate is formed, the end face of described separator is between the end face and bottom surface of the first semiconductor layer, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And
The grid crossing with fin that separator is formed are stacking,
Wherein, side wall, with clean positive charge, makes the first semiconductor layer present N-shaped.
4. P-type semiconductor device according to claim 3, wherein, in the wall of side, the density of positive charge is about 1 × 10
17~ 1 × 10
21cm
-3, and in the first semiconductor layer, the concentration of electronics is about 1 × 10
17~ 5 × 10
18cm
-3.
5. semiconductor device according to any one of claim 1 to 4, wherein, substrate comprises body Si, and the first semiconductor layer comprises SiGe, and the second semiconductor layer comprises Si.
6. semiconductor device according to claim 5, wherein, side wall comprises the lamination of oxide and nitride.
7. manufacture a method for N-type semiconductor device, comprising:
Substrate is formed the first semiconductor layer and the second semiconductor layer successively;
Composition is carried out, to form fin structure to the second semiconductor layer, the first semiconductor layer;
The first semiconductor layer in selective etch fin structure, makes it laterally recessed;
The dielectric of middle filling tape net negative charge is recessed into, with organizator side wall in described transverse direction;
Substrate forms separator, and described separator exposes a part for described side wall, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And
Separator forms the grid crossing with fin stacking.
8. manufacture a method for P-type semiconductor device, comprising:
Substrate is formed the first semiconductor layer and the second semiconductor layer successively;
Composition is carried out, to form fin structure to the second semiconductor layer, the first semiconductor layer;
The first semiconductor layer in selective etch fin structure, makes it laterally recessed;
The dielectric of the clean positive charge of middle filling tape is recessed into, with organizator side wall in described transverse direction;
Substrate forms separator, and described separator exposes a part for described side wall, and wherein the part of fin structure above separator serves as the fin of this semiconductor device; And
Separator forms the grid crossing with fin stacking.
9. the method according to claim 7 or 8, wherein, substrate comprises body Si, and the first semiconductor layer comprises SiGe, and the second semiconductor layer comprises Si.
10. the method according to claim 7 or 8, wherein, organizator side wall comprises:
Substrate forms oxide skin(coating) and nitride layer successively; And
Selective removal oxide skin(coating) and the part of nitride layer outside being laterally recessed into.
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