CN100353567C - Method of manufacturing variable capacitor - Google Patents
Method of manufacturing variable capacitor Download PDFInfo
- Publication number
- CN100353567C CN100353567C CNB2003101137003A CN200310113700A CN100353567C CN 100353567 C CN100353567 C CN 100353567C CN B2003101137003 A CNB2003101137003 A CN B2003101137003A CN 200310113700 A CN200310113700 A CN 200310113700A CN 100353567 C CN100353567 C CN 100353567C
- Authority
- CN
- China
- Prior art keywords
- ion
- layer
- doped
- doped region
- ion well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000003990 capacitor Substances 0.000 title abstract description 3
- 150000002500 ions Chemical class 0.000 claims abstract description 100
- 238000000034 method Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 88
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 2
- 239000004575 stone Substances 0.000 claims 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 239000000428 dust Substances 0.000 description 4
- 230000009514 concussion Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a method for manufacturing a variable capacitor. An ion well of a first current conducting type is formed in a substrate. A plurality of isolation structures are arranged on the surface of the ion well. The isolation structures are provided with at least one active region on the surface of the ion well. Ions of the first current conducting type are implanted on the surface of the ion well, so that a doping region is formed in the active region. A doping layer of a second current conducting type is formed on the surface of the substrate, so that part of the surface of the doping region is covered. A self-aligned metal silicide layer is formed on the surfaces of the doping region and the doping layer.
Description
Technical field
The present invention relates to a kind of method of making variable capacitance, refers to that especially a kind of making one has the method that PN connects the variable capacitance of face.
Background technology
In modern information industry, various data, data, message, image etc. all are to transmit with the form of electric signal, and are used for handling the treatment circuit of electric signal, also just become one of most important basis in the modern information industry.For instance, in general information system (similarly being computer), all will operate together with each digital circuit that a clock pulse is coordinated in the digital system, the oscillator that therefore is used for producing clock pulse is one of important circuit building square indispensable in the Modern Digital System.In addition, coordinate different clock pulse (for example in the communication system of transmission signal) synchronously, also need to use phase lock circuitry; Then need accurate voltage-controlled oscillator (VCO) in the phase lock circuitry, control voltage-controlled oscillator (VCO) with voltage and shake the different concussion signal of frequency, synchronous to coordinate each clock pulse.Also having, similarly is in some accurate filter, and also normal use can be adjusted resistance-capacitance (RC) filter of frequency filtering.
No matter be the filtering characteristic (similarly being the passband frequency range of filter) of resistance-capacitance (RC) filter, or the concussion characteristic of inductor-capacitor (LC) voltage-controlled oscillator (VCO) (similarly being the frequency of concussion signal), can be adjusted with the mode that changes capacitance.Developed at present and multiple variable capacitance and can be applicable in the integrated circuit package, for example PN diode, Xiao's based diode (Schottky diode) and (the metal oxide semiconductor of metal-oxide-semiconductor (MOS), MOS) transistors diodes etc. is common two-carrier transistor (the bipolar junction transistor that is applied to, BJT), CMOS (Complementary Metal Oxide Semiconductor) (complementary metal oxide semiconductor, CMOS) variable capacitance in transistor and two-carrier-CMOS (Complementary Metal Oxide Semiconductor) transistor electronic building bricks such as (BiCMOS).
Please refer to Fig. 1, Fig. 1 is the generalized section of the variable capacitance of known PN diode formation.As shown in Figure 1, one substrate 10 includes a N type ion well 12, and a plurality of isolation structures 14, for example field oxide (field oxide layer) or shallow isolating trough (shallow trenchisolation) structure are located at N type ion well 12 and substrate 10 surfaces.Isolation structure 14 is to define a plurality of presumptive areas in N type ion well 12 surfaces, is used for making N type doped region 16 and P type doped region 18 respectively, has the diode structure that PN connects face to form one.When applying a reverse bias, the PN of diode connects face and can produce one and can be considered the exhaustion region (depletion region) of dielectric layer, and to make diode can equivalence be an electric capacity between two conducting regions of negative electrodes such as N type doped region 16, P type doped region 18, anode.Along with the anode of diode, cross-pressure size between negative electrode are adjusted, the width of exhaustion region can change thereupon, and then reaches the purpose that changes the equivalent capacitance value that diode provides between anode, negative electrode.
Prior art method needs to utilize one light shield to define the position of N type doped region 16, P type doped region 18 when making variable capacitance usually, adjust CONCENTRATION DISTRIBUTION in N type doped region 16, the P type doped region 18 with the admixture that utilizes different kenels respectively, improve the quality factor (quality factor) of variable capacitance.In addition, between the anode of known variable capacitance and negative electrode the institute through approach be by P type doped region 18 behind N type ion well 12 again to N type doped region 16, in the ordinary course of things, the doping content of N type ion well 12 is not high, therefore cause the resistance value in this approach to increase easily, influence the electrical performance of variable capacitance.Under the prerequisite that does not increase process complexity, how to improve coordinability (tunability), the quality factor of variable capacitance and a good capacitance-voltage linear relationship (C-V linearity) is provided, with effective electrical performance of improving variable capacitance, make it can satisfy the harsh day by day service conditions of circuit unit such as filter or voltage-controlled oscillator (VCO), become the important topic that present industry is pursued more high-quality variable capacitance.
Summary of the invention
Therefore, purpose of the present invention is promptly in that a kind of method of making variable capacitance is provided, with effective electrical performance of improving variable capacitance.
In preferred embodiment of the present invention, this method is that the ion well and a plurality of isolation structure that form one first conductive type in a substrate are located in the ion well, and makes these isolation structures define at least one active area in ion well surface.Then implant the ion of first conductive type, in active area, to form a doped region in ion well surface.Form the doped layer of one second conductive type subsequently in substrate surface, to cover the part surface of doped region, wherein the interface of this doped layer and this doped region is positioned at this substrate surface, and aims at metal silicide layer voluntarily in doped region, doped layer surface formation one.
Because the present invention utilizes the second conductive type doped layer be located at the first conductive type doped region in the substrate and be covered in the doped region top to have the variable capacitance that PN connects face, therefore the present invention does not need to utilize in addition one light shield to define the position of doped region, doped layer and carry out its dopping process, not only can save light shield and fabrication steps, more the anode of variable capacitance and the distance between negative electrode be can effectively shorten, its quality factor and electrical performance improved.In addition, the present invention can also further adjust the concentration of doped region, make doped region concentration be higher than the ion well concentration of its below, thus, the exhaustion region that PN connects face is slowly to diffuse to the lower ion well area of concentration by the higher doped region surface of concentration, and then can improve the capacitance-voltage linear relationship of variable capacitance, can also provide higher harmony simultaneously.
Description of drawings
Fig. 1 is the generalized section of a known variable capacitance.
Fig. 2 to Fig. 5 makes the method schematic diagram of a variable capacitance for the present invention.
Fig. 6 is the top view of the present invention's one variable capacitance.
Fig. 7 is the schematic diagram that concerns of the degree of depth of the present invention's one variable capacitance and concentration.
Fig. 8 to Figure 15 makes the method schematic diagram of a CMOS transistor AND gate one variable capacitance for the present invention.
Symbol description:
10,20,40 substrates, 12,22 ion wells
14,24,50 isolation structures, 16,18,26,64 doped regions
28,76 doped layers, 30,78 blocking layer of metal silicide
32,80 metal silicide layers, 42,52 embedded doped regions
44,46,48 ion wells, 56,58 gates
60,62 light dope drains, 66 sidewall
68,70 source/drain, 72 protective layers
74 open the A active area
I CMOS area I I variable capacitance zone
Embodiment
Please refer to Fig. 2 to Fig. 5, Fig. 2 to Fig. 5 makes the method schematic diagram of a variable capacitance for the present invention.As shown in Figure 2, at first provide a substrate 20, and substrate 20 includes a N type ion well 22, and a plurality of isolation structure 24, for example field oxide or shallow trench isolation structure are located at ion well 22, substrate 20 surfaces.Isolation structure 24 is to define at least one active area A in ion well 22 surfaces, is used for making the anode and the negative electrode of variable capacitance.Subsequently, the admixture of utilization and ion well 22 identical conduction patterns mixes, and forms N type doped regions 26 with 22 surfaces of the ion well in active area A, is used as the bottom electrode (negative electrode) of variable capacitance.In preferred embodiment of the present invention, can comprise at least one embedded N type doped region (not shown) in the substrate 20 in addition and be located at ion well 22 belows, with the resistance of further reduction doped region 26, ion well 22.In addition, the dopant concentration of doped region 26 is the dopant concentrations that are higher than ion well 22, variable capacitance processing procedure of the present invention is combined with the CMOS processing procedure, utilize a dopping process to make the light dope drain of doped region 26 and nmos pass transistor, and utilize another dopping process to make N type ion well 22 and the transistorized N type of PMOS ion well.In other embodiments of the invention, ion well 22 can also be a P type ion well, and doped region 26 can be a P type doped region.
As shown in Figure 3, then carry out a deposition manufacture process in substrate 20 surfaces, and carry out a dopping process synchronously, with the doped layer 28 that has different conductive type in substrate 20 surface formation one and ion well 22, doped region 26, be used as the top electrode (anode) of variable capacitance, and make between doped layer 28 and the doped region 26 and to form a PN and connect face.In preferred embodiment of the present invention, ion well 22, doped region 26 are to be N type doped region, and doped layer 28 is a P type doped layer, it for example is the P type epitaxial layer that composite materials such as silicon, SiGe or silicon and SiGe form, its thickness is approximately between the 1000-1500 dust, perhaps be once the doped P-type polysilicon layer, its thickness is approximately between the 2000-3000 dust.In addition, in other embodiments of the invention, ion well 22, doped region 26 can also be P type doped region, and 28 of doped layers are a N type doped layer, for example being the N type epitaxial layer that composite materials such as silicon, SiGe or silicon and SiGe form, perhaps is once the N type polysilicon layer that mixes.
As shown in Figure 4, then an ion disposing process is carried out on substrate 20 surfaces, implant P type ion (or N type ion) in doped layer 28, with the resistance of further adjustment doped layer 28.As shown in Figure 5, form one afterwards again and aim at blocking layer of metal silicide (salicide block voluntarily, SAB) 30 doped layer 28 surfaces that are covered in doped region 26 tops avoid the follow-up PN that destroys 26 of doped layer 28 and doped regions when aiming at the metal silicide processing procedure voluntarily to connect face.Can select to carry out the doped layer 28 of a gold-tinted and etch process removal part subsequently, pattern with definition doped layer 28, and form one in doped layer 28 with doped region 26 surfaces again and aim at metal silicide layer 32 voluntarily, with the anode of reduction variable capacitance and the contact resistance of negative electrode, finish the making of variable capacitance.The top view of variable capacitance is as shown in Figure 6, and wherein doped layer 28 is doped region 26 tops that are covered in part, so that doped layer 28, doped region 26 all include the zone that makes metal silicide layer (indicating part as oblique line), can be used for connecting other lead.
Please refer to Fig. 7, Fig. 7 is the schematic diagram that concerns of the degree of depth of the present invention's one variable capacitance and concentration.As shown in Figure 7, variable capacitance of the present invention meets the face place at the PN of P type doped layer (P+) and N type doped region (NW+NLDD) and has higher dopant concentration, can obtain higher unit-area capacitance value.Because the unit-area capacitance value of variable capacitance is to be inversely proportional to the exhaustion region width, therefore along with the voltage that puts on variable capacitance increases, the width of exhaustion region can increase gradually, that is exhaustion region can diffuse to lower N type ion well (NW) zone of concentration downwards, and obtain lower unit-area capacitance value, therefore variable capacitance of the present invention has preferable capacitance-voltage linear relationship, can also provide higher harmony simultaneously.
Please refer to Fig. 8 to Figure 15, Fig. 8 to Figure 15 makes the method schematic diagram of a CMOS transistor AND gate one variable capacitance for the present invention.In preferred embodiment of the present invention, variable capacitance is to utilize a BiCMOS processing procedure to form, and with under the situation of light shield that must not increase existing processing procedure or step, just can reach the purpose of the electrical performance of improving variable capacitance.As shown in Figure 8, the inventive method is that a substrate 40 is provided earlier, and substrate 40 includes one and be used for making the transistorized CMOS area I of CMOS, and a variable capacitance area I I who is used for making variable capacitance.In addition, substrate 40 can also comprise a BJT zone (not shown) that is used for making BJT in addition.Utilize N type ion pair substrate 40 to mix then, in substrate 40, to form a plurality of embedded N type doped regions 42.Implant P type ion and N type ion in substrate 40 surfaces in regular turn subsequently, in the CMOS area I, forming at least one P type ion well 44, and in the CMOS area I, form at least one N type ion well 46, in variable capacitance area I I, form at least one N type ion well 48.
Form a plurality of isolation structures 50 in substrate 40 surfaces afterwards, for example field oxide or shallow trench isolation structure, to define a nmos transistor region respectively at P type ion well 44 surfaces, define a PMOS transistor area in N type ion well 46 surfaces, and the active area that defines a variable capacitance in N type ion well 48 surfaces.Carry out an ion disposing process subsequently again,, be used as channel stop (channel stop), prevent to produce leakage current between CMOS transistor AND gate variable capacitance between N type ion well 46,48, to form an embedded P type doped region 52.
As shown in Figure 9, utilize a heat treatment that the ion in the N type ion well 46,48 is become to embedded N type doped region 42.In addition, in other embodiments of the invention, can also utilize ion disposing process in N type ion well 48, to form at least one N type doped region (not shown) again and be connected to embedded N type doped region 42, to be used as the bottom electrode contact zone of variable capacitance.Yet the present invention can also directly utilize the design (shown in the variable capacitance top view of Fig. 6) of the top electrode and the bottom electrode layout patterns of variable capacitance, make the top electrode of variable capacitance only be covered in the part lower electrode surface, so that bottom electrode can be reserved the zone that makes contact plunger (metal silicide layer), and save ion disposing process one.
As shown in figure 10, next form a gate 56 and 58 respectively, and utilize N type ion to form two N type light dope drains 60, form a N type doped region 64 in N type ion well 48 surfaces simultaneously in P type ion well 44 surfaces in ion well 44,46 surfaces.In preferred embodiment of the present invention, doped region 64 is intended for the bottom electrode of variable capacitance, and the dopant concentration of doped region 64 is the dopant concentrations that are higher than ion well 48.Utilize P type ion to form two P type light dope drains 62 subsequently again in N type ion well 46 surfaces.As shown in figure 11, in gate 56 sidewalls to form sidewall 66 with gate pole 58 sidewalls, and utilize N type ion to form two N type source/drain 68 once more in P type ion well 44 surfaces, and utilize P type ion to form two P type source/drain 70 in N type ion well 46 surfaces, to finish the CMOS processing procedure.
As shown in figure 12, then in substrate 40 surface coverage one protective layer 72, and protective layer 72 surfaces include an opening 74, to expose doped region 64 surfaces.Protective layer 72 mainly is to be used for covering the CMOS transistor, is beneficial to the follow-up top electrode of making variable capacitance in doped region 64 tops.Protective layer 72 can be an oxide layer, a silicon nitride layer, or the composite bed of being made up of other dielectric materials such as oxide layer and silicon nitride layers.
As shown in figure 13, carry out a deposition manufacture process in substrate 40 surfaces, and carry out a dopping process synchronously, with the doped layer 76 that has different conductive type in substrate 40 surface formation one and ion well 48, doped region 64, be used as the top electrode (anode) of variable capacitance, and make between doped layer 76 and the doped region 64 and to form a PN and connect face.In preferred embodiment of the present invention, ion well 48, doped region 64 are to be N type doped region, and doped layer 76 is a P type doped layer, it for example is the P type epitaxial layer that composite materials such as silicon, SiGe or silicon and SiGe form, its thickness is approximately between the 1000-1500 dust, perhaps be once the doped P-type polysilicon layer, its thickness is approximately between the 2000-3000 dust.In addition, in other embodiments of the invention, ion well 48, doped region 64 can also be P type doped region, and 76 of doped layers are a N type doped layer, for example being the N type epitaxial layer that composite materials such as silicon, SiGe or silicon and SiGe form, perhaps is once the N type polysilicon layer that mixes.
Then an ion disposing process is carried out on substrate 40 surfaces, implant P type ion (or N type ion) in doped layer 76, with the resistance of further adjustment doped layer 76.As shown in figure 14, form one again and aim at doped layer 76 surfaces that blocking layer of metal silicide 78 is covered in doped region 64 tops voluntarily, avoid the follow-up PN that destroys 64 of doped layer 76 and doped regions when aiming at the metal silicide processing procedure voluntarily to connect face.Subsequently as shown in figure 15, can select to carry out the doped layer 76 of a gold-tinted and etch process removal part, pattern with definition doped layer 76, and form one in doped layer 76 with doped region 64 surfaces again and aim at metal silicide layer 80 voluntarily, with the anode of reduction variable capacitance and the contact resistance of negative electrode, finish the making of variable capacitance.
Compared to known variable capacitance manufacture method, the present invention utilizes the doped layer (top electrode) be located at the doped region (bottom electrode) in the substrate and be covered in the doped region top to have the variable capacitance that PN connects face, therefore the present invention does not need to utilize in addition one light shield to define the position of doped region, doped layer and carry out its dopping process, not only can save light shield and fabrication steps, more the anode of variable capacitance and the distance between negative electrode be can effectively shorten, its quality factor and electrical performance improved.In addition, the present invention can also further adjust the concentration of the doped region of variable capacitance, make doped region concentration be higher than its below ion well concentration, thus, the exhaustion region that PN connects face is slowly to diffuse to the lower ion well area of concentration by the higher doped region surface of concentration, and then can improve the capacitance-voltage linear relationship of variable capacitance, can also provide higher harmony simultaneously.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (16)
1. method of making variable capacitance, this method includes the following step:
One substrate is provided, and this substrate includes the ion well of one first conductive type and is located at a plurality of isolation structures in this ion well, and this isolation structure is to define at least one active area in this ion well surface;
Implant the ion of first conductive type in this ion well surface, in this active area, to form a doped region;
Form the doped layer of one second conductive type in this substrate surface, to cover the part surface of this doped region, wherein the interface of this doped layer and this doped region is positioned at this substrate surface; And
Aim at metal silicide layer voluntarily in this doped region and this doped layer surface formation one.
2. according to the method for claim 1, other is contained in this doped layer surface and forms one and aim at blocking layer of metal silicide voluntarily, aims at the face that connects between this doped layer of metal silicide damage layer and this doped region voluntarily to avoid this.
3. according to the process of claim 1 wherein that the embedded doped region that this substrate surface comprises at least one first conductive type in addition is located at this ion downhole.
4. according to the process of claim 1 wherein that this substrate surface comprises at least one CMOS (Complementary Metal Oxide Semiconductor) transistor in addition, and this doped region is to utilize same dopping process to form with the transistorized light dope drain of this CMOS (Complementary Metal Oxide Semiconductor).
5. according to the method for claim 4, wherein this method is before forming this doped layer, and other is contained in this substrate surface and forms at least one protective layer, to be used for covering this CMOS (Complementary Metal Oxide Semiconductor) transistor.
6. according to the process of claim 1 wherein that this doped layer comprises a crystal silicon layer of heap of stone.
7. according to the process of claim 1 wherein that this doped layer comprises a polysilicon layer.
8. according to the method for claim 1, other comprises and carries out an ion disposing process, to implant the ion of second conductive type in this doped layer, is used for adjusting the resistance of this doped layer.
9. according to the process of claim 1 wherein that the dopant concentration of this doped region is higher than the dopant concentration of this ion well.
10. method of in a substrate, making at least one CMOS (Complementary Metal Oxide Semiconductor) transistor and at least one variable capacitance, include one in this substrate and be used for making the transistorized first area of this CMOS (Complementary Metal Oxide Semiconductor), and a second area that is used for making this variable capacitance, this method includes the following step:
Implant the first conductive type ion in this substrate surface, to form at least one first ion well in this first area and to form at least one second ion well in this second area;
Implant the second conductive type ion in this substrate surface, to form at least one the 3rd ion well in this first area;
Form a plurality of isolation structures in this substrate surface;
Form one first gate and one second gate respectively at this first ion well surface and the 3rd ion well surface;
Utilize the first conductive type ion to form two first light dope drains, form a doped region in this second ion well surface simultaneously in the 3rd ion well surface;
Utilize the second conductive type ion to form two second light dope drains in this first ion well surface;
Form sidewall in this first gate sidewalls and this second gate sidewalls;
Form two first source/drain in this first ion well surface, and form two second source/drain with first conductive type in the 3rd ion well surface with second conductive type; Cover a protective layer in this substrate surface, and this protective layer surface includes an opening, to expose this doped region surface;
Form the doped layer of one second conductive type in this doped layer surface; And
Carry out one and aim at the metal silicide processing procedure voluntarily, aim at metal silicide layer voluntarily to form one in this substrate surface.
11. according to the method for claim 10, other is contained in this doped layer surface and forms one and aim at blocking layer of metal silicide voluntarily, aims at the face that connects between this doped layer of metal silicide damage layer and this doped region voluntarily to avoid this.
12. according to the method for claim 10, other is contained in the embedded doped region that this second ion downhole forms at least one first conductive type.
13. according to the method for claim 10, wherein this doped layer comprises a crystal silicon layer of heap of stone.
14. according to the method for claim 10, wherein this doped layer comprises a polysilicon layer.
15. according to the method for claim 10, other comprises and carries out an ion disposing process, to implant the ion of second conductive type in this doped layer, is used for adjusting the resistance of this doped layer.
16. according to the method for claim 10, wherein the dopant concentration of this doped region is higher than the dopant concentration of this second ion well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101137003A CN100353567C (en) | 2003-11-19 | 2003-11-19 | Method of manufacturing variable capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101137003A CN100353567C (en) | 2003-11-19 | 2003-11-19 | Method of manufacturing variable capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1619838A CN1619838A (en) | 2005-05-25 |
| CN100353567C true CN100353567C (en) | 2007-12-05 |
Family
ID=34760015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101137003A Expired - Lifetime CN100353567C (en) | 2003-11-19 | 2003-11-19 | Method of manufacturing variable capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100353567C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1165586A (en) * | 1995-09-18 | 1997-11-19 | 菲利浦电子有限公司 | Varicap diode and method of manufacturing a varicap diode |
| CN1168741A (en) * | 1994-10-13 | 1997-12-24 | 微米技术有限公司 | Split-polysilicon CMOS process for multi-megabit dynamic memories with stacked capacitor cells |
| US5965912A (en) * | 1997-09-03 | 1999-10-12 | Motorola, Inc. | Variable capacitor and method for fabricating the same |
-
2003
- 2003-11-19 CN CNB2003101137003A patent/CN100353567C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1168741A (en) * | 1994-10-13 | 1997-12-24 | 微米技术有限公司 | Split-polysilicon CMOS process for multi-megabit dynamic memories with stacked capacitor cells |
| CN1165586A (en) * | 1995-09-18 | 1997-11-19 | 菲利浦电子有限公司 | Varicap diode and method of manufacturing a varicap diode |
| US5965912A (en) * | 1997-09-03 | 1999-10-12 | Motorola, Inc. | Variable capacitor and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1619838A (en) | 2005-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100391010C (en) | Junction varactor with high q factor | |
| KR100564890B1 (en) | Manufacture of Bipolar / CMOS Integrated Circuits | |
| CN100499127C (en) | Vertical PNP transistor and method of making same | |
| CN1296290A (en) | Linear capacitor structure in CMOS technology | |
| TW201436046A (en) | RF device and method for forming an RF device | |
| US10340395B2 (en) | Semiconductor variable capacitor using threshold implant region | |
| US20180323115A1 (en) | Bulk CMOS RF Switch With Reduced Parasitic Capacitance | |
| US6001701A (en) | Process for making bipolar having graded or modulated collector | |
| US6653716B1 (en) | Varactor and method of forming a varactor with an increased linear tuning range | |
| US6949440B2 (en) | Method of forming a varactor | |
| US6387769B2 (en) | Method of producing a schottky varicap | |
| US8232157B2 (en) | Semiconductor device and method of manufacturing the same | |
| US5965928A (en) | Semiconductor device with MOS capacitor and fabrication method thereof | |
| KR100629194B1 (en) | Method of manufacturing variable capacitance diode and variable capacitance diode | |
| US6867107B2 (en) | Variable capacitance device and process for manufacturing the same | |
| CN100353567C (en) | Method of manufacturing variable capacitor | |
| US7994563B2 (en) | MOS varactors with large tuning range | |
| JP2003007841A (en) | Method of manufacturing semiconductor device | |
| TWI242257B (en) | Junction varactor | |
| US5528066A (en) | Bipolar transistor having a collector well with a particular concentration | |
| JP2001291781A (en) | Method for manufacturing semiconductor device | |
| US6753573B2 (en) | Semiconductor device having complementary MOS transistor | |
| KR20030054746A (en) | Method for forming semiconductor device | |
| TW587302B (en) | Manufacturing method for MOS capacitor | |
| TWI222165B (en) | Method of forming a varactor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20071205 |
|
| CX01 | Expiry of patent term |