587302 05799twfl .doc/006 修正曰期93.1.19 玖、發明說明： 本發明是有關於一種金氧半導體(MOS)電容器的製造 方法，且特別是有關於製造一種具有與基底相同導電型式 之金氧半導體電容的製造方法。 在一同時具有處理數位(Digital)及類比(Analog)信號之 積體電路（1C)中，例如，在一資料/通訊（Information &Communication)元件中，類比及數位信號是經由不同之半 導體元件處理的，因爲類比信號的處理需要一高品質(High Performance)的電容器。而一般在於一具有金氧半導體之積 體電路中，多半都使用金氧半導體電容器來達到上述目 的。， · 金氧半導體電容器於類比或是混合操作模式的角色， 不同於數位操作模式。一般而言，當電容元件於積體電路 中，是一重要元件，需要很精準的電容，電容元件通常是 經一特殊製程製造。半導體的電容元件，通常分爲多晶矽 對多晶矽，金屬對多晶矽，或是金屬對金屬。金屬的電極 沒有缺乏型電容。但是以多晶砂爲電極的情形，多晶砂本 身會有缺乏型電容。因此一般多晶矽電極需摻雜足夠的雜 質，以降低缺乏型電容。缺乏型電容會造成電容値的變化。 這些變化在類比或是混合操作模式，必須仔細考慮。 4 587302 05799twfl.doc/006 ' 修正日期 93.1.19 對於數位操作模式，電容元件不是電路的主要部分， 然而數位電路也可能需要電容器元件’以達到一些特殊功 能。此時電容元件的品質要求，可能不需要如類比電路中 所需的品質。電容元件就可利用原本製程形成，不須特殊 製程。常見的是所謂的金氧半導體電容器，其可經一般類 似的金氧半導體電晶體製程形成。 在半導體製造，互補型金氧半導體(CMOS)積體電路是 一般習知的設計。一個CMOS元件，一般包括許多個P-型 電晶體，與N-型電晶體，這些電晶體通常形成於同一個基 底上之對應井區。特別是於雙井設計的CMOS包括有不同 導電型的井區，’其一般是相鄰的。此CMOS元件，不僅需 要金氧半導體(M0S)電晶體以外，其也需要電容器。此電 容一般是由M0S電容器達成，例如由美國第5,703,806號 專利及第5，168,075號專利。然而此傳統M0S電容器仍有 因半導體材料缺乏效應所引起的一些缺點，其會影響到 CMOS元件的性能。如此，要得到穩定的電容値，其僅能 於低電壓的操作。 傳統M0S電容器一般僅利用源/汲區域與閘極之間的 重疊部分來達成。這也會使的需要多餘的光罩與植入步 驟。另外而M0S電容器也會使用在一數位類比混合的電 5 587302 05799twfl.doc/006 修正曰期93.1.19 路中，其需要特殊製程。 在一個傳統的金氧半導體(MOS)電容器中，源極及汲 極彼此短路，以作爲電容器其中之一電極，閘氧化層則作 爲電容器的介電層，而閘極則爲電容器的另一電極。第1A 圖繪示出在一互補型金氧半導體(CMOS)積體電路中，形成 於一 P井之NM0S電容器，以及形成於一 N井之PM0S電 容器。於第1A圖中，一個M0S電晶體有一閘極，其包 括一閘氧化層106, 一多晶矽層108,以及一金屬矽化層 110。於閘極的側壁有一間隙壁112。於間隙壁112下的基 底形成有一源/汲延伸區 116(source/drain extension region)。 一源/汲區域114也形成於此基底100中，位於閘極的兩側。 對應於不同的井區105，也形成有另一 M0S電晶體。傳統 的電容器就如一 M0S電晶體，但是操作方式不同。 針對電容的用途，一通道摻雜區也可形成於閘氧化層 106下的井區104中。通道摻雜區可降低電容的操作電壓。 多種不同的電容存在於第1A圖中的M0S電容器。例 如以NM0S電容器爲例，多種不同的電容繪示於第1B圖。 由於缺乏型電容的缺乏型效應’ 一電容118存在於閘 氧化層106與多晶矽層1〇8之介面。而介於多晶矽層1〇8 與基底井區104之間，有一電容120，其中閘氧化層106 6 587302 05799twn.doc/006 · 修正日期 93.1.19 爲介電層。如果井區104當作一電容之電極，由於缺乏型 效應，一電容122也存在於閘氧化層106下方的井區104 表面。如果以源/汲極區當爲電容之電極，一電容124也存 在於多晶矽層108與源/汲極區之間。 另外，在閘極頂部也有一金屬矽化層110,其有一些 功能，如第1C圖所示。第1C圖是一上視圖，繪示於不同 井區的MOS元件，例如一 P型井區與一 N型井區相互鄰 近接觸。此時，一個二極體自然形成於介面。爲了避免二 極體影響連接，金屬矽化層110可連接不同型的MOS閘 極。在剖面圖，如第1A圖中，金屬矽化層110形成於閘 極頂部。 ^ 對於一個金氧半導體元件如第2圖中所示，一氧化層 〇與一金屬層Μ，依序形成於一半導體基底S，例如P型 矽半導體基底之上。當一閘極電壓Vg施加於金屬層Μ之 上，此MOS元件就如一個電容。當閘極電壓Vg爲負値時， 電洞會累積於靠近氧化層0的半導體基底S的表面。此種 情形稱爲一累積模式（accumulation mode)。當閘極電壓Vg 爲負値到某一個値時，電容質有一固定値。當閘極電壓Vg 爲正値，一強反轉現象開始發生於半導體基底表面上。產 生強反轉現象的最小電壓値稱爲，平面帶電壓（flat-band 7 587302 05799twfl.doc/006 · 修正日期 93.1.19 voltage)。平面帶電壓取決於半導體基底得功函數。當閘極 電壓Vg高於平面帶電壓，但是還不是足夠高，此時電洞 開始被驅離開閘極，留下一些負電，此時稱爲缺乏模式 (depletion mode)。當閘極電壓Vg高到M0S元件的起始電 壓時，強反轉完全發生於氧化層下的基底表面。 第3圖繪示一傳統M0S電晶體，對應於不同起始電 壓値VT的汲極電流Id與汲極電壓Vd的變化。當閘極電壓 Vg高於起始電壓値VT以啓動M0S電晶體，在汲極電壓 Vd大於某一個値時，汲極電流Id趨於一平穩値。當汲極電 壓vd於開始階段，汲極電流Id處於線性特性。線性特性 給於M0S電晶體有多種用途。 此一個M0S電容器可在下列三種模式下操作： 1·當閘極偏壓(Gate Bias)足夠局時，亦即高過nm〇S 之電晶體模式之起始電壓時，在基底/氧化層之間的介面， 亦即一反相層(Inversion Layer)附近，會產生一兩度空間的 電子流(Electron Gas)。在反相層中之電子則經由N+植入源 /汲極區，與電極導通，在此一操作模式下，可得一高品質 之固定電容値。 2.當閘極偏壓介於上述之起始電_及平面帶電壓時， 基底下相當之深度爲空乏區’因此形成一可變電容器 8 05799twfl.doc/006 修正日期93.1.19 (Variable Capacitor)。由於淡摻雜之P型基底不經由重摻雜 之N型源/汲區連接電極’而由基底在相當距離連接電極’ 如此，導致一高的串聯電阻(High Series Resistance)。此操 作模式一般稱爲缺乏操作模式。 3.當閘極偏壓低於平面帶電壓時，電洞累積於閘電 極下方，在此一模式的操作下，若欲經由P·基底電極連接 井區，亦同時遭受相當高的串聯電阻。 因此，由於電容器之電容値決取於施加之電壓’當其 應用於一類比電路時，信號極易失真，而使得金氧半導電 體電容器的實際應用產生困難。 _ 此外，如以上所述，傳統之金氧半導體電容器在缺乏 模式下，由於其中一個電極爲基底，且基底之接觸端在相 當之距離以外，而使得電容器遭受到極高的串聯電阻，這 些高串聯電阻具有下列影響： 1、 金氧半導體電容器之電阻-電容常數（RC Time Constant)及此一寄生電阻（Parasitic Resistor)產生了 一 個低 通頻率響應（Low-Pass Frequency Response)，以限制金氧半 導體可變電容器結構之適應頻率範圍。 2、 即使在金氧半導體可變電容器結構之可適用頻率 範圍中，高串聯電阻亦產生一高信號功率損失，因此，導 9 587302 05799twfl.doc/006 修正曰期93.1.19 致一較低之品質因素。 因此本發明提供了一種金氧半導體電容器的製造方 法，其可在一 CMOS元件’具有雙摻雜多晶矽閘極的製程 下進行。本發明方法包括提供一第一導電型的基底，於基 底中有第一型井區與第二型井區。一介電層形成於基底 上。具有第一導電型的第一多晶矽閘極，形成於第一型井 區。具有第二導電型的第二多晶矽閘極，形成於第二型井 區。具有第一導電型的第一摻雜區，形成於基底中，位於 第一多晶矽閘極兩側。具有第二導電型的第二摻雜區，形 成於基底中，位於第二多晶矽閘極兩側。一間隙壁形成於 第一多晶矽閘極與第二多晶矽閘極的側壁’其中部份介電 層也被移除，以暴露出部份的第一摻雜區及第二摻雜區。 進行一植入步驟，於暴露部份的第一摻雜區，再植入第一 導電型雜質，以形成第一基底電極。進行一植入步驟，於 暴露部份的第二摻雜區，再植入第二導電型雜質，以形成 第二基底電極。 另外，於第一多晶矽閘極與第二多晶矽閘極下方的通 道區可分別再植入與其所在井區’相同導電型的雜質，以 分別形成第一通道植入區（Channel Doped Region)與第二通 道植入區，如此降低電容的操作電壓。 10 587302 修正日期93.1.19 05799twfl.doc/006 利用上述方法，一金氧半導體電容器利用基底上之導 體層及基底中之摻雜區作爲電極’以及基底上之介電層作 爲電容器之介電層，並且，利用此一方法，M〇S電容之導 電型與基底相同，因此，在缺乏操作模式下，基底電極直 接與個別的通道植入區相連接，如此得到一較傳統之金氧 半導體電容器爲小之井電阻値(Well Resistance)。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖繪示出一傳統之金氧半導體電容器於Cm〇S 元件中的剖面結構； 第1B圖繪示出於第1A圖中，一傳統之N型金氧半 導體電容器的電容機制； 第1C圖繪示出一傳統的CMOS元件，具有PM0S元 件與NM0S元件，於不同導電型的井區，其中包括金屬矽 化層的功能； 第2圖繪示出一傳統的M0S電容元件； 第3圖繪示出對於傳統的M0S電晶體，其汲極電流 與汲極電壓的變化； 11 587302 05799twfl.doc/006 * 修正日期 93.1.19 第4A-4C圖繪示出依據本發明之一 MOS電容器之製 造流程； 第5圖繪示出依據本發明，於一 CMOS元件中，包括 雙摻雜結構之M0S電容器； 第6圖繪示出傳統之金氧半導體電容器及本發明中具 有反相導電型之電容器的電容-電壓特徵値之比較曲線；以 及 第7A-7B圖繪示本發明金氧半導體電容器剖面圖，及 其達成之電路與傳統之金氧半導體電容器之電路，以得到 第6圖的曲線。 圖式中標示之簡單說明： 100, 500 淡摻雜基底 104, 200 井區 106, 202 閘氧化層 108, 204 多晶矽層 110,210 金屬矽化層 112, 208 間矽壁 114, 206b 基底摻雜區 116, 206a 基底摻雜區延伸區 12 05799twfl .doc/006 修正曰期93.1.19 118, 120, 122, 124 電容― 實施例 本發明提供一種金氧半導體電容器的製造方法，在 CMOS製程中進型。其中此金氧半導體之導電型與其所形 成之區域相同，例如，在一 N井或N-型基底中形成一 NM0S 電容，或在一 P井或一 P-型基底中形成一 PM0S電容，詳 細的揭露如以下所敘。 第4A-4C圖繪示出依據本發明之一 M0S電容器之製 造流程剖面圖。參考第4A圖，提供一摻雜區域200，例如 是一基底或一井區，輕微的摻雜有一導電型的雜質，例如 是P型雜質或N型雜質。然後，在區域200上形成一介電 層 202。 形成一導電層204於介電層202上，例如，形成一多 晶矽閘極，又稱爲一閘極層204。介電層202例如是閘氧 化層。利用此閘極層204爲一罩幕層，對摻雜區域200進 行植入雜質，此一雜質的導電型與摻雜區域200相同。閘 極層204也可以摻雜相同導電型之雜質。於第4A圖中， 當定義閘極層204時，介電層202並未被一起定義。另一 種選擇，介電層202也可一起定義。若是摻雜區域200爲 587302 05799twfl.doc/006 · 修正日期 93.1.19 一 N型淡摻雜區域時，植入之雜質選擇N型雜質，相反的， 如果區域200爲一 P型滲摻雜區域，則植入之雜質則爲P 型。如此，則形成一基底摻雜區206a。通常，這些基底摻 雜區206a是用來作爲金氧半導體之源極或汲極的延伸區。 這特徵不同於傳統的方法。 在植入形成基底摻雜區206a之後，還會實施一些製 程，例如是熱製程，使得在基底摻雜區206a中的雜質得 以進一步擴散，結果，基底摻雜區206a之範圍得以擴大， 使得閘極層204、介電層202和基底摻雜區206a之間彼此 有一重疊部分。 _ 參考第46_圖，一間隙壁208形成於閘極層204的側 壁。其例如可先沉積一氧化層，再進行回蝕刻這氧化層與 介電層202。利用閘極層204及間隙壁208爲一罩幕層， 進行一植入步驟，以形成形成一摻雜區206b於基底，位 於閘極層204之兩側。於間隙壁208下的摻雜區206a爲一 摻雜延伸區。摻雜區206a與206b—起形成一基底電極206。 從製程觀點而言，這些摻雜區206a與206b類似於MOS 電晶體的源/汲區，及其延伸區，但是所摻雜的導電型不同。 本發明的金氧半導體電容器，可利用同樣相容的製程進行 製造，不需多餘的定義製程。本發明的重點，是在於安排 14 587302 05799twfl .doc/006 修正日期93.1.19 植入雜質的導電型，全部與_摻雜區域200的導電型相同。 而爲了使相關摻雜區的摻雜濃度提高，以將低缺乏電容效 應，用於其他電路植入的步驟，也可用來植入電容的摻雜 T品° 另外，一金屬矽化層210，例如鈦矽化層，也形成於 閘極層204之上。這金屬矽化層210的目之一如第1C圖 所示。 參考第4C圖，通常一金氧半導體電容也會包括一通 道摻雜區Pimp(Nimp)如虛線所繪示，位於閘氧化層202之下 方。通道摻雜區必須與摻雜區域200，具有相同導電型。 通道摻雜區可以降低電容的操電壓。 一般例如於閘極層204形成之前，於預定之通道區部 份，對基底進行通道調整植入。通道調整植入步驟也可以 與一般的起始電壓調整植入步驟一起進行。通道調整植入 步驟也可於導電層204形成之後，以較高之植入能量，將 需要之雜質植入於導電層204下之摻雜區域200。在此’ 植入通道之雜質具有與區域200相同的導電型。其雜質濃 度一般較高於區域200。 第4C圖中，植入雜質之通道區域如虛線所繪示。本 發明之主要特徵之一就是，於摻雜區域200上形成相同導 05799twfl.doc/006 修正日期93.1.19 電型之MOS電容元件。例如於P井區上形成PMOS，而并 區上形成NMOS，如此基底電極與源極/汲極可直接連接。 在缺乏模式操作時，因基底電極直接由源極/汲極連接，相 對於如第1A圖之傳統MOS電容，而形成較小的電阻値。 因此，可以得到較小的RC時間常數。其他類似之機制所 引起之過高電阻也可藉由本發明設計之機制降低。 如第4A圖至第4C圖所繪示之本發明所提供之方法， 不需要提供一般金氧半導體之製程之外，額外的製程步驟 或罩幕，僅將基底電極206摻雜與雜區域200相同之導電 型，而可以製造出較傳統金氧半導體電容器較小之串聯電 阻的電容器，而可以應用於高頻之電路或元件。 第5圖繪示了一種利用本發明所提供之方法所製造出 末的MOS電谷益於CMOS兀件中。如第5圖所繪示，一 個淡摻雜P-型基底500中包括了一個淡摻雜n井504a及 〜淡摻雜p井504b。在N井504a及P井504b中，各自形 成了一個NM0S電容502a及一個PM0IS電容502b。而在 NM0S電容502a及PM0S電容502b，其通道區分別摻雜 有N型雜質及P型雜質。基底電極522包括摻雜區514, 516。閘極520包括一閘極層508及金屬矽化層510。電容 的界電層爲閘極氧化層506。 587302 05799twn.doc/006 * 修正日期 93.1.19 本發明的MOS電容器可有效利用線性區。第6圖繪 示出傳統及本發明之金氧半導體的電容-電壓特性曲線的 比較。以一具有一厚約53至55埃(Angstrom)之閘氧化層 之NM0S電容而言，實心點線代表傳統之金氧半導體電容 器，依7A圖所示之電路測量得到，而空心點線代表本發 明之金氧半導體電容器如第7B圖所示之電路測量得到。 傳統M0S電容器的平面帶電壓約爲〇伏，同時當閘極電 壓增大時，其電容値不容易達到穩定的最大値。例如，於 閘極電壓等於2.5伏時，其電容値對於最大値比僅約爲 0.95，但是仍小於1。這是因爲缺乏電容現象造成的。 . 參考第5圖及第6圖，本發明操作MOS電容器是取 在閘極電壓大於零的部份，例如約〇-1伏。由於本發明的 M0S電容器是形成於同型的井區或基底上，功函數可有效 降低。平面帶電壓，如空心點線所示，也因此下降約1·〇5 伏。另外，當閘極電壓增大時，電容値可以較快趨於平穩 的最大値。在施加正電壓於NM0S電容器502a的閘極520 時，電容値有較佳的線性關係。這允許本發明能有效利用 於電容線性區，當閘極電壓設定爲大於零的偏壓。 於第5圖中的NM0S電容器502a，閘極520設定爲電 容的正電極，而基底電極522設定爲電容的負電極。類似 17 587302 05799twfl .doc/006 * 修正曰期 93.1 · 19 的，PMOS電容器502b的正電極爲基底電極522，而負電 極爲閘極520。 另外，本發明也可利用非線性區特性，其僅將電極極 性複換即可。非線性區在不同的電路設計可使用。同時本 發明M0S電容器也可應用於三井結構的元件。 上述中，電容器的半導體導電型是可以互換的，而本 發明特徵仍維持不變。 本發明之主要特徵可歸納爲，一金氧半導體電容器被 形成於一相同導電型之基底或井區。本發明更特別適用於 CMOS的製程下，具有不同導電型的井區。本發明的基底 電極的導電型與其所在的摻雜區同型，其寄生電阻可有效 降低，以增進電容器之品質，不受操作頻率及電壓之太大 影響。 本發明之金氧半導體電容器可以應用於多數的無線傳 送/接收器(Wireless Transceiver)中，電壓控制震盪器（Voltage Controller Oscillator, VC〇)之電波頻率（Radio Frequency，RF) 的頻率調整電路(Frequency Tuning Circuit)中。還可以應用 於廣泛使用於電視（TV)及頻率調節（Frequency Modulation， FM)電波接收器（Radio Receiver)之可調整電波瀘波器 (Tunable Radio Filter)中，以及一些在影音（Audio/Video)信 18 587302 05799twfl.doc/006 * 修正日期 93.1.19 號處理電路（Signal Processing Circuit)中，頻率靈敏 (Frequency Agile)之低通濾器(Low Pass Filter)中。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。587302 05799twfl .doc / 006 Modified date 93.1.19 玖, Description of the invention: The present invention relates to a method for manufacturing a metal-oxide-semiconductor (MOS) capacitor, and in particular, to a metal-oxide having the same conductivity type as the substrate Manufacturing method of semiconductor capacitor. In an integrated circuit (1C) having both digital and analog signals, for example, in an information & communication (Communication) device, the analog and digital signals pass through different semiconductor devices. Processing, because analog signal processing requires a high performance (High Performance) capacitor. Generally speaking, in an integrated circuit having a metal-oxide semiconductor, a metal-oxide semiconductor capacitor is mostly used to achieve the above purpose. The role of metal-oxide semiconductor capacitors in analog or hybrid operation modes is different from digital operation modes. Generally speaking, when a capacitor element is an integrated component in an integrated circuit, it needs an accurate capacitor. The capacitor element is usually manufactured through a special process. Semiconductor capacitor components are usually divided into polycrystalline silicon to polycrystalline silicon, metal to polycrystalline silicon, or metal to metal. Metal electrodes have no lack of capacitance. However, in the case of polycrystalline sand as the electrode, the polycrystalline sand itself may have a lack of capacitance. Therefore, polysilicon electrodes generally need to be doped with sufficient impurities to reduce the lack of capacitance. The lack of a capacitor will cause a change in the capacitance. These changes must be considered carefully in analog or mixed mode of operation. 4 587302 05799twfl.doc / 006 'Date of revision 93.1.19 For digital operation mode, the capacitive element is not the main part of the circuit, but the digital circuit may also require a capacitor element ’to achieve some special functions. At this time, the quality requirements of the capacitor element may not require the quality required in an analog circuit. The capacitor element can be formed by the original process, and no special process is required. A so-called metal-oxide semiconductor capacitor is common, which can be formed by a general similar metal-oxide semiconductor transistor process. In semiconductor manufacturing, complementary metal-oxide-semiconductor (CMOS) integrated circuits are generally known designs. A CMOS device generally includes many P-type transistors and N-type transistors. These transistors are usually formed in corresponding well regions on the same substrate. In particular, CMOS designed for dual wells includes well regions of different conductivity types, which are generally adjacent. This CMOS device requires not only a metal oxide semiconductor (MOS) transistor, but also a capacitor. This capacitor is typically achieved by a MOS capacitor, such as US Patent No. 5,703,806 and US Patent No. 5,168,075. However, this traditional MOS capacitor still has some disadvantages caused by the lack of effects of semiconductor materials, which will affect the performance of CMOS devices. In this way, to obtain a stable capacitor 値, it can only operate at low voltage. Traditional MOS capacitors are typically achieved using only the overlap between the source / drain region and the gate. This will also require extra masks and implantation steps. In addition, the M0S capacitor will also be used in a digital analog hybrid 5 587302 05799twfl.doc / 006 modified date 93.1.19 circuit, which requires a special process. In a traditional metal-oxide-semiconductor (MOS) capacitor, the source and the drain are short-circuited to each other as one of the capacitor's electrodes, the gate oxide layer is used as the dielectric layer of the capacitor, and the gate is the other electrode of the capacitor. . FIG. 1A illustrates an NMOS capacitor formed in a P-well and a PMOS capacitor formed in an N-well in a complementary metal-oxide-semiconductor (CMOS) integrated circuit. In FIG. 1A, a MOS transistor has a gate electrode, which includes a gate oxide layer 106, a polycrystalline silicon layer 108, and a metal silicide layer 110. A gap 112 is formed on the side wall of the gate electrode. A source / drain extension region 116 is formed under the spacer 112. A source / drain region 114 is also formed in the substrate 100 on both sides of the gate. Corresponding to different well regions 105, another MOS transistor is also formed. Traditional capacitors are like a MOS transistor, but they operate differently. For capacitor applications, a channel doped region can also be formed in the well region 104 under the gate oxide layer 106. The channel doped region reduces the operating voltage of the capacitor. Many different capacitors exist in the MOS capacitor in Figure 1A. For example, taking NMOS capacitors as an example, a variety of different capacitors are shown in Figure 1B. Due to the lack of type capacitor effect, a capacitor 118 exists at the interface between the gate oxide layer 106 and the polycrystalline silicon layer 108. Between the polycrystalline silicon layer 108 and the substrate well region 104, there is a capacitor 120, of which the gate oxide layer 106 6 587302 05799twn.doc / 006 · The revision date 93.1.19 is a dielectric layer. If the well region 104 is used as an electrode of a capacitor, a capacitor 122 also exists on the surface of the well region 104 below the gate oxide layer 106 due to the lack of type effect. If the source / drain region is used as an electrode of a capacitor, a capacitor 124 also exists between the polysilicon layer 108 and the source / drain region. In addition, there is also a metal silicide layer 110 on the top of the gate, which has some functions, as shown in Figure 1C. Figure 1C is a top view showing MOS devices in different well areas, for example, a P-type well area and an N-type well area are in close contact with each other. At this time, a diode is naturally formed on the interface. In order to prevent the diode from affecting the connection, the metal silicide layer 110 can be connected to different types of MOS gates. In the sectional view, as shown in FIG. 1A, the metal silicide layer 110 is formed on the top of the gate. ^ As shown in FIG. 2 for a gold-oxide semiconductor device, an oxide layer 0 and a metal layer M are sequentially formed on a semiconductor substrate S, such as a P-type silicon semiconductor substrate. When a gate voltage Vg is applied to the metal layer M, the MOS device acts like a capacitor. When the gate voltage Vg is negative, holes will accumulate on the surface of the semiconductor substrate S near the oxide layer 0. This situation is called an accumulation mode. When the gate voltage Vg is negative to a certain value, the capacitance has a fixed value. When the gate voltage Vg is positive, a strong inversion phenomenon begins to occur on the surface of the semiconductor substrate. The minimum voltage that produces a strong reversal phenomenon is called flat-band voltage (flat-band 7 587302 05799twfl.doc / 006 · Date of revision 93.1.19 voltage). The planar band voltage depends on the work function of the semiconductor substrate. When the gate voltage Vg is higher than the flat band voltage, but not high enough, at this time the hole starts to be driven away from the gate, leaving some negative electricity, which is called depletion mode. When the gate voltage Vg reaches the initial voltage of the MOS element, a strong inversion occurs completely on the substrate surface under the oxide layer. FIG. 3 shows a conventional MOS transistor, which corresponds to changes in the drain current Id and the drain voltage Vd corresponding to different starting voltages VT. When the gate voltage Vg is higher than the starting voltage VT to start the M0S transistor, when the drain voltage Vd is greater than a certain value, the drain current Id tends to be stable. When the drain voltage vd is in the initial stage, the drain current Id is in a linear characteristic. The linearity characteristic gives M0S transistor a variety of uses. This M0S capacitor can be operated in the following three modes: 1. When the gate bias (Gate Bias) is sufficient, that is, when the initial voltage of the transistor mode is higher than nm0S, the The interface between them, that is, near an inversion layer, will produce a two-degree space electron flow (Electron Gas). The electrons in the inversion layer are connected to the electrodes through the N + implanted source / drain region. In this operation mode, a high-quality fixed capacitor 値 can be obtained. 2. When the gate bias voltage is between the above-mentioned initial voltage and the plane voltage, the equivalent depth below the substrate is a dead zone. Therefore, a variable capacitor is formed. 8 05799twfl.doc / 006 Modification date 93.1.19 (Variable Capacitor ). Since the lightly doped P-type substrate is not connected to the electrode through a heavily doped N-type source / drain region, the electrode is connected at a considerable distance from the substrate, which results in a high series resistance. This operating mode is commonly referred to as the lack of operating mode. 3. When the gate bias voltage is lower than the flat band voltage, the holes accumulate under the gate electrode. Under this mode of operation, if you want to connect the well area through the P · base electrode, you will also suffer from a very high series resistance. Therefore, since the capacitance of the capacitor depends on the applied voltage, when it is applied to an analog circuit, the signal is easily distorted, which makes the practical application of metal-oxide semiconductor capacitors difficult. _ In addition, as mentioned above, in the absence mode of traditional metal-oxide semiconductor capacitors, because one of the electrodes is a substrate and the contact end of the substrate is beyond a considerable distance, the capacitor suffers from extremely high series resistance. These high The series resistance has the following effects: 1. The resistance-capacitance constant (RC Time Constant) of the metal oxide semiconductor capacitor and this parasitic resistor (Parasitic Resistor) produce a low-pass frequency response to limit the metal oxide Adaptable frequency range of semiconductor variable capacitor structure. 2. Even in the applicable frequency range of the metal oxide semiconductor variable capacitor structure, the high series resistance also generates a high signal power loss. Therefore, the derivative 9 587302 05799twfl.doc / 006 amends the date 93.1.19 to a lower value. Quality factor. Therefore, the present invention provides a method for manufacturing a metal-oxide semiconductor capacitor, which can be performed in a process in which a CMOS device 'has a dual-doped polycrystalline silicon gate. The method of the present invention includes providing a substrate of a first conductivity type, which has a first type well area and a second type well area in the substrate. A dielectric layer is formed on the substrate. A first polycrystalline silicon gate having a first conductivity type is formed in a first type well region. A second polycrystalline silicon gate having a second conductivity type is formed in the second type well region. A first doped region having a first conductivity type is formed in the substrate and is located on both sides of the first polycrystalline silicon gate. A second doped region having a second conductivity type is formed in the substrate and is located on both sides of the second polysilicon gate. A gap wall is formed on the sidewalls of the first polysilicon gate and the second polysilicon gate. Part of the dielectric layer is also removed to expose part of the first doped region and the second doped region. Area. An implantation step is performed, and a first conductive type impurity is implanted in the first doped region of the exposed portion to form a first substrate electrode. An implantation step is performed, and a second conductive type impurity is implanted in the second doped region of the exposed portion to form a second substrate electrode. In addition, the channel regions under the first polysilicon gate and the second polysilicon gate can be re-implanted with impurities of the same conductivity type as the well region where they are located, respectively, to form a first channel implanted region (Channel Doped). Region) and the second channel implanted region, thus reducing the operating voltage of the capacitor. 10 587302 Correction date 93.1.19 05799twfl.doc / 006 Using the above method, a metal oxide semiconductor capacitor uses a conductive layer on the substrate and a doped region in the substrate as electrodes' and a dielectric layer on the substrate as the capacitor's dielectric layer Moreover, with this method, the conductivity type of the MOS capacitor is the same as that of the substrate. Therefore, in the absence of an operation mode, the substrate electrode is directly connected to the individual channel implantation region, so that a more traditional metal-oxide semiconductor capacitor is obtained. It's Well Resistance. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A A cross-sectional structure of a conventional metal oxide semiconductor capacitor in a CMOS device is shown. FIG. 1B illustrates a capacitance mechanism of a conventional N-type metal oxide semiconductor capacitor in FIG. 1A. FIG. 1C shows A conventional CMOS device with PM0S and NM0S devices is used in well areas of different conductivity types, including the function of a metal silicide layer. Figure 2 shows a traditional M0S capacitor device. Figure 3 shows The change of the drain current and the drain voltage of the conventional M0S transistor; 11 587302 05799twfl.doc / 006 * Date of revision 93.1.19 Figures 4A-4C show the manufacturing process of a MOS capacitor according to the present invention; FIG. 5 illustrates a MOS device including a double-doped M0S capacitor in accordance with the present invention; FIG. 6 illustrates a conventional metal-oxide semiconductor capacitor and a capacitor having an inverse conductivity type in the present invention- Voltage Comparison curves Zhi; and 7A-7B of FIG MOS capacitor illustrates a cross-sectional view of the invention, and which is reached in the circuit and the circuit of a conventional MOS capacitor gold, 6 to give a graph of Fig. Brief description marked in the figure: 100, 500 lightly doped substrate 104, 200 well area 106, 202 gate oxide layer 108, 204 polycrystalline silicon layer 110, 210 metal silicide layer 112, 208 silicon walls 114, 206b base doped region 116, 206a Substrate Doped Region Extension Region 12 05799twfl .doc / 006 Modified Date 93.1.19 118, 120, 122, 124 Capacitance-Example The present invention provides a method for manufacturing a metal-oxide semiconductor capacitor, which is molded in a CMOS process. The conductivity type of the metal-oxide semiconductor is the same as the area formed by it, for example, a NMOS capacitor is formed in an N-well or N-type substrate, or a PM0S capacitor is formed in a P-well or a P-type substrate. The disclosure is as follows. 4A-4C are cross-sectional views showing a manufacturing process of a MOS capacitor according to one embodiment of the present invention. Referring to FIG. 4A, a doped region 200 is provided, such as a substrate or a well region, and is slightly doped with a conductive type impurity such as a P type impurity or an N type impurity. Then, a dielectric layer 202 is formed on the region 200. A conductive layer 204 is formed on the dielectric layer 202. For example, a polysilicon gate, also referred to as a gate layer 204, is formed. The dielectric layer 202 is, for example, a gate oxide layer. An impurity is implanted into the doped region 200 by using the gate layer 204 as a mask layer. The conductivity of the impurity is the same as that of the doped region 200. The gate layer 204 may be doped with impurities of the same conductivity type. In FIG. 4A, when the gate layer 204 is defined, the dielectric layer 202 is not defined together. Alternatively, the dielectric layer 202 may be defined together. If the doped region 200 is 587302 05799twfl.doc / 006 · Correction date 93.1.19 When an N-type lightly doped region, the implanted impurity is selected as an N-type impurity. Conversely, if the region 200 is a P-type doped region , The implanted impurities are P-type. In this way, a base doped region 206a is formed. Generally, these substrate doped regions 206a are used as extension regions of a source or a drain of a metal-oxide semiconductor. This feature is different from traditional methods. After the implantation of the base doped region 206a, some processes, such as a thermal process, are performed to further diffuse the impurities in the base doped region 206a. As a result, the range of the base doped region 206a is expanded, making the gate The electrode layer 204, the dielectric layer 202, and the base doped region 206a have an overlapping portion with each other. Referring to FIG. 46_, a spacer 208 is formed on a side wall of the gate layer 204. For example, an oxide layer can be deposited first, and then the oxide layer and the dielectric layer 202 can be etched back. Using the gate layer 204 and the spacer 208 as a cover layer, an implantation step is performed to form a doped region 206b on the substrate, on both sides of the gate layer 204. The doped region 206a under the spacer 208 is a doped extension region. The doped regions 206a and 206b together form a base electrode 206. From a process point of view, these doped regions 206a and 206b are similar to the source / drain regions of MOS transistors and their extension regions, but the conductivity types are different. The metal-oxide-semiconductor capacitor of the present invention can be manufactured by using the same compatible manufacturing process, and does not need to define a manufacturing process redundantly. The main point of the present invention is to arrange 14 587302 05799twfl.doc / 006 amendment date 93.1.19 The conductivity type of the implanted impurity is all the same as the conductivity type of the doped region 200. In order to increase the doping concentration of the relevant doped region to reduce the lack of capacitance effect, the step of implanting other circuits can also be used to implant the doped T product of the capacitor. In addition, a metal silicide layer 210, such as A titanium silicide layer is also formed on the gate layer 204. One of the purposes of the metal silicide layer 210 is shown in FIG. 1C. Referring to FIG. 4C, a metal-oxide-semiconductor capacitor generally includes a channel doped region Pimp (Nimp), which is located below the gate oxide layer 202 as shown by a dashed line. The channel doped region must have the same conductivity type as the doped region 200. The channel doped region can reduce the operating voltage of the capacitor. Generally, for example, before the formation of the gate layer 204, the substrate is subjected to channel adjustment implantation in a predetermined channel region portion. The channel adjustment implantation step can also be performed together with a general starting voltage adjustment implantation step. The channel adjustment implantation step may also implant the required impurities into the doped region 200 under the conductive layer 204 with a higher implantation energy after the conductive layer 204 is formed. Here, the impurities of the implantation channel have the same conductivity type as the region 200. Its impurity concentration is generally higher than the region 200. In FIG. 4C, the channel region where the impurity is implanted is shown as a dotted line. One of the main features of the present invention is that the same conductance is formed on the doped region 200. 05799twfl.doc / 006 Modified date 93.1.19 Electrical type MOS capacitor element. For example, PMOS is formed on the P-well region, and NMOS is formed on the parallel region, so that the base electrode can be directly connected to the source / drain. In the absence of mode operation, the base electrode is directly connected by the source / drain, which results in a smaller resistance compared to the conventional MOS capacitor as shown in Figure 1A. Therefore, a smaller RC time constant can be obtained. The excessive resistance caused by other similar mechanisms can also be reduced by the mechanism designed by the present invention. As shown in FIG. 4A to FIG. 4C, the method provided by the present invention does not need to provide a general metal oxide semiconductor process, additional process steps or masks, and only the base electrode 206 is doped with the impurity region 200. The same conductivity type can be used to manufacture capacitors with less series resistance than traditional metal-oxide semiconductor capacitors, and can be applied to high-frequency circuits or components. FIG. 5 shows that a MOS power valley manufactured by the method provided by the present invention is beneficial to a CMOS element. As shown in FIG. 5, a lightly doped P-type substrate 500 includes a lightly doped n-well 504a and a lightly doped p-well 504b. In the N-well 504a and the P-well 504b, an NMOS capacitor 502a and a PM0IS capacitor 502b are formed, respectively. In the NM0S capacitor 502a and the PM0S capacitor 502b, the channel regions are doped with N-type impurities and P-type impurities, respectively. The base electrode 522 includes doped regions 514, 516. The gate electrode 520 includes a gate layer 508 and a metal silicide layer 510. The boundary layer of the capacitor is a gate oxide layer 506. 587302 05799twn.doc / 006 * Revision date 93.1.19 The MOS capacitor of the present invention can effectively utilize the linear region. Fig. 6 shows a comparison of the capacitance-voltage characteristic curves of the conventional and the metal-oxide semiconductors of the present invention. For a NM0S capacitor with a gate oxide layer with a thickness of about 53 to 55 angstroms (Angstrom), the solid dotted line represents a traditional metal oxide semiconductor capacitor, which is measured according to the circuit shown in Figure 7A, and the hollow dotted line represents The invented metal-oxide semiconductor capacitor was measured by the circuit shown in FIG. 7B. The conventional M0S capacitor has a flat band voltage of about 0 volts. At the same time, when the gate voltage increases, its capacitance 値 does not easily reach a stable maximum 値. For example, when the gate voltage is equal to 2.5 volts, the capacitance ratio to the maximum ratio is only about 0.95, but it is still less than one. This is due to the lack of capacitance. Referring to Fig. 5 and Fig. 6, the operation of the MOS capacitor according to the present invention is taken at a portion where the gate voltage is greater than zero, for example, about 0-1 volts. Since the MOS capacitor of the present invention is formed on the same well area or substrate, the work function can be effectively reduced. The voltage on the plane, as indicated by the dotted line, also drops by about 1.05 volts. In addition, when the gate voltage increases, the capacitance 値 can quickly reach a stable maximum 値. When a positive voltage is applied to the gate 520 of the NMOS capacitor 502a, the capacitance 値 has a better linear relationship. This allows the present invention to be effectively used in the capacitor linear region when the gate voltage is set to a bias greater than zero. In the NMOS capacitor 502a in FIG. 5, the gate electrode 520 is set as the positive electrode of the capacitor, and the base electrode 522 is set as the negative electrode of the capacitor. Similar to 17 587302 05799twfl.doc / 006 * The date 93.1 · 19 is amended, the positive electrode of the PMOS capacitor 502b is the base electrode 522, and the negative electrode is the gate electrode 520. In addition, the present invention can also take advantage of the characteristics of the non-linear region, which only needs to re-polarize the electrodes. The non-linear region can be used in different circuit designs. At the same time, the MOS capacitor of the present invention can also be applied to components of the Mitsui structure. In the foregoing, the semiconductor conductivity type of the capacitor is interchangeable, while the features of the present invention remain unchanged. The main feature of the present invention can be summarized as that a metal-oxide semiconductor capacitor is formed on a substrate or a well region of the same conductivity type. The present invention is more particularly applicable to well regions with different conductivity types in a CMOS process. The conductivity type of the base electrode of the present invention is the same as that of the doped region in which it is located, and its parasitic resistance can be effectively reduced to improve the quality of the capacitor without being affected by the operating frequency and voltage. The metal-oxide semiconductor capacitor of the present invention can be used in most wireless transmitters / receivers (Wireless Transceivers). Tuning Circuit). It can also be used in Tunable Radio Filter widely used in TV (TV) and Frequency Modulation (FM) Radio Receiver, and some in Audio / Video Letter 18 587302 05799twfl.doc / 006 * Date of revision 93.1.19 Signal Processing Circuit, Frequency Agile Low Pass Filter. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
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