1241681 f , W3〇2twf.doc/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於 一種晶圓絕緣層内連線之製造方法與結構。 【先前技術】 積體電路(integrated circuit)工業基本上是由積體電路 設計、晶圓製造、晶圓測試與晶圓封裝四大主幹體系所組 成之高科技產業。一般積體電路在製造完成之後，都必須 ，過一連串的測試，以確保所生產之晶片的品質，甚至可 稭由這些測試的結果以修正積體電路的製程。而且，於晶 圓▲製造完成之後，通常都會進行許多的晶圓測試。若經過 測試發現晶圓上之線路出現瑕疲或不符合要求時，通常會 drcuit) ? =樣的運作， :可省略重作光罩以及其他方面的成本， 並了以大大地提昇晶圓之良率。 T .在198 8年’英代爾公司的研究人1241681 f, W3022twf.doc / c IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor process, and in particular, to a method and a structure for manufacturing wafer interconnects. [Previous technology] The integrated circuit industry is basically a high-tech industry consisting of four main systems: integrated circuit design, wafer manufacturing, wafer testing, and wafer packaging. Generally, after the integrated circuit is manufactured, it must pass a series of tests to ensure the quality of the produced wafer, and even the results of these tests can be used to modify the integrated circuit manufacturing process. Furthermore, many wafer tests are usually performed after the wafer is completed. If the circuit on the wafer is found to be flawed or does not meet the requirements after testing, it will usually be drucuit) = = the same operation, the cost of re-working the mask and other aspects can be omitted, and the wafer can be greatly improved. Yield. T. In 1988, a researcher at Indale Corporation
一種被稱為聚焦離子束一 H MB)的裝置，以於一塊486微虛 遺漏的電路’且經測試後此：二言了了-段 利用聚焦離子束修補線路的運作’因此開啟了 補晶圓上之線路*現贼或不符人丄:係以此種技術以修 用聚焦離子束技術修補線路仍有的部分’然而，使 束的農置是相當昂貴的機^ ’因絲焦離子 補晶圓上她較長輯 =彻«、離子束技術修 稱，會使得製程上需耗費較高 12416§3—/c 的成本。另外，利用聚焦離子束技術進行線路修補的動作 係一費時的步驟，同樣的，若用以修補相距較長距離的 路時，更是需要耗費許多時間才得以完成之。& 、^ 【發明内容】 有鑑於此，本發明的目的就是在提供—種晶圓絕 層内連線之製造方法，能夠修補晶圓上的線路，且可解夺 習知線路修補技術耗時且高成本的問題。 〜 尽i明的乃口 π疋從识一禋晶圓絕緣層内連線 結構，能夠避免晶圓上因出現瑕庇或不符合 政 而影響晶圓之良率的問題。 八]踝路時 本發明提出一種晶圓絕緣層内連線之製 方法係先提供一晶圓，晶圓上已报&右夕万法，此 綠u ρ热 日日圓上已形成有多數條導線，且邕 線上係覆蓋有絕緣層。然後，在 v 兩條導線。接乂 蓋住絕緣芦以及…囫形成遮幕，共形的覆 勺同&、、象θ及上述之兩標記圖案。之後，至少移险兩挪 出2上以及兩標記圖案之間的以義^ 出兩標記圖案以及絕緣層 成溝木以暴路 層，覆蓋住被暴露出的^ 於遮幕上形成第二導電 遮幕，亚同時剝除遮幕 曰之後移 依照本發明的較佳每〕弟一蛉電層。 氣化矽。此外，於晶圓上 =，上述之遮幕的材質包括 衾佈法。另外，上、乂成氧化矽遮幕的方法包括旋轉 才对嗤或石夕膠。，、、幕的材貝亦包括二氧化鈦、醋酸 I2416§32twfdoc/c 、々…、本發明的較佳實施例，上述至少移除兩標記圖 ^上以及兩標記圖案之間的遮幕以形成溝渠之步驟包括係 =遮幕上切割出一區域，再剝除區域内之遮幕。另外， 上述於遮幕上切割出區域之方法包括聚焦離子束技術或是 雷射技術。 依…、本發明的較佳實施例，上述第一導電層的材質 包括鎢、銷、金、銅、銘或是其組合。 ^依照本發明的較佳實施例，上述於絕緣層中形成孔 洞的方法包括聚焦離子束技術或是雷射技術。 、兩依照本發明的較佳實施例，上述於孔洞中填入第一 導電層的方法包括使用聚焦離子束。 依照本發明的較佳實施例，上述第二導電層的材質 包括鎢、鉑、金、銅、鋁或是其組合。 依照本發明的較佳實施例，上述第二導電層的形成 方法包括利用一濺鍵(Sputter)法或是一電鍵法。 依照本發明的較佳實施例，上述絕緣層係一保護層。 ^ 依照本發明的較佳實施例，上述絕緣層的材質包括 氮化;5夕或氧化石夕。 本發明又提出一種晶圓絕緣層内連線之結構，此結 構係由晶圓、絕緣層、二記圖案與導體層所組成。其中晶 圓上具有多數條導線。另外，上述之絕緣層配置於晶圓表 面並覆蓋住上述之導線，其中絕緣層中係形成有兩孔洞， 以暴露出其中二導線。其中，二標記圖案配置於孔洞内並 與二導線電性接觸，且二標記圖案之上表面係高於絕緣層 I2416§Xvfdoc/c 3二3記以:層至少覆蓋在二標記圖案之 連接。 系之間的絕緣層上，以使二導線電性 由上述可知，本發 法並非使用聚焦離子束來絕緣相連線之製造方 此利用本發明的方法$=、、、邑緣層令的内連線結構。因 線路的修補，較習知: 與成本。另外，利用 ：=技術-大幅的μ時間 補，可大幅節省時間 此^丁_：曰曰圓上的線路修 顯易懂=下々顯击上述和其他目的、特徵和優點能更明 佳實施例’並配合所附圖式，作詳細 【實施方式】 二般於晶圓上進行線路修補所進行之技術為聚焦離 〇cus 1〇n beam ’ FIB)技術’但聚焦離子束技術用於 修補線路所需的時間較長且成本較高。特別是，如圖i所 不，當晶圓100上相距較長距離的線路(如導線1〇2與 線104的距離106相距約超過數百微米（um))需進行修 動作時，習知的聚焦離子束技術會耗費相當多的時間且 本會過高。 圖2A至圖2F係繪示本發明較佳實施例之晶圓絕緣 層内連線之製造方法的流程上視圖。圖3A至圖3F為八 別繪示圖2A至圖2F中沿Ι-Γ線之剖面圖。 ·'、'乃 1241683 14382twf.doc/c 曰。首先，請同時參照圖2A與圖3A，先提供_晶圓3⑽， 300上已形成有數條導線302，且數條導線302上係 覆蓋f絕緣層304。其中，絕緣層3〇4的材質例如是氮化 f或氧化矽，形成方法例如是化學氣相沈積法(CVD)。在 一實施例中，此絕緣層3〇4亦可當做是晶圓的保護層，其 將可以保護下方的基底300及數條導線3〇2，避免因為^ 來雜質及機械性的傷害而造成損傷。 /、接著，請同時參照圖2B與圖3B，於絕緣層3〇4中 形成兩孔洞306a與306b，以分別暴露出兩條導線3〇2a 與3〇2b。其中，於絕緣層304中形成兩孔洞306a與306b 的方法例如是聚焦離子束技術或是雷射技術。 、之後，請同時參照圖2C與圖3C，於孔洞306a與孔 洞306b =填入一導電層，以形成兩標記圖案3〇%與 308b。接著，於晶圓3()()上形成遮幕31()，共形的覆蓋住 絕緣層304以及兩標記圖案3〇%與3〇肋。其中，上述之 導電層（即標記圖案308a與3〇8b)的材質例如是鎢、鉑、 金、銅、銘或疋其組合，形成導電層之方法例如是使用聚 焦離子束技術。在-實施例中，遮幕31G的材質例如是氧 化石夕，而其形成方法例如是旋轉塗佈法。在另—實施例中， 遮幕31㈣材質例如是二氧化鈦、醋酸_旨或石夕膠，其形 ，方法例如疋直接將二氧化鈦、醋酸樹自旨餅膠膜放置於 曰曰圓300上以覆蓋住絕緣層3()4以及標記圖案遍&、3〇8b 即可。 繼之’請同時參照圖2D與®犯，至少移除兩標記 1241683 14382twf.doc/c 圖案308a與308b上以及兩標記圖案3〇8a與3〇8b之間的 遮幕310以形成溝渠312，其係暴露出兩標記圖案 與308b以及位於兩標記圖案3〇8a與3〇肋之間的絕緣層 304。其中，上述形成溝渠312之步驟例如是先於遮幕31〇 上切割出一區域314，且此區域314至少包括兩標記圖案 308a與308b所在之區域以及兩標記圖案3〇8a與3〇肋之 間的區域，然後再剝除區域314内之遮幕31〇。在一實施 例中，於遮幕310上切割出區域314之方法例如是使用聚 焦離子束技術或是雷射技術。在另一實施例中，倘若遮幕 310的材質為二氧化鈦、醋酸樹酯或矽膠，則於遮幕31〇 上切割出區域314之方法可利用刀具在遮幕31〇上進行切 割的動作。 之後，請同時參照圖2E與圖3E，於遮幕310上形 成導電層316,覆蓋住被暴露出的兩標記圖案308a與308b 以及絕緣層304。其中，導電層316的材質例如是鎢、鉑、 金、銅、鋁或是其組合，形成方法例如是利用濺鍍(sputter) 法或是電鍍法。 之後，請同時參照圖2F與圖3F，移除遮幕31()，並 同時剝除遮幕310上方的導電層316。如此一來，導線3〇2a 與302b即可以透過留下來的導電層316以及標記圖案 308a與308b而電性連接，以完成晶圓絕緣層内連線之製 值得注意的是，本發明係可特別應用於晶圓上線路 的修補。其中，利用本發明以修補晶圓上的線路的方法為 !241683 l4382twf.d〇c/c 將待修補的線路視為圖2B與圖3B中之導線3〇2&與 3〇2b，然後再進行本發明之晶圓絕緣層内連線之製程，形 成内連線結構(例如是標記圖案3〇8a與3〇8b)以及導體層 316，即可使待修補的線路能夠電性連接，而達到線路修 補的目的。 、 夕 以上是說明本發明之晶圓絕緣層内連線之製造方 法’接著說明本發明之晶圓絕緣層内連線之結構。 請參照圖3F，本發明之晶圓修補後之結構係由晶圓 3〇〇、絕緣層304、二標記圖案30^與308|3以及導體層316 所組成。其中晶圓300上具有數條導線3〇2。另外，曰上述 之絕緣層304係配置於晶圓300表面並覆蓋住上述之數條 導線302，其中絕緣層304中係形成有兩孔洞3〇6&與 306b’以暴露出其中二導線3〇2a與302b。二標記圖案3〇2a 與302b配置於二孔洞3〇如與3〇6b内並與二導線3〇%與 302b電性接觸，且二標記圖案308a與308b之上表面係 高於絕緣層304之上表面。其中，上述之導體層316至少 覆蓋在二標記圖案308a與308b之表面上以及二標記圖案 308a與308b之間的絕緣層304上，以使二導線3〇2a與302b 電性連接。 ' 由上述可知，本發明係於二導線302a與302b上分 別形成標記二圖案308a與308b，且其係與二導線302a 與302b電性接觸。之後再於二標記圖案308a與308b上 形成導電層316，以使二導線302a與302b能藉由導電層 316與二標記圖案308a與308b而電性連接。若將二導線 I2416§3?2twfdoc/c 302a與遍替換成待修補的線路，則本發明亦可庫用於 二曰^線路的修補，以使待修補的線路能夠達到紐連接 可;崎相料之製造方法亦 了應用於U線路，^本發明並非使用聚焦離子束來 絕緣層中的内連線結構(即標記圖案鳩與雇），因此 解決f知使用聚焦離子束之方式來修補線路會 有兩成本與耗時的缺點。另外，本發明之晶圓絕緣層内連 線之製造綠亦可提高晶圓之產“及對於祕之修補有 較高的成功率。特別是，本發明應驗修補相距超過數百 微米之二導線間之線料’除了可達到修獅路的目的 外’於節省時間與成本方面較習知技術有更大的功效。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 、 【圖式簡單說明】 圖1係繪示晶圓上具有待修補之二導線的上視示意 圖0 圖2A至圖2F係繪示本發明較佳實施例之晶圓絕緣 層内連線之製造方法的流程上視圖。s 圖3A至圖3F為分別繪示圖2A至圖2F中沿1_1，線 之剖面圖。 【主要元件符號說明】 12 1241683 14382twf.doc/c 100、300 ··晶圓 102、104、302、302a、302b :導線 106 :距離 304 :絕緣層 306a、306b :孔洞 308a、308b :標記圖案 310 :遮幕 312 :溝渠 314 :區域 316 :導電層A device called Focused Ion Beam (H MB) is based on a 486 micro-missing circuit, and after testing, it is said: the operation of the segment-focused ion beam repairing circuit is used. The line on the circle * is a thief or inconsistent: this technique is used to repair the part of the line using the focused ion beam technology. 'However, making the farming of the beam is a very expensive machine. Her longer series on the wafer = complete «, ion beam technology modification, will make the process need to consume a higher cost of 12416§3-/ c. In addition, the use of focused ion beam technology for line repair is a time-consuming step. Similarly, if it is used to repair a long distance road, it takes a lot of time to complete it. &, ^ [Summary of the Invention] In view of this, the object of the present invention is to provide a method for manufacturing a wafer insulation interconnect, which can repair the circuits on the wafer, and can eliminate the consumption of conventional circuit repair technology. Timely and costly issues. The best way to understand is to understand the interconnect structure of the wafer insulation layer, which can avoid problems that affect the yield of the wafer due to defects or non-compliance on the wafer. Eight] When the ankle is used, the present invention proposes a method for manufacturing wafer interconnects. First, a wafer is provided. The wafer has been reported on the wafer, and the green u ρ hot Japanese yen has formed a majority. Wires, and the wires are covered with an insulating layer. Then, two wires at v. Then cover the insulating reed and ... 囫 to form a curtain. The conformal covering spoon is the same as & After that, remove at least two of the two symbols and the meaning between the two mark patterns. ^ Draw out the two mark patterns and the insulation layer to form a trench layer to cover the exposed ^ and form a second conductive on the screen. The curtain is simultaneously stripped, and the curtain is moved in accordance with the preferred embodiment of the present invention. Vaporized silicon. In addition, on the wafer =, the material of the above-mentioned mask includes a cloth method. In addition, the method of forming and shading the silicon oxide curtain includes rotating the face to face or the stone glue. The material of the curtain also includes titanium dioxide, acetic acid I2416§32twfdoc / c, 々 ..., a preferred embodiment of the present invention, the above mentioned at least removing the mask on the two mark diagrams ^ and between the two mark patterns to form a trench The steps include cutting an area on the curtain, and then stripping the curtain in the area. In addition, the above-mentioned method for cutting out the area on the mask includes a focused ion beam technique or a laser technique. According to a preferred embodiment of the present invention, a material of the first conductive layer includes tungsten, a pin, gold, copper, an inscription, or a combination thereof. ^ According to a preferred embodiment of the present invention, the method for forming a hole in the insulating layer includes a focused ion beam technique or a laser technique. According to a preferred embodiment of the present invention, the method of filling a first conductive layer in a hole described above includes using a focused ion beam. According to a preferred embodiment of the present invention, the material of the second conductive layer includes tungsten, platinum, gold, copper, aluminum, or a combination thereof. According to a preferred embodiment of the present invention, the method for forming the second conductive layer includes using a sputter method or an electric bond method. According to a preferred embodiment of the present invention, the insulating layer is a protective layer. ^ According to a preferred embodiment of the present invention, the material of the above-mentioned insulating layer includes nitride; The present invention also proposes a structure for interconnecting the wafer insulation layer. The structure is composed of a wafer, an insulation layer, two patterns and a conductor layer. There are many wires on the crystal circle. In addition, the above-mentioned insulation layer is disposed on the surface of the wafer and covers the above-mentioned wires, wherein two holes are formed in the insulation layer to expose two of the wires. Among them, the two-marker pattern is disposed in the hole and is in electrical contact with the two wires, and the upper surface of the two-marker pattern is higher than the insulating layer I2416§Xvfdoc / c 32: 3: The layer covers at least the connection of the two-marker pattern. It can be seen from the above that the electrical properties of the two wires are electrically insulated from each other. This method does not use a focused ion beam to insulate the connected wires. Therefore, the method of the present invention is used. Interconnection structure. Because of the repair of the line, it is more familiar: and cost. In addition, using: = Technology-a large μ time complement, can save a lot of time. ^ Ding :: The line on the circle is easy to understand. The following and other purposes, features and advantages can be better implemented. Example 'and in accordance with the attached drawings, detailed [Implementation] The technology generally used to perform circuit repair on wafers is focused off-cuso 10n beam' FIB) technology 'but focused ion beam technology is used for repair The line takes longer and costs more. In particular, as shown in Figure i, when a long distance line on the wafer 100 (such as the distance 106 between the wire 102 and the line 104 is more than several hundred micrometers (um)) is required to perform a repair operation, it is known that The focused ion beam technology takes a considerable amount of time and would be too high. FIG. 2A to FIG. 2F are top views showing a flow of a method for manufacturing an interconnection of a wafer insulating layer according to a preferred embodiment of the present invention. 3A to 3F are cross-sectional views taken along line I-Γ in FIGS. 2A to 2F. · ',' Are 1241683 14382twf.doc / c. First, please refer to FIG. 2A and FIG. 3A at the same time. First, a wafer 提供 is provided. A plurality of wires 302 have been formed on 300, and the plurality of wires 302 are covered with an f insulation layer 304. The material of the insulating layer 304 is, for example, nitride f or silicon oxide, and the formation method is, for example, chemical vapor deposition (CVD). In an embodiment, the insulating layer 304 can also be used as a protective layer for the wafer, which can protect the underlying substrate 300 and the plurality of wires 300, avoiding damage caused by impurities and mechanical damage. damage. /. Next, please refer to FIG. 2B and FIG. 3B at the same time, and form two holes 306a and 306b in the insulating layer 304 to expose the two wires 302a and 302b, respectively. The method for forming the two holes 306a and 306b in the insulating layer 304 is, for example, focused ion beam technology or laser technology. After that, please refer to FIG. 2C and FIG. 3C at the same time. Fill a hole in the hole 306a and the hole 306b with a conductive layer to form two marking patterns 30% and 308b. Next, a mask 31 () is formed on the wafer 3 () () to conformally cover the insulating layer 304 and the two mark patterns 30% and 30 ribs. The material of the conductive layer (ie, the marking patterns 308a and 30b) is, for example, a combination of tungsten, platinum, gold, copper, indium, or rhenium. The method of forming the conductive layer is, for example, using a focused ion beam technology. In the embodiment, the material of the mask 31G is, for example, oxidized stone, and the formation method thereof is, for example, a spin coating method. In another embodiment, the material of the mask 31 is, for example, titanium dioxide, acetic acid, or stone gum, and its shape. For example, the method is to directly place a film of titanium dioxide and acetic acid tree cake on a circle 300 to cover it. The insulating layer 3 () 4 and the mark pattern may be all over & Followed by 'Please refer to FIG. 2D and ® at the same time, remove at least two markers 1241683 14382twf.doc / c the mask 310 on the patterns 308a and 308b and between the two marker patterns 308a and 308b to form a trench 312, It exposes two marking patterns and 308b and an insulating layer 304 between the two marking patterns 308a and 30 ribs. The above-mentioned step of forming the trench 312 is, for example, cutting an area 314 on the mask 31o, and this area 314 includes at least the area where the two marking patterns 308a and 308b are located and the two marking patterns 308a and 30b. Area, and then the mask 31 within area 314 is stripped. In one embodiment, the method of cutting the region 314 on the mask 310 is, for example, using a focused ion beam technique or a laser technique. In another embodiment, if the material of the mask 310 is titanium dioxide, acetate, or silicone, the method of cutting the area 314 on the mask 31 may use a cutter to perform a cutting operation on the mask 31. After that, please refer to FIG. 2E and FIG. 3E at the same time. A conductive layer 316 is formed on the mask 310 to cover the exposed two marking patterns 308a and 308b and the insulating layer 304. The material of the conductive layer 316 is, for example, tungsten, platinum, gold, copper, aluminum, or a combination thereof, and the formation method is, for example, a sputtering method or a plating method. After that, please refer to FIG. 2F and FIG. 3F at the same time, remove the mask 31 (), and simultaneously strip the conductive layer 316 above the mask 310. In this way, the wires 3202a and 302b can be electrically connected through the remaining conductive layer 316 and the mark patterns 308a and 308b to complete the interconnection of the wafer insulation layer. It is worth noting that the present invention can It is especially suitable for repairing lines on wafers. Among them, the method for repairing the circuit on the wafer by using the present invention is! 241683 l4382twf.d0c / c. The circuit to be repaired is regarded as the wires 3 2 & 3 2b in FIG. 2B and 3B, and then The process of interconnecting the wafer insulation layer of the present invention is performed to form an interconnect structure (for example, marking patterns 308a and 308b) and a conductor layer 316, so that the circuit to be repaired can be electrically connected, and To achieve the purpose of line repair. The above is the method for manufacturing the interconnections of the wafer insulation layer of the present invention. 'Next, the structure of the interconnections of the wafer insulation layer of the present invention is explained. Referring to FIG. 3F, the repaired structure of the wafer of the present invention is composed of wafer 300, insulating layer 304, two mark patterns 30 ^ and 308 | 3, and conductor layer 316. The wafer 300 has a plurality of wires 300. In addition, the above-mentioned insulation layer 304 is disposed on the surface of the wafer 300 and covers the above-mentioned several wires 302. Among the insulation layers 304, two holes 3006 and 306b 'are formed to expose two of the wires 3. 2a and 302b. The two marking patterns 302a and 302b are arranged in the two holes 30, such as in the 306b and in electrical contact with the two wires 30% and 302b, and the upper surface of the two marking patterns 308a and 308b is higher than that of the insulating layer 304. On the surface. The above-mentioned conductor layer 316 covers at least the surfaces of the two marking patterns 308a and 308b and the insulating layer 304 between the two marking patterns 308a and 308b, so that the two wires 302a and 302b are electrically connected. As can be seen from the above, the present invention is to form two marking patterns 308a and 308b on the two wires 302a and 302b, respectively, and it is in electrical contact with the two wires 302a and 302b. Then, a conductive layer 316 is formed on the two marking patterns 308a and 308b, so that the two wires 302a and 302b can be electrically connected through the conductive layer 316 and the two marking patterns 308a and 308b. If the two-conductor I2416§3? 2twfdoc / c 302a is replaced with the line to be repaired, the present invention can also be used to repair the two-line circuit, so that the line to be repaired can reach a new connection. The manufacturing method of the material is also applied to the U line. The present invention does not use a focused ion beam to insulate the interconnect structure in the insulating layer (ie, mark the pattern and dovetail), so the solution is to use the focused ion beam to repair the line. There are two disadvantages of cost and time. In addition, the green manufacturing of the interconnects of the wafer insulation layer of the present invention can also improve the yield of the wafer "and has a higher success rate for the repair of the secret. In particular, the present invention has been proven to repair two wires with a distance of more than several hundred microns. The timeline material "except for the purpose of repairing lion road" is more effective than the conventional technology in terms of saving time and cost. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Invention, anyone skilled in this art can make some changes and retouch without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. Brief description of the drawings] FIG. 1 is a schematic top view showing two wires to be repaired on a wafer. 0 FIGS. 2A to 2F are diagrams illustrating a method for manufacturing an interconnect of a wafer insulating layer according to a preferred embodiment of the present invention. Top view of the process. S Figures 3A to 3F are cross-sectional views taken along line 1_1 in Figures 2A to 2F, respectively. [Description of main component symbols] 12 1241683 14382twf.doc / c 100, 300 ·· Wafer 102, 104, 302, 302a, 302b: Line 106: distance 304: insulating layer 306a, 306b: holes 308a, 308b: marking pattern 310: cover screen 312: a trench 314: 316 Region: conductive layer
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