TWI240962B - Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions - Google Patents

Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions Download PDF

Info

Publication number
TWI240962B
TWI240962B TW93126919A TW93126919A TWI240962B TW I240962 B TWI240962 B TW I240962B TW 93126919 A TW93126919 A TW 93126919A TW 93126919 A TW93126919 A TW 93126919A TW I240962 B TWI240962 B TW I240962B
Authority
TW
Taiwan
Prior art keywords
semiconductor transistor
item
scope
patent application
implantation
Prior art date
Application number
TW93126919A
Other languages
Chinese (zh)
Other versions
TW200610037A (en
Inventor
Yun-Ren Wang
Ying-Wei Yen
Shu-Yen Chan
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW93126919A priority Critical patent/TWI240962B/en
Application granted granted Critical
Publication of TWI240962B publication Critical patent/TWI240962B/en
Publication of TW200610037A publication Critical patent/TW200610037A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions is provided. A silicon substrate having thereon a poly gate structure is prepared. The poly gate structure has sidewalls and a top surface. An offset spacer is formed on its sidewall. An ion implantation process is carried out to form an ultra-shallow junction doping region in the silicon substrate next to the offset spacer. An oxide liner is deposited on the offset spacer and on the top surface of the poly gate structure. A tensile nitride spacer layer is then deposited on the oxide liner. A stress modification implantation process is performed to turn the tensile nitride spacer layer into a more compressive status. A dry etching process is then carried out to etch the nitride spacer layer so as to form a spacer.

Description

1240962 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體製程，尤指一種可以抑制缺陷引發的 (defect-induced)瞬間增益擴散(transient enhanced diffusion TED)效 應的半導體製程方法。本發明特別適合應用於具備超淺接面之汲 極/源極延伸區域的電晶體元件的製作過程。 【先前技術】 隨著半導體1C元件推進至次微米或奈米等級以下之微細化尺 寸，積體電路中的M0S電晶體元件須製作成具有超淺接面⑽ra shallow junct㈣之汲極/源極延伸⑽職/办血加咖㈣區域之結 構，以克服元件尺寸縮小所伴隨產生如短通道效應(sh〇rtch雲】 effect)等問題。然而，形成超淺接面之汲極/源極延伸區域的問題 在於其接©城，則MQS電晶體元件的片微越大，如此將導致 兀件操作蚪的飽和電流(saturati〇n cu腦t)不足。這個現象在麗^ 電晶體元件上越顯得嚴重。 般超义接面之汲極/源極延伸區域的製作係以低能量離子佈 ^進入錄底的絲面。在縮小元件尺寸同時，祕，汲極與通 则雜原子/讀必須提高，接面深度減小及摻雜原子濃度分佈 各重^有縣的交化，因此掌握摻雜元素擴散的行為便顯得相 性的与鄕不過石夕曰曰内換雜^素的擴散受到許多製程參數與材質特 、〜曰’例如缺陷引發的瞬間增益擴散(transient enh anced 1240962 diffusion，TED)效應必須設法減小。 因此，目前該技術領域確實需要一種可 =r擴一法，可避免超淺::== 域的摻雜輪廓因擴散而產生改變。 【發明内容】 可以有效抑制前述 本發明之主要目的在提供一種半導體製程， 缺陷引發的瞬間增益擴散效應。 本《明之另-主要目的在提供一種具備超淺接面之沒極/源極 延伸區域的電晶體元件㈣方法，可避免贼接崎極/源極延伸 區域的摻雜輪廓因瞬間增益擴散效應而產生改變。 根據本發明讀佳實關，本發明提供—種具峨接面汲極/ 源極延伸半導體電晶體元件的製作方法，包含有··提供一基底； 於4基底上形成一閘極結構，其包含有兩側壁以及一上表面；於 該閘極結構之側壁上形成偏側壁子；進行第一離子佈植製程，於 該閘極結構兩側之該基底形成第一摻雜區域；於該閘極結構之偏 側壁子上以及其上表面沈積一襯墊層；於該襯墊層上沈積一側壁 子層；進行一應力修正佈植製程，改變該側壁子層之應力狀態由 伸張狀悲(tensile)改變至較為壓縮(compressive)之狀態；以及進行 一乾蝕刻製程，將該側壁子層蝕刻成側壁子。 1240962 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文特 舉-較佳實施例，並配合所關式，作詳細說明如下。 【實施方式】 明茶閱第1圖至第3圖’其!會示的是根據本發明較佳實施例製· 作具備超雜面线極/源觀輕域18的pMQs電晶體元件⑽. t剖面示意圖。如第！圖所示’在N型基底1〇上以絕緣結構，如 淺溝絕緣(shallow trench —η，STI)結構，定義出主動區域12〇。_ N型基底10如N型石夕基底。在主動區域12〇上形成有多晶石夕問極 結構12。多晶石夕閘極結構12與基底1〇之間有閘極介電層14，例 如二氧化矽等。 在多晶石夕閘極結構12的侧壁上形成有偏侧壁子(〇ffset spaCer)16。偏侧壁子16可以由二氧化矽所構成。在形成偏側壁子 16之後，利用離子佈植製程，在多晶石夕閘極結構I]兩側的基底 修 10内植入P型摻質，例如硼離子，形成超淺接面的p型摻雜區域 18。根據本發明之較佳實施例，p型摻雜區域18的接面深度約為 30埃以内。 隨後’以化學氣相沈積方法或者以爐管，在多晶矽閘極結構12 、 上以及在P型摻雜區域18上沈積二氧化矽襯墊層22。二氧化矽襯 墊層 22 可以是以 BTBAS (bis(tertiarybutylamine)silane)為前驅物 8 1240962 (precursor)與氧氣所產生的二氧化石夕。 接著’於二氧化石夕襯墊層22上沈積氮化石夕侧壁子層24。氮化 矽侧壁子層24 積可以採帛姆餘沈積⑽师㈣,/ (position，CVD)製程。根據本發明之較佳實施例，氮化秒側壁子 層24的厚度約為_至700埃。氮化石夕侧壁子層％此時的^力: 仍為伸張狀態(tensile)。 如第2圖所示，接著對氮化矽側壁子層24進行一應力修正 鲁 (stress modification)佈植製程30，以電性為中性的重摻質，例如鍺 (germanium)或氙(xenon)等，以佈植能量在25至15〇KeV之間劑 量在2E14至5E15at〇ms/Cm2之間的條件下，將原先應力為伸張狀 態(tensile)的氮化石夕側壁子層24改變成較為壓縮(c〇mpressive)之狀 態。根據本發明之較佳實施例，應力修正佈植製程3〇的投射範圍 (projected range，Rp)其值應小於氮化矽側壁子層24的厚度，以厚 度700埃為例，RP較佳介於350至7〇〇埃之間。第4圖係以表列鲁 分別利用鍺以及氤進行佈植製程3〇之較佳化條件。 如第3圖所示，接著進行一乾姓刻製程，將氮化石夕侧壁子層24 名虫刻成在多晶梦閘極結構12側壁上的側壁子34。隨後再進行離子 ' 佈植製程，將P型摻質植入多晶矽閘極結構12兩側的基底1〇内，' 形成PM0S電晶體元件1〇〇的汲極/源極區域48。 9 1240962 第5圖以表列利用錯(Ge)為應力修正佈植製程的接質，在不 同的摻雜條件下所可以改變的氮化石夕側壁子層24應力值以及超淺 接面的P型掺雜區域18的片電阻㈣。如第5圖所示，當錯(Ge) 的佈植能量it _Kev，魅在則atGmsw的條件下，氮僻 . 侧壁子層24應力值由原先的U9E10 dyne/cm2 (tensile)降至 心7E9 dyne/cm2 (compressive)，而超淺接面的p型摻雜區域i8的 片電阻(Rs)由4634ohm/sq大幅降低至1787〇hm/sq。 相較於習知技藝，由於本發明以應力修正佈植製程3〇改變氮 · 化石夕侧壁子層24的應力值，使其由原先的伸張狀態㈣此)改變成 較為壓縮(compressive)之狀態，藉此降低矽表面的空隙缺陷 (defect)，由此可使植入石夕基底10的硼摻質擴散程度降低，避免超 淺接面汲極/源極延伸區域的摻雜輪廓因瞬間增益擴散效應而產生 改變，因此可以達到降低超淺接面的P型摻雜區域18的片電阻並 且獲得較淺的接面深度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖繪示的是根據本發明較佳實施例製作具備超淺 ' 接面之汲極/源極延伸區域的PMOS電晶體元件的剖面示意圖。 第4圖以表列分別利用鍺以及氙進行佈植製程之較佳化條件。 ⑽962 的摻雜終 =m_Ge則力修蝴·糊《，在不同 的p、斤可以改、交的氮化梦側壁子層應力值以及超淺接面 、型摻雜區域的片電阻(RS)。 【主要元件符號說明】 1〇基底 14 閘極介電層 18 p型摻雜區域 24 氮化矽側壁子層 34 側壁子 100 PMOS電晶體元件 12 多晶石夕閘極結構 16 偏侧壁子 22 二氧化石夕襯塾層 30 應力修正佈植製程 48 汲極/源極區域 120 主動區域1240962 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor process, and more particularly to a semiconductor process method capable of suppressing a defect-induced transient enhanced diffusion TED effect. The invention is particularly suitable for the manufacturing process of a transistor element having a drain / source extension region with an ultra-shallow junction. [Previous technology] As semiconductor 1C devices advance to submicron or nanometer-sized miniaturized sizes, M0S transistor devices in integrated circuits must be made with a shallow / junction drain / source extension Unemployment / blood plus coffee area structure to overcome problems such as short channel effect (shortch cloud effect) accompanying the reduction in component size. However, the problem of forming the drain / source extension region of the super shallow junction is that it is connected to the circuit, and the chip of the MQS transistor element is slightly larger, which will cause the saturation current of the element to operate. t) insufficient. This phenomenon becomes more serious on Li transistor devices. The production of the drain / source extension area of the general supersense interface is made by using a low-energy ion cloth to enter the silk surface of the recording bottom. While reducing the size of the element, the secretion, the drain and the general heteroatom / read must be increased, the junction depth is reduced, and the dopant atom concentration distribution is different. There are cross-country crossovers, so mastering the diffusion behavior of dopant elements appears to be consistent However, Shi Xiyue ’s diffusion of internal impurities is affected by many process parameters and material characteristics. For example, transient enh anced 1240962 diffusion (TED) effect caused by defects must be managed to reduce. Therefore, at present, the technical field really needs a method that can be expanded by r, which can avoid the change of the doping profile of the super shallow ::: = domain due to diffusion. [Summary of the Invention] The main objective of the present invention is to effectively suppress the transient gain diffusion effect caused by defects caused by a semiconductor process. The main purpose of this article is to provide a transistor device with an ultra-shallow junction / source extension region, which can avoid the effect of instantaneous gain diffusion on the doping profile of the junction / source extension region. Make a difference. According to the present invention, the present invention provides a method for manufacturing a semiconductor transistor element with an E-junction drain / source extension, including: providing a substrate; and forming a gate structure on 4 substrates. Comprising two side walls and an upper surface; forming side walls on the side walls of the gate structure; performing a first ion implantation process to form a first doped region on the substrate on both sides of the gate structure; A pad layer is deposited on the side wall of the polar structure and on the upper surface thereof; a side wall sub layer is deposited on the pad layer; a stress correction implantation process is performed to change the stress state of the side wall sub layer from a stretched state ( tensile) to a more compressed state; and performing a dry etching process to etch the sidewall sub-layer into a sidewall. 1240962 In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiment in combination with related formulas in detail as follows. [Embodiment] Mingcha read Figure 1 to Figure 3 'its! Will be shown in accordance with the preferred embodiment of the present invention to make · pMQs transistor with super-heteroline line pole / source view light domain 18 ⑽. Schematic t section. As the first! As shown in the figure, the active region 12 is defined by an insulating structure on the N-type substrate 10, such as a shallow trench insulation (STI) structure. _ The N-type substrate 10 is an N-type Shixi substrate. A polycrystalline stone interrogation structure 12 is formed on the active region 120. There is a gate dielectric layer 14 between the polycrystalline silicon gate structure 12 and the substrate 10, such as silicon dioxide. A sidewall spacer 16 is formed on the sidewall of the polycrystalline stone gate structure 12. The side wall 16 may be made of silicon dioxide. After the partial sidewalls 16 are formed, P-type dopants, such as boron ions, are implanted into the substrate 10 on both sides of the polycrystalline stone gate structure I] using an ion implantation process to form a p-type super shallow junction. Doped region 18. According to a preferred embodiment of the present invention, the junction depth of the p-type doped region 18 is within about 30 angstroms. Subsequently, a silicon dioxide liner layer 22 is deposited on the polycrystalline silicon gate structure 12 and on the P-type doped region 18 by a chemical vapor deposition method or a furnace tube. The silicon dioxide lining cushion layer 22 may be a bismuth dioxide produced by using BTBAS (bis (tertiarybutylamine) silane) as a precursor 8 1240962 (precursor) and oxygen. Next, a nitride stone sidewall sub-layer 24 is deposited on the stone dioxide gasket layer 22. The silicon nitride sidewall sub-layers can be deposited by a deposition method (position, CVD). According to a preferred embodiment of the present invention, the thickness of the nitrided second sidewall sub-layer 24 is about ˜700 Å. Nitrile stone side wall sublayer% force at this time: still in a stretched state (tensile). As shown in FIG. 2, a stress modification implantation process 30 is performed on the silicon nitride sidewall sub-layer 24, and a heavy neutral dopant such as germanium or xenon ), Etc., under the condition that the implantation energy is between 25 and 150 KeV and the dose is between 2E14 and 5E15 at 0 ms / Cm2, the nitrided nitride sidewall sub-layer 24 originally changed to a tensile state is changed to Compressed. According to a preferred embodiment of the present invention, the projected range (Rp) of the stress correction implantation process 30 should be smaller than the thickness of the silicon nitride sidewall sub-layer 24. Taking the thickness of 700 angstroms as an example, RP is preferably between Between 350 and 700 Angstroms. Figure 4 shows the optimal conditions for the implantation process 30 using germanium and thallium, respectively, in the form of tablelu. As shown in FIG. 3, a dry last engraving process is then performed to engraving 24 worms on the side walls of the nitrided stone side wall into side walls 34 on the side wall of the polycrystalline gate structure 12. Subsequently, an ion implantation process is performed, and a P-type dopant is implanted into the substrate 10 on both sides of the polycrystalline silicon gate structure 12 to form a drain / source region 48 of the PMOS transistor element 100. 9 1240962 Fig. 5 shows the table in Table 5 using stress (Ge) as the stress to modify the bonding process of the implantation process. Under different doping conditions, the stress value of the nitrided nitride sublayer 24 and the P of the super shallow junction can be changed. The sheet resistance of the type doped region 18 is chirped. As shown in Figure 5, when the implantation energy of it (Ge) is it_Kev, the charm is at Gmsw, and the nitrogen is isolated. The stress value of the side wall sublayer 24 is reduced from the original U9E10 dyne / cm2 (tensile) to the heart. 7E9 dyne / cm2 (compressive), and the sheet resistance (Rs) of the p-type doped region i8 of the super shallow junction was greatly reduced from 4634ohm / sq to 1787hm / sq. Compared with the conventional technique, the present invention changes the stress value of the nitrogen · fossil evening wall sublayer 24 by the stress correction process 30, so that it changes from the original stretched state to a more compressed one. State, thereby reducing void defects on the silicon surface, thereby reducing the degree of diffusion of boron dopants implanted into the substrate 10, and avoiding the doping profile of the drain / source extension region of the super shallow junction due to transient The gain diffusion effect causes a change, so that it is possible to reduce the sheet resistance of the P-type doped region 18 of the super shallow junction and obtain a shallower junction depth. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention. [Brief description of the drawings] FIGS. 1 to 3 are schematic cross-sectional diagrams of manufacturing a PMOS transistor device having a drain / source extension region with an ultra shallow junction according to a preferred embodiment of the present invention. Figure 4 lists the optimized conditions for the implantation process using germanium and xenon, respectively. The doping end of ⑽962 = m_Ge Zelixiu. "The stress value of the nitrided nitride sidewall sublayer can be changed at different p, jin, and the sheet resistance (RS) of the super shallow junction and type doped regions. . [Description of main component symbols] 10 base 14 gate dielectric layer 18 p-type doped region 24 silicon nitride sidewall sublayer 34 sidewall 100 PMOS transistor 12 polycrystalline silicon gate structure 16 partial sidewall 22 Stone dioxide lining 30 Stress correction process 48 Drain / source region 120 Active region

Claims (1)

1240962 案號：0931269191240962 Case number: 093126919 、申請專利範圍： η >-ν t ?- η β ι^ η 修正 種具超淺接祕働雜延伸半 法，包含有： 提供一基底； 於該基底上形成-閘極結構’其包含有兩侧壁以及—上表面； 於該閘極結構之侧壁上形成偏側壁子； 進订離子佈植製程’於該閘極結構兩側之該基底形成淺接面 摻雜區域；Scope of patent application: η > -ν t?-Η β ι ^ η Modified species with super shallow doping extension method, including: providing a substrate; forming a gate structure on the substrate, which includes There are two side walls and an upper surface; side walls are formed on the side walls of the gate structure; an ion implantation process is performed to form shallow junction doped regions on the substrate on both sides of the gate structure; 於該閘極結構之偏_子上以及其上表面沈積—襯㈣； 於該襯墊層上沈積一侧壁子層； ^卜應力修正佈㈣程，改_㈣子層之應力狀態由伸張 狀態(tensile)改變至較為壓縮(c〇mpressive)之狀態；以及 進订-祕雌程，職繼子層侧成侧壁子。Deposition-lining on the bias electrode of the gate structure and its upper surface; depositing a sidewall sub-layer on the liner layer; ^ stress correction layout process to change the stress state of the sub-layer by extension The state of tension is changed to a more compressed state; and the order-secret female process, the step-child sub-layers become side walls. 2.如申晴專利範圍第丨項所述之具超淺接硫極/雜延伸半導 體電晶體元件㈣作方法，其中該基絲錄底。 φ .如申明專利fe圍第i項所述之具超淺接面沒極/源極延伸半導 體電晶體it件的製作方法，其中該閘極結構為多晶砍閑極。 4.如申凊專利範圍第j項所述之具超淺接面沒極/源極延伸半導· 體電晶體το件的製作方法，其巾制極結構與該基底之間設有問 極介電層。 12 1240962 案號:093126919 94年7月12日修正 5·如申請專利範圍第1項所述之具超淺接面汲極/源極延伸半導 體電晶體元件的製作方法，其中該側壁子層為氮化矽所構成。 6·如申請專利範圍第丨項所述之具超淺接面汲極/源極延伸半導 體電晶體元件的製作方法，其中該應力修正佈植製程的植入摻質 為鍺(germanium)或氙(xenon)。 7. 如申請專利範圍第1項所述之具超淺接面汲極/源極延伸半導 體電晶體元件的製作方法，其中該應力修正佈植製㈣植入能量 約介於25至150KeV之間。 8. 如申請專利範圍f !項所述之具超淺接面酿/源極延伸半導 體電晶體元件賴作方法，其巾簡力修正佈植製㈣植入換質 為錯，植入能量約lOOKeV，劑量約在5E15at〇ms/cm2。 9. 如申請專利範圍帛i項所述之具超淺接面沒極/源極延伸半導 體電晶體磁的製作方法，其中該淺接面摻雜區域為？型換雜區 域。 10· —種半導體電晶體元件的製作方法，包含有： 提供一矽基底； 於該石夕基底上形成一閘極結構，其包含有兩侧壁以及一上表 1240962 舛年7月12曰修正 案號：093126919 於該間極結構之繼上軸偏側壁子； 一進行第-料舰製程，於關滅構_之該雜底形成第 -摻雜區域’作為該半導體電晶體树的汲樹源極延伸，· 於該間極結構之偏側壁子上、其上表面，以及該第一換雜區域 上形成一襯墊層； 於該襯墊層上沈積一側壁子層； 、Jt订-應力修正佈植製程，改變該罐子層之應力狀態由伸張 狀怨(tensile)改變至較為壓縮(c〇mp聰㈣之狀態； 進行-乾蝴縣，職繼子層⑽成侧壁子 ;以及 進仃第二離子雜製程，於細壁子_彳之财基絲成第二 摻雜區域，作為該半導體電晶體元件岐極/源極。 U·如申料利範圍第1G項所述之半導體電晶體元件的製作方 \ 1 /，其中該應力修正佈植製程的植入摻質為電性中性之摻質物種。 12.如申請專利範圍第10項所述之半導體電晶體元件的製作方 去’其中該應力修正佈植製程的植入能量約介於25至150Kev之 間。 13·如申請專利範圍第10項所述之半導體電晶體元件的製作方 法’其中該應力修正佈植製程的植入摻質為鍺，植入能量約 WOlCeV ’ 劑量約在 5E15atoms/cm2。 14 1240962 案號：卿⑽丨9 94年7月丨2日修正 14. 如申請專利範圍第1〇項所述之半導體電晶體元件的製作方 法，其中該應力修正佈植製程具有一投射範圍其值小於該側壁子 層之厚度。 15. 如申請專利範圍第14項所述之半導體電晶體元件的製作方 法’其中該侧壁子層之厚度約為6〇〇至7〇〇埃。 16·如申請專利範圍第1〇項所述之半導體電晶體元件的製作方 法，其中該側壁子層為氮化矽所構成。 17·如申請專利範圍第1 〇項所述之半導體電晶體元件的製作方 法，其中該閘極結構與該石夕基底之間設有閘極介電層。 I8·如申請專利範圍帛10項所述之半導體電晶體元件的製作方 法，其中该應力修正佈植製程可以降低該石夕基底的空隙缺陷。 十一、圖式： 12409622. The operation method of the ultra-shallow sulphide / hetero-extended semiconductor transistor element described in item 丨 of Shen Qing's patent scope, wherein the base wire is recorded at the bottom. φ. The method for manufacturing an it device with an ultra shallow junction electrode / source extension semiconductor transistor as described in item i of the patent claim, wherein the gate structure is a polycrystalline chip. 4. The method for manufacturing an ultra-shallow electrodeless / source-extended semiconducting and bulk transistor το as described in item j of the patent scope of the patent, with an interrogation electrode provided between the towel electrode structure and the substrate. Dielectric layer. 12 1240962 Case No .: 093126919 Amended on July 12, 1994 5. The method for manufacturing a semiconductor transistor element with an ultra shallow junction drain / source extension as described in item 1 of the scope of patent application, wherein the sidewall sublayer is Made of silicon nitride. 6. The method for manufacturing a semiconductor transistor device with an ultra shallow junction drain / source extension as described in item 丨 of the patent application scope, wherein the implantation dopant of the stress correction implantation process is germanium or xenon (xenon). 7. The method for fabricating a semiconductor transistor element with an ultra shallow junction drain / source extension as described in item 1 of the scope of the patent application, wherein the stress correction cloth is implanted and the implantation energy is between about 25 and 150 KeV. . 8. As described in the patent application scope f !, the method for the operation of the semiconductor device with super shallow junction / source extension semiconductor transistor has a simple force to correct the implantation, the implantation quality is wrong, and the implantation energy is about 10OKeV, the dose is about 5E15at 0ms / cm2. 9. The method for fabricating the super-shallow junctionless / source-extended semiconductor transistor magnetism described in item (i) of the scope of patent application, wherein the doped region of the shallow junction is? Pattern change area. 10 · A method for fabricating a semiconductor transistor device, comprising: providing a silicon substrate; forming a gate structure on the stone substrate, which includes two side walls and a table 1240962 as amended on July 12, 2014 Case No .: 093126919 On the pole structure following the upper shaft off-side wall; once the first-material carrier process is performed, the first doped region is formed on the hetero bottom of the passivation structure as the drain of the semiconductor transistor tree Source extension, forming a cushion layer on the side wall of the interphase structure, its upper surface, and the first doping region; depositing a side wall sub-layer on the cushion layer; The stress correction and implantation process changes the stress state of the tank layer from a tension to a more compressed state; proceeding-Qianhu County, the step sub-layers are formed into side walls; and仃 Second ionic hybrid process, forming a second doped region on the thin-walled substrate of 彳 彳 彳, as the semiconductor transistor element's divergence / source. U · Semiconductor as described in item 1G Fabricator of transistor element \ 1 /, where the stress is corrected The implantation dopant of the implantation process is an electrically neutral dopant species. 12. The fabrication method of the semiconductor transistor device described in item 10 of the scope of the patent application, wherein the stress modifies the implantation energy of the implantation process. Approximately between 25 and 150 Kev. 13. The method for fabricating a semiconductor transistor device as described in item 10 of the patent application scope, wherein the implantation dopant of the stress correction implantation process is germanium and the implantation energy is about WOlCeV. The dose is about 5E15atoms / cm2. 14 1240962 Case No .: Qing ⑽ 丨 9 July 1994 丨 2 amended 14. The method for fabricating a semiconductor transistor device as described in item 10 of the patent application scope, wherein the stress correction cloth The implantation process has a projection range whose value is smaller than the thickness of the side wall sub-layer. 15. The method for manufacturing a semiconductor transistor device described in item 14 of the scope of patent application, wherein the thickness of the side wall sub-layer is about 600 to 70 angstroms. 16. The method for manufacturing a semiconductor transistor device as described in item 10 of the scope of the patent application, wherein the side wall sublayer is composed of silicon nitride. 17. As described in the scope of the patent application Semiconducting A method for fabricating a transistor element, wherein a gate dielectric layer is provided between the gate structure and the Shi Xi substrate. I8. The method for fabricating a semiconductor transistor element according to the scope of application for patent 10 items, wherein the stress Correction of the implantation process can reduce the void defect of the Shixi substrate. 片電阻(ohm/sq) 4634 3969 1787 接面深度(nm) eg 應力值(dyne/cm2) 1.19E10 6.581E09 -2.27E09 CM p c 1 /-s \ r\ in ε llJ 1—H LLJ i 1 H 5E li ο % _ 藏 ω s δ » Λ LO CNJ s O o o 〇Sheet resistance (ohm / sq) 4634 3969 1787 Junction depth (nm) eg Stress value (dyne / cm2) 1.19E10 6.581E09 -2.27E09 CM pc 1 / -s \ r \ in ε llJ 1—H LLJ i 1 H 5E li ο% _ Tibetan ω s δ »Λ LO CNJ s O oo 〇
TW93126919A 2004-09-06 2004-09-06 Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions TWI240962B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW93126919A TWI240962B (en) 2004-09-06 2004-09-06 Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW93126919A TWI240962B (en) 2004-09-06 2004-09-06 Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions

Publications (2)

Publication Number Publication Date
TWI240962B true TWI240962B (en) 2005-10-01
TW200610037A TW200610037A (en) 2006-03-16

Family

ID=37013000

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93126919A TWI240962B (en) 2004-09-06 2004-09-06 Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions

Country Status (1)

Country Link
TW (1) TWI240962B (en)

Also Published As

Publication number Publication date
TW200610037A (en) 2006-03-16

Similar Documents

Publication Publication Date Title
JP5173582B2 (en) Semiconductor device
CN100585834C (en) Ic and its manufacturing method
JP2012004473A (en) Semiconductor device and method for manufacturing semiconductor device
JP2014041974A (en) Semiconductor device and method of manufacturing the same
JP2007251066A (en) Method of manufacturing semiconductor device
US20060189066A1 (en) Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
US20060001105A1 (en) Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
US20070287258A1 (en) A method of manufacturing gate sidewalls that avoids recessing
TWI818928B (en) Method for fabricating semiconductor device
JP2003078137A (en) Method for forming elevated source/drain areas using polysilicon spacer
JP2012069964A (en) Structure and method for selective deposition of germanium spacers on nitride
TW574746B (en) Method for manufacturing MOSFET with recessed channel
US20060014350A1 (en) Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions
JP4005055B2 (en) Semiconductor device and manufacturing method thereof
KR101131418B1 (en) Semiconductor device and method of manufacturing the same
TWI240962B (en) Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions
CN106158639B (en) The forming method of semiconductor devices
US8039330B2 (en) Method for manufacturing semiconductor device
KR100690910B1 (en) Salicide process and the method of fabricating a semiconductor device using the same
KR100400253B1 (en) Method for forming the thin film transistor of semiconductor device
TW201318032A (en) Semiconductor device and method of forming epitaxial layer
KR100613355B1 (en) MOSFET and method of fabricating the MOSFET
US8362530B2 (en) Semiconductor device including MISFET and its manufacture method
CN100388440C (en) Manufacturing method of semiconductor transistor element with supershallow connection surface drain/source expansion
JP5341122B2 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees