1237229 13528twf.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於〜 一種利用儲能元件中和 之潮汐現象。 【先前技術】 種電荷中和電路 電荷的電路装置 ，且特別是有關於 ，解決液晶顯示器 顯影在程中/主要製程包括上光阻、曝光、 扩隸般ϊ奋X寻過程。其中上光阻的步驟由於主要以 卩衫泠&Α 土光阻，谷易造成玻璃基板中間 =佈的光阻較周圍所塗佈的光阻薄；另一方面，在姓 驟時，玻璃基板的中間區域作Back ch職1麵叩 雪曰：弋刻速度比周圍區域來的快，造成完成後的薄膜 制曰曰-0、通逼關漏電流較低。軸此種玻璃基板在切割 衣面板組裝成她後，係以晝素電容存取影像資料，然 而在電源關閉時的通道關閉漏電流依不同區分佈而不同， 放=的速j自然也不同。因此，座落於玻璃基板中間區域 的1素電容在電源關閉時需要較長的時間釋放電荷。 參考圖1所繪示，係於玻璃基板上以薄膜電晶體製程 生產的液晶面板示意圖，包括液晶面板1〇〇，其中以分割 成四個區域的右上角畫素區1〇2為例，一封閉不規則曲線 110 4曰示通道關閉漏電流較低與較高的分際。在電源關閉 時，由於110包圍的區域需要較長的時間釋放電荷，意即 影像自對應的晝素消退的時間較長，對使用者而言，會看 到殘留的晝面如潮汐般消退，以102區塊為例，消退的方 1237229 13528twf.doc 向係圖1中的箭頭方向所示。 薄膜！ 1卜髀：t夜晶顯示器用途的薄膜電晶體製程’造成 相差。所對應的導通電流(Icm)與關閉漏電流(i〇ff) 導Ϊ二的5次方到6次方倍，例如電晶體_壓在 極^ =日為24V，則—約為A數量級，而電晶體閘 赵^在關閉狀態時為-6V’則關閉漏電流Ioff約為pA 夕夏級:在顯示器電源關閉的同時，由於Ioff較Ion小很 =、、，所明於高解析度面板而言，更容易觀察到影像殘留 /月沙現象，更詳細的說，當關上電源瞬間因薄膜電晶體膜 同造成電容不同，所需的放電時間也不相同，因此液 曰^旋轉回復的咖亦不同，故在面板上出現如海潮退潮般 殘影晝面。此時薄膜電晶體本身也切換至關閉狀態，在晝 素電容中的電荷只能藉漏電流經由資料掃描線放電，然而 由上所述可知I〇ff是pA數量級，放電速度對於使用者的 肉眼來說，就出現明顯的不均勻消退的殘留影像，意即潮 汐現象。此現象非純粹將Ioff電流提高就可改善，因為 在製程上將薄膜電晶體本身規格Ioff提高的結果，會造 成其它影像特性變差，例如出現顫動現象(flicker)。因此 針對薄臈電晶體的潮汐現象’需要在電路設計上求改善。 麥考第2A圖，係繪示習知技術中於電源關閉時將電 晶體閘極電壓加速拉至地源電位GND的電路200，其中 利用儲能元件，在電源關閉同時使閘極電壓逐漸拉到GND 電位的電壓趨勢快速地拉到GND。由第2B圖及2C圖可 分別看出電路改良前後閘極電位回歸地源準位在響應上的 1237229 13528twf.doc 至別：然而，以這樣的機制僅適用於薄膜電晶 := = =到_準位;若是薄膜電晶體開 啟电£無法有效¥通薄膜電晶體的_，則齡現象仍缺 存在。因此’需要-财效整合電路，使得閘極電壓在電 源關閉時仍足夠將畫素上的電荷有效地相互中和，決 液晶面板的潮汐現象問題。 / ' 【發明内容】 綜上所述，本發明的一目的在於提供一種電荷中和控 ^電路’適用於-液晶顯示面板，在不需變更面板成膜製 私的條件下’ >肖除因賴電晶體在關閉時無法提供有效的 放電路徑而造成的潮汐現象。 ^本發明的又一目的在於提供一種電荷中和控制電路， 係，合於液晶面板所具有的特定應用積體電路(asic)，控 制，膜電晶體導通的時間點，以及所有液晶面板上的薄膜 電，體閘極全開之時機’使液晶面板在關機後有足夠高的 電晶體啟動準位’有效將晝素上的電荷中和，以消除潮沙 現象。 曰根據本發明提供的電荷中和控制電路，適用於消除液 晶顯示面板的潮汐現象，係利用内建於特定應用積體電路 Sic)的—個訊號開關訊號偵測單元(signai—〇ff detect〇r) 來偵/則控制訊號的狀態。當該訊號開關偵測單元偵測不到 一主控制單元的輸出訊號時，表示系統處於關閉狀態，此 時一間極全開訊號(A11_gate_on)為低致能準位，而將液晶 1237229 13528twf.doc 所有的薄膜電晶體之閘極全數導通， :液曰曰，存電容積存的電量經由薄膜 ^由迴路 出，與晝素中的儲存電容及其它儲能元件的;=圣端釋 ::的特定應用積體電路(ASIC)中，該電荷 匕括況麵測元件以及—閘極延遲單元，其中 測單兀耦接至—主要…孔麵 要乜制mk供兩個低準位致 f其中一個疋電源致能職DCJDC.ENA，㈣ 輸入，的切換裝置處將輸人電壓關掉，以及域至Vgh ，遲單元，使VGH在關掉電源之前有延遲時間，以維持 薄膜電晶體㈣極打騎需的臨界電壓。其餘例如類比電 壓源、電晶體關閉電壓、以及共同電壓等其它電源部分， 則設定在DC一DC.ENA訊號送出的同時關閉。該訊號偵 測單元另外送出一個閘極全數開啟(Aii-gate_on)訊號使得 所有薄膜電晶體的閘極打開，並決定此動作時間點，經由 閘極延遲單元來控制在DC—DC.ENA產生時刻的—特定 時間間隔之後開始動作。 一般在液晶面板的系統中，正常的關機程序依下列順 序依次關閉電源：背光模組、訊號提供模組、以及電源模 組。根據本發明之關機電源時序，係以下方所述的順序操 作。當DCJDC.ENA動作後，類比電壓源VDDA、閘極 掃描線電壓VEEG以及共同電壓Vcom等均要先關俥， 其電壓均隨時間遞減至零電位GND。另一方面，為了讓 薄膜電晶體的閘極全數開啟，必須將VGH關閉時延後， 1237229 13528twf.doc 使知有足夠咼的電壓準位使閘極打開。而Vgh與 DC〜DC.ENA動作後的時間差由VGH延遲單元調整。閘 極全數開啟的時機必須在VDDA遞減至GND之後，才強 ^所有的的閘極打開，藉由電晶體源極側的路徑迅速達到 電荷中和；閘極全數開啟的時機最晚必須在VGH電壓達 到能打開電晶體的閘極的最小電壓之前。 练上所述，本發明中的電荷中和控制電路可整合至液 晶面板的特定應用積體電路(ASIC)模組上，以解決潮汐現 ^的問題，運用特定應用積體電路(ASIC)内部電路配合外 部電路達成，因此可以減少印刷繞線板上元件的使用數， 達到降低成本的效果，以及精簡印刷繞線板的佈局設計。 根據本發明中的電荷中和電路，控制VGH打開時機，以 及閘極全開的時機，使得面板關機指令下達後有足夠的 準位讓賴電晶體保㈣啟，有效將畫素上的電荷 量中和掉，以解決潮沙問題。另外，由於薄膜電晶體的成 膜製程等原因造成面板上各區域分布的電晶體特性不同而 引起之潮汐現象，在不變更製程的條件下，利用 明即 能改善。 為瓖本發明之上述和其他目的、特徵、和優點能更明 ”、、員易Ιϊ ’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 【實施方式】 請參照圖4 ’其綠示依照本發明一較佳實施例的電荷 中和電路裝置示意圖，係適祕消除液晶顯示面板系統 1237229 13528twf.doc 400的潮汐現象，利用内建於特定應用積體電路(asic)4i〇 二中一個訊號開關偵測單元(signal—〇ff detect〇r)4丨4來偵測 訊號的狀態。當該訊號開關偵測單元414偵測不到一主控 =單兀412訊號時，表示液晶面板系統處於關閉狀態，此 時一閘極全開訊號(All-gate-on)為低準位，而將所有的薄 ，電晶體之閘極全數導通。參考圖3，倾示本發明一較 佳實施例中的藉由迴路使液晶儲存電容31〇所積存的電荷 經由薄膜電晶體320的源極端中和之示意圖。其中3〇ι係 源極驅動線，302係閘極驅動線；若薄膜電晶體32〇的源 ，不能控制如本發_方法使電荷巾和，意即該閘極驅動' 線上之訊號不能適時使該閘極在電荷中和之前保持開啟， 則由於製程造成關閉時漏電流過小且不均的因素，^電晶 體上的電荷則必須經由源極驅線3〇1的路徑緩慢放電，'面 板上各區域的電晶體放電速度亦不同而產生潮汐現象。 請再參照圖4,根據本發提供的電荷中和控制電路， 適配於一液晶面板的特定應用積體電路(ASIC)4l〇中，1 電荷中和控制電路包括—訊號_單元414以及—問極 啟延遲單元416，其中該訊號偵測單元414耦接至一主^ 控制單元412，並提供兩個低準位致能訊號，其中一個a 電源致能訊號DC—DC.ENA，分別輕接至電源供應模組^ 的電源輸入端的切換裝置處將輸入電壓關掉，以及耦 電晶體閘極開啟準位(VGH)延遲單元43〇，使vgh在關 掉電源之前有延遲時間，以維持薄膜電晶體的閘極㈣^ 需的臨界電壓。其餘例如類比電壓源VDDA、電晶體閘 11 1237229 13528twf.doc 極關閉準位VGL、以及共同電壓VCOM等其它電源部分， 則設定與DCJDC.ENA訊號同時關掉。該訊號偵測單元414 另外送出一個All gate on訊號使得所有薄膜電晶體的閘極 打開，並決定動作時間點，此時間點可由閘極延遲單元來 控制在DC一DC.ENA的一特定時間間隔之後開始動作。 一般在液晶面板的系統中，正常的關機程序依下列順 序依次關閉電源··背光模組、訊號提供模組、以及電源模 組。根據本發明之關機電源時序，係以下所述的電源順序 操作，如圖5所繪示。當DC—DC.ENA動作後，類比電 壓源VDDA、閘極掃描線電壓VEEG以及共同電壓Vc〇m 等均要先關俥，其電壓均隨時間遞減至零電位GND。另 一方面，為了讓薄膜電晶體的閘極全數開啟，必須將VGH 關閉時延後，使得有足夠的電壓準位使閘極打開。而VGH 與DC_DC.ENA動作後的時間差由VGH延遲單元調整。 閘極全數開啟的時機必須在VDDA遞減至GND之後，才 強迫所有的的閘極打開，藉由電晶體源極侧的路徑迅速達 到電荷中和；閘極全數開啟的時機最晚必須在vgh電壓 達到能打開電晶體的閘極的最小電壓之前。如圖6所繪 示，其中所閘極開啟訊號範圍的起點與終點需分別晚^ vgh延遲控制範圍的起點與終點。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限疋本發明’任何熟習此技藝者，在不脫離本發明之精 =範圍内，當可作些許之更動與潤飾，因此本發明之保 複範圍當視後附之申請專利範圍所界定者為準。 12 1237229 13528twf.doc 【圖式簡單說明】 圖1是依照習知技術所繪示之一液晶顯示面板的潮汐 現象示意圖。 圖2A是依照習知技術所繪示之快速放電電路方塊示 意圖。 圖2B是依照習知技術所繪示之電容放電曲線圖。 圖2C是依照習知技術所繪示之電容快速放電曲線 圖。 圖3是依照本發明中一較佳實施例所繪示之晝素電容 所對應薄膜電晶體之電何中和不意圖。 圖4是依照本發明中一較佳實施例所繪示之解決潮汐 現象整合電路方塊示意圖。 圖5是依照本發明一較佳實施例中解決潮汐現象電路 之控制訊號示意圖。 圖6是依照本發明一較佳實施例中薄膜電晶體的電位 響應示意圖。 【主要元件符號說明】 圖式標記說明 100 液晶面板 102 晝素區塊 110 通道關閉漏電流較低與較高的分際 200 快速放電電路 301 貢料掃描線 302 閘極掃描線 1237229 13528twf.doc 310 電荷儲能元件 320 電晶體 400 解決潮汐現象電路 410 特定應用積體電路 412 主控制單元 414 訊號開關偵測單元 416 閘極開啟延遲單元 420 電源供應模組 430 VGH延遲控制單元 141237229 13528twf.doc IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a tidal phenomenon using energy storage elements to neutralize. [Previous technology] A kind of electric charge neutralization circuit and electric charge circuit device, and especially related to solving the liquid crystal display development in process / main process including photoresist, exposure, and expansion. Among them, the photoresist step is mainly based on the photoresist of the soil, and it is easy to cause the middle of the glass substrate = the photoresist of the cloth is thinner than the photoresist applied around it; on the other hand, the glass The middle area of the substrate is used as the back side, and the surface is engraved faster than the surrounding area, resulting in a finished film system with a value of -0 and a low leakage current. After the glass substrate of this type is assembled into a cutting panel, the image data is accessed by day capacitors. However, when the power is turned off, the channel-off leakage current varies according to the distribution in different regions, and the speed of discharge is naturally different. Therefore, a 1-element capacitor located in the middle region of the glass substrate takes a long time to discharge charge when the power is turned off. Referring to FIG. 1, a schematic diagram of a liquid crystal panel produced by a thin film transistor process on a glass substrate, including a liquid crystal panel 100, in which a pixel region 10 in the upper right corner divided into four regions is taken as an example. The closed irregular curve 110 indicates that the channel closing leakage current is lower and higher. When the power is turned off, since the area surrounded by 110 takes a long time to discharge the charge, which means that the image will take a long time to fade from the corresponding diurnal hormone. For the user, the residual diurnal surface will see a tide-like disappearance. Taking block 102 as an example, the faded square 1237229 13528twf.doc is shown in the direction of the arrow in Figure 1. film! 1 髀: The thin film transistor process for night crystal display applications' causes a phase difference. The corresponding on-current (Icm) and off-leakage current (i0ff) are 5 to 6 times the power of the second conductor. For example, if the transistor voltage is 24V at the pole, the voltage is about A, The transistor gate ^ is -6V 'in the closed state, and the leakage current Ioff is about pA. Xixia level: At the same time when the power of the display is turned off, because Ioff is smaller than Ion, it is clear that the high-resolution panel That is, it is easier to observe the image sticking / moon sand phenomenon. In more detail, when the power is turned off, the capacitance of the thin film transistor film is different, and the required discharge time is different. Different, so the afterglow daylight surface like the ebb tide appears on the panel. At this time, the thin film transistor itself is also switched to the off state, and the charge in the day capacitor can only be discharged through the data scanning line by the leakage current. However, it can be known from the above that I0ff is on the order of pA, and the discharge speed is to the naked eye of the user. In other words, there is an obvious non-uniform residual image, which means tidal phenomenon. This phenomenon can not be improved simply by increasing the Ioff current, because the increase in the Ioff specification of the thin film transistor itself in the manufacturing process will cause other image characteristics to deteriorate, such as flicker. Therefore, the tidal phenomenon of thin crystal transistors needs to be improved in circuit design. Figure 2A of McCaw is a circuit 200 in the conventional art that accelerates the gate voltage of a transistor to ground potential GND when the power is turned off. The energy storage element is used to gradually pull the gate voltage while the power is turned off. The voltage trend to the GND potential is quickly pulled to GND. From Figures 2B and 2C, it can be seen that the gate potential returns to the ground source level before and after the circuit improvement. The response is 1237229 13528twf.doc. Otherwise: However, this mechanism is only applicable to thin film transistors: = = = 到_Level; if the thin-film transistor is turned on and cannot be effectively turned on, the age phenomenon is still lacking. Therefore, a 'financial-efficiency integration circuit' is required, so that the gate voltage is still sufficient to effectively neutralize the charges on the pixels with each other when the power is turned off, and the problem of the tidal phenomenon of the liquid crystal panel is resolved. / [Summary of the Invention] In summary, an object of the present invention is to provide a charge neutralization control circuit 'applicable to-a liquid crystal display panel without changing the conditions of the panel film formation and private use' > A tidal phenomenon caused by the fact that the transistor cannot provide an effective discharge path when it is turned off. ^ Another object of the present invention is to provide a charge neutralization control circuit, which is suitable for the specific application integrated circuit (asic), control, the time point at which the film transistor is turned on, and With thin-film electricity, when the body gate is fully open, 'the LCD panel has a sufficiently high transistor startup level after shutdown' to effectively neutralize the charge on the day element to eliminate the tide and sand phenomenon. That is, the charge neutralization control circuit provided by the present invention is suitable for eliminating the tidal phenomenon of the liquid crystal display panel. It uses a signal switch signal detection unit (signai—0ff detect) that is built in the specific application integrated circuit (Sic). r) to detect / control the state of the signal. When the signal switch detection unit cannot detect the output signal of a main control unit, it indicates that the system is in the off state. At this time, an extremely fully open signal (A11_gate_on) is at a low enable level, and the LCD 1237229 13528twf.doc The gates of all thin-film transistors are all turned on, the liquid is said, the electricity stored in the storage volume passes through the thin-film circuit, and is connected to the storage capacitors and other energy storage elements in the daylight; In an integrated circuit (ASIC), the charge includes a surface measurement element and a gate delay unit, in which the measurement unit is coupled to-mainly ... the hole surface needs to control mk for two low levels to cause one of f疋 Power enable function DCJDC.ENA, ㈣ input, switch off the input voltage at the switching device, and the domain to Vgh, the delay unit, so that VGH has a delay time before the power is turned off to maintain the thin film transistor. The required critical voltage for riding. Other power sources such as analog voltage source, transistor shutdown voltage, and common voltage are set to be turned off at the same time as the DC-DC.ENA signal is sent. The signal detection unit sends another Aii-gate_on signal to make the gates of all thin film transistors open, and determines the time point of this action. The gate delay unit is used to control the DC-DC.ENA generation time. -The action starts after a certain time interval. Generally in a LCD panel system, the normal shutdown procedure turns off the power in the following order: the backlight module, the signal supply module, and the power module. The power-off sequence of the present invention operates in the sequence described below. After DCJDC.ENA is activated, the analog voltage source VDDA, the gate scanning line voltage VEEG, and the common voltage Vcom must be turned off first, and their voltages will decrease to zero potential GND with time. On the other hand, in order for the gate of the thin-film transistor to fully turn on, the VGH turn-off time must be delayed, and 1237229 13528twf.doc knows that there is a sufficient voltage level to open the gate. The time difference between Vgh and DC ~ DC.ENA is adjusted by the VGH delay unit. All gates must be turned on after VDDA is decremented to GND. All gates are turned on, and the charge is quickly neutralized by the path on the source side of the transistor. The gates must be turned on at the latest VGH at the latest. Before the voltage reaches the minimum voltage that can turn on the gate of the transistor. As mentioned above, the charge neutralization control circuit in the present invention can be integrated into an application-specific integrated circuit (ASIC) module of a liquid crystal panel to solve the problem of tide, and the inside of the application-specific integrated circuit (ASIC) is used. The circuit is implemented in cooperation with external circuits, so the number of components on the printed wiring board can be reduced, the cost reduction effect can be achieved, and the layout design of the printed wiring board can be simplified. According to the charge neutralization circuit in the present invention, the timing of VGH opening and the timing of the gate fully opening are controlled, so that after the panel shutdown command is issued, there is a sufficient level for the Lai transistor to be turned on, effectively neutralizing the amount of charge on the pixel. And off to solve the tide and sand problem. In addition, the tidal phenomenon caused by the different characteristics of the transistor distribution in each area of the panel due to the film formation process of the thin film transistor, etc., can be improved by using the method without changing the process. In order to make the above and other objects, features, and advantages of the present invention clearer, ”said Yi Yi I.“ A preferred embodiment is given below and will be described in detail with the accompanying drawings. [Embodiment] Please Referring to FIG. 4 ′, a green schematic diagram of a charge neutralization circuit device according to a preferred embodiment of the present invention is shown, which is suitable for eliminating the tidal phenomenon of the liquid crystal display panel system 1237229 13528twf.doc 400. asic) 4i〇2 a signal switch detection unit (signal—〇ff detect〇r) 4 丨 4 to detect the status of the signal. When the signal switch detection unit 414 can not detect a master control = unit 412 When the signal is displayed, it means that the LCD panel system is in the closed state. At this time, the All-gate-on signal is at a low level, and all the thin, transistor gates are all turned on. Refer to Figure 3, and show In a preferred embodiment of the present invention, a circuit is used to neutralize the electric charge accumulated in the liquid crystal storage capacitor 31 through the source terminal of the thin film transistor 320. Among them, 30 μ is a source driving line, and 302 is a gate driving. Line; if thin film transistor 3 The source of 20 cannot be controlled. If the method described in this issue makes the charge towel and the signal on the gate drive, the signal on the line cannot timely keep the gate open before the charge is neutralized. The leakage current is too small when the process is turned off due to the process. And because of unevenness, the charge on the transistor must be slowly discharged through the path of the source drive line 301, and the transistor's discharge rate in each area of the panel is also different to produce a tidal phenomenon. Please refer to Figure 4, again According to the charge neutralization control circuit provided by the present invention, the application specific integrated circuit (ASIC) 410 adapted for a liquid crystal panel, 1 the charge neutralization control circuit includes a signal_unit 414 and an interrogation delay unit 416. The signal detection unit 414 is coupled to a main control unit 412 and provides two low-level enable signals, one of which is a power enable signal DC-DC.ENA, which is lightly connected to the power supply module. ^ Turn off the input voltage at the switching device of the power input terminal and couple the transistor gate-on-level (VGH) delay unit 43 to make vgh have a delay time before turning off the power to maintain the gate of the thin-film transistor ㈣ ^ required Threshold voltage. Others, such as analog voltage source VDDA, thyristor 11 1237229 13528twf.doc, and other power supply parts such as the pole close level VGL, and common voltage VCOM, are set to be turned off at the same time as the DCJDC.ENA signal. The signal detection unit 414 In addition, an All gate on signal is sent to make the gates of all thin film transistors open and determine the time point of operation. This time point can be controlled by the gate delay unit to start the operation after a specific time interval of DC-DC.ENA. In the LCD panel system, the normal shutdown procedure turns off the power in the following order: backlight module, signal supply module, and power module. According to the power-off sequence of the present invention, the power supply sequence operation described below is illustrated in FIG. 5. After DC-DC.ENA is activated, the analog voltage source VDDA, the gate scanning line voltage VEEG, and the common voltage Vc0m must be turned off first, and their voltages will decrease to zero potential GND with time. On the other hand, in order to fully turn on the gate of the thin film transistor, the VGH turn-off delay must be delayed so that there is a sufficient voltage level to open the gate. The time difference between VGH and DC_DC.ENA is adjusted by the VGH delay unit. All gates must be turned on after VDDA is decremented to GND before all gates are forced to open, and the charge is quickly neutralized by the path on the source side of the transistor; the gates must be turned on at the latest at vgh voltage Before the minimum voltage to reach the gate of the transistor is reached. As shown in Fig. 6, the start and end of the gate-on signal range need to be delayed ^ vgh to delay the start and end of the control range, respectively. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make some modifications and retouching without departing from the spirit of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the attached patent application. 12 1237229 13528twf.doc [Brief description of the drawings] FIG. 1 is a schematic view of a tidal phenomenon of a liquid crystal display panel according to a conventional technique. FIG. 2A is a schematic block diagram of a fast discharge circuit according to a conventional technique. FIG. 2B is a capacitor discharge curve diagram according to a conventional technique. FIG. 2C is a fast discharge curve diagram of a capacitor according to a conventional technique. FIG. 3 is a schematic diagram of how to neutralize the electric charge of the thin film transistor corresponding to the daylight capacitor according to a preferred embodiment of the present invention. FIG. 4 is a schematic block diagram of an integrated circuit for solving a tidal phenomenon according to a preferred embodiment of the present invention. FIG. 5 is a schematic diagram of a control signal of a tide phenomenon solving circuit according to a preferred embodiment of the present invention. FIG. 6 is a schematic diagram of a potential response of a thin film transistor according to a preferred embodiment of the present invention. [Description of Symbols of Main Components] Graphical Symbol Description 100 LCD Panel 102 Daylight Block 110 Channel Closed Leakage Current Low and High Divide 200 Fast Discharge Circuit 301 Material Scanning Line 302 Gate Scanning Line 1237229 13528twf.doc 310 Charge energy storage element 320 Transistor 400 Solve tidal phenomenon circuit 410 Application-specific integrated circuit 412 Main control unit 414 Signal switch detection unit 416 Gate open delay unit 420 Power supply module 430 VGH delay control unit 14