TWI236055B - Plasma apparatus and method capable of adaptive impedance matching - Google Patents
Plasma apparatus and method capable of adaptive impedance matching Download PDFInfo
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1236055 五、發明說明(1) 一、 【發明所屬之技術領域】 一種半導體製造的裝置,特別是一種在高密度電漿化 學氣相沉積製程中應用雙極靜電吸盤時可降低閘極氧化層 損壞的半導體製造裝置。 二、 【先前技術】 當完成晶圓上金屬氧化半導體(Metal_ Oxide Semiconductor簡稱M0S)元件的主體製作後,接下來便是 進行M0S元件上方的多重金屬導體層與内連線的製作,隨 著製程技術的演進,元件尺寸規格也日益縮小,因此也使 得金屬導體間的間隙愈來愈小而在金屬導體間產生高深寬 比(h i g h a s p e c t r a t i 〇 )的間隙,導致沉積介電層於金屬 間的間隙時會因為難以沉積完全而形成孔洞於其中,進而 破壞元件電性造成晶圓的報廢。 為了解決上述沉積不完全的問題,美國專利號6, 2 3 9, 〇18與美國專利號6, 2 1 8, 284提出了利用高密度電漿化學氣 相沉積(high density plasma chemical vapor dep0si t ion簡稱HDPCVD)的製程來沉積金屬間的介電層(如 二氧化矽),美國專利號6,1 1 7,3 45中亦詳述了 HDPCVD製程 ’主要就是利用HDPCVD製程同時兼具化學氣相沉積與非等 向蝕刻作用的特性,如第一A圖所示,蝕刻作用來自於1236055 V. Description of the invention (1) 1. [Technical field to which the invention belongs] A device for semiconductor manufacturing, especially a bipolar electrostatic chuck in a high-density plasma chemical vapor deposition process, which can reduce gate oxide layer damage Semiconductor manufacturing equipment. 2. [Previous technology] After the main body of the Metal Oxide Semiconductor (M0S) device on the wafer is completed, the next step is to make the multiple metal conductor layers and interconnects above the M0S device. With the evolution of technology, the size of components has become smaller and smaller, so the gaps between metal conductors have become smaller and smaller, and high-aspectrati (0) gaps have been created between metal conductors, resulting in the deposition of dielectric layers between metal-to-metal gaps. It will be difficult to deposit completely and form holes in it, which will destroy the electrical properties of the components and cause wafer scrap. In order to solve the above-mentioned problem of incomplete deposition, U.S. Patent No. 6, 2 3 9, 〇18 and U.S. Patent No. 6, 2 1 8, 284 proposed the use of high density plasma chemical vapor dep0si t ion (HDPCVD for short) to deposit a dielectric layer (such as silicon dioxide) between metals. US Patent No. 6,11,3,45 also details the HDPCVD process, which is mainly using the HDPCVD process and chemical gas. Characteristics of phase deposition and anisotropic etching, as shown in Figure A, the etching comes from
1236055 五、發明說明(2) HDPCVD機台10中使用交流電漿產生電源12 利用電漿1 6與靜電吸般? ^卜的雷你ϋ你+ 曰 斯电及盤2 0上的電位至使電漿中的離子轟擊 日日囫18表面,非等向钱刻金屬導線上方 :進而^成金屬導體間無孔洞(V0ld free)的介電層沉積 在離子轟皋B曰圓18表面的過程中,往往會因為電漿16 :晶圓:8板面間電位差分布不均句而造成晶圓表面產生電 ",右晶圓18表面電位差距過大’將會損壞已製作完成 的閘極氧化層而使閘極氧化層產生崩潰的現象。 電漿1 6與 可能是來自於 台1 0中,靜電 e1ectros tat i el ectrostat i 靜電力將晶圓 有單一電極, 不會產生上述 題,然而,當 放電電路連接 感應電荷中和 至會因為移動 晶圓1 8板面 靜電吸盤2 0 吸盤2 0的型 c chuck)與 c chuck)兩 1 8吸附於靜 靜電吸盤2 0 電漿1 6與晶 製程結束後 ,必須等電 後才能移動 晶圓1 8時間 間電位差 上電位分 式包含單 雙極靜電 種型式, 電吸盤2 0 盤面電位 圓1 8板面 ,由於靜 漿16内帶 晶圓,如 過早造成 分布不均勻的產生原因 布不均,在一HDPCVD機 極靜電吸(mono-p〇lar 吸(bi〜p〇lar 由於靜電吸盤2 0係利用 上,若靜電吸盤20内只 分布可視為均勻分布而 間電位差分布不均的問 電吸盤20上的晶圓18無 電粒子與晶圓1 8板面上 此將影響量產的速度甚 晶圓1 8破片。 雙極靜電吸盤20 1如第一b圖所示,使用雙極靜電吸 2〇1時,就可在製程結束後利用雙極本身產生一放電電與 1236055 五、發明說明(3) 以增快移除雙極靜電吸盤2〇1對晶圓18吸附的靜電力,而 ΓΠΐίΐ度過慢與過早移動晶圓18產生的破片問題, 一疋; 離子轟擊的父流偏壓電源2 2亦透過雙極靜電 吸盤201内環電極28與外環電極3〇產生吸引離子轟擊的電 位差’如第-C圖所示’在高頻交流電傳輸的過程中,往 往會因為内外電極傳輸線阻抗的不同造成内外電極不同的 功率輸出,進而導致雙極靜電吸盤2〇1上電位分布不均勻 ,如第二Α圖所示,使晶圓丨8上内外側受離子轟擊後,產 生不同的電位而使晶圓i 8上產生表面電流,如第二B圖所 y造成多晶石夕導體層36上累積的電荷通過石夕底材4〇上的 閘極氧化層3 8,進而損壞閘極氧化層38。 為了解決上述閘極氧化層損壞的問題,美國 號5 題 :13 140與美國專利號5, 843, m中提到了增加製程步驟以 改受沉積介電層後的元件外觀來解決閘極氧化層因電漿16 而損壞的問題,但並沒有提到如何避免雙極靜電吸盤2〇ι 上吸引離子轟擊之電位差分布不均的問題H ς何避 ,雙極靜電吸盤上201吸引離子轟擊之電位差分布不均將 ,在應用雙極靜電吸盤2〇1的HDPCVD製程中相當重要的課 三 發明内容 本發明的主要目的為解決上述提到的雙極靜電吸盤上1236055 V. Description of the invention (2) The use of AC plasma in HDPCVD machine 10 to generate power 12 The use of plasma 16 and electrostatic attraction? ^ Bu Lei you ϋ you + Said electricity and the potential on the plate 20 so that the ions in the plasma bombarded the surface of the sundial 18, non-isotropically engraved above the metal wire: and then ^ formed no holes between metal conductors ( V0ld free) dielectric layer is deposited on the surface of the ion bombardment B, circle 18 surface, often because of the uneven distribution of the potential difference between the plasma 16: wafer: 8 board surface and cause electricity on the wafer surface ", If the surface potential difference of the right wafer 18 is too large, the gate oxide layer that has been fabricated will be damaged and the gate oxide layer will collapse. Plasma 16 and possibly from stage 10, electrostatic e1ectros tat i el ectrostat i The electrostatic force will have a single electrode on the wafer, which will not cause the above problem. However, when the discharge circuit is connected to the induced charge, it will be neutralized due to movement. Wafer 1 8 plate electrostatic chuck 2 0 chuck 2 0 type c chuck) and c chuck) 2 1 8 attracted to static electrostatic chuck 2 0 plasma 16 and crystal process, you must wait for electricity before moving the wafer The potential difference upper potential fraction over time includes single and bipolar electrostatic types, electric chucks, 20 disk surface potential circles, 18 plate surfaces, and wafers in the static slurry 16. If the distribution is too early, it may cause uneven distribution. In the HDPCVD machine, the electrostatic suction (mono-pollar suction (bi ~ pollar) is used because the electrostatic chuck 20 is used. If only the distribution in the electrostatic chuck 20 can be considered as a uniform distribution and the potential difference is unevenly distributed. The non-electric particles on the wafer 18 on the electric chuck 20 and the surface of the wafer 18 will affect the speed of mass production even if the wafer 18 is broken. The bipolar electrostatic chuck 20 1 uses bipolar electrostatic as shown in the first figure b. It can be used after the end of the process when it is inhaled The electrode itself generates a discharge current and 1236055 V. Description of the invention (3) To accelerate the removal of the electrostatic force of the bipolar electrostatic chuck 021 on the wafer 18, and to move the wafer 18 too slowly and prematurely Fragmentation problems, a moment; the parental bias bias power 22 of the ion bombardment also passed through the bipolar electrostatic chuck 201 inner ring electrode 28 and outer ring electrode 30 to generate a potential difference that attracts ion bombardment 'as shown in Figure -C' at high frequencies In the process of alternating current transmission, the power output of the internal and external electrodes is often different due to the different impedances of the internal and external electrode transmission lines, which leads to uneven potential distribution on the bipolar electrostatic chuck 201. As shown in Figure A, the wafer 丨After the upper, inner and outer sides are bombarded by ions, different potentials are generated to cause surface currents on the wafer i 8. As shown in y of the second B, the accumulated charge on the polycrystalline stone conductor layer 36 passes through the stone substrate 4. On the gate oxide layer 38, which in turn damages the gate oxide layer 38. In order to solve the above-mentioned problem of gate oxide layer damage, US No. 5 Question: 13 140 and US Patent No. 5, 843, m mentioned adding process steps To change the deposition The appearance of the component after the electrical layer solves the problem of the gate oxide layer being damaged by the plasma 16. However, it does not mention how to avoid the problem of uneven distribution of the potential difference attracting ion bombardment on the bipolar electrostatic chuck 20m. The uneven potential distribution of 201 attracting ion bombardment on the bipolar electrostatic chuck will be uneven, which is very important in the HDPCVD process using the bipolar electrostatic chuck 201. SUMMARY OF THE INVENTION The main purpose of the present invention is to solve the bipolar On electrostatic chuck
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吸引離子轟擊之電位差分布不均這個問題,本發明提出增 加一阻抗匹配電路於產生離子轟擊的交流偏壓電源與雙^ 靜電吸盤之間,利用阻抗匹配電路調整雙極靜電吸盤内外 電極的阻抗使内外電極阻抗相同,造成雙極靜電吸盤内外 電極有相同的功率輸出,更進一步地使雙極靜電吸盤上吸 引離子轟擊之電位差分布均勻而防止電漿對閘極氧化層的 破壞,經過實驗後的數據比較,晶圓上晶片(di e)的不良 率(fai 1 rate)由未加入阻抗匹配電路前的3〇%〜6〇%改進至 加入阻抗匹配電路後的〇%〜2%。 本發明提出的阻抗匹配電路包含可量測雙極靜電吸盤 中内外電極電壓與電流的功率量測器’利用功率比較器比 較内外電極的輸出功率差異後產生一控制訊號輸出,由自 動阻抗匹配器接收此控制訊號後由邏輯驅動馬達(1〇gic drive motors)改變各個可變阻抗元件的阻抗值以使内外 電極有相同的功率輸出。 四、【實施方式】 本叙明的一些貫施例會詳細描述如下。然而,.除了詳 細描述外,本發明還可以廣泛地在其他的實^例施行。亦 艮P,本發明的範圍不受在該提出之實施例的限制,而應以 後面提出之申請專利範圍為準。The problem of uneven distribution of potential difference attracting ion bombardment. The present invention proposes to add an impedance matching circuit between the AC bias power source generating the ion bombardment and the double electrostatic chuck, and use the impedance matching circuit to adjust the impedance of the inner and outer electrodes of the bipolar electrostatic chuck so that The internal and external electrode impedances are the same, resulting in the same power output for the internal and external electrodes of the bipolar electrostatic chuck, which further makes the potential difference of the attracted ion bombardment on the bipolar electrostatic chuck uniform and prevents the plasma from damaging the gate oxide layer. Data comparison shows that the failure rate (fai 1 rate) of wafers on wafers is improved from 30% to 60% before the impedance matching circuit is added to 0% to 2% after the impedance matching circuit is added. The impedance matching circuit provided by the present invention includes a power measuring device that can measure the voltage and current of the internal and external electrodes in a bipolar electrostatic chuck. The power comparator compares the output power difference between the internal and external electrodes to generate a control signal output. After receiving this control signal, the logical drive motors (10gic drive motors) change the impedance value of each variable impedance element so that the internal and external electrodes have the same power output. Fourth, [implementation] Some implementation examples described in this description will be described in detail as follows. However, in addition to the detailed description, the present invention can be widely implemented in other embodiments. In other words, the scope of the present invention is not limited by the proposed embodiment, but should be based on the scope of the patent application filed later.
1236055 五、發明說明(5) 如第三A圖所示,本發明中所提到的具阻抗匹配功能 的電漿裝置,主要應用於一高密度電漿化學氣相沉積 HDPCVD(high density plasma chemical vapor deposition)機台中,本發明應用的HDPCVD機台為一種感 應耦合電漿反應器1 〇 1,其電漿產生方式為利用一交流電 漿產生電源1 2通往感應線圈1 4,利用感應線圈1 4產生的電 磁場產生一具高濃度與低能量的電漿1 6,在本實施例中, 交流電漿產生電源12操作頻率約介於20 0KHz至3 50KHz之間 在HDPCVD製程反應(如金屬間介電層沉積)中,在進行 沉積反應前,需先將欲沉積介電層的晶圓1 8吸附於一雙極 靜電吸盤201上,雙極靜電吸盤2 〇1係利用一直流電源2 4產 生之靜電吸附力將,晶圓1 8吸附於雙極靜電吸盤2〇1上;待 製程終了時,此雙極靜電吸盤20 1將可提供一放電迴路使 靜電較一單極靜電吸盤更快速地消除以將晶圓丨8移出反應 室。 在沉積介電層於高深寬比(high aspect ratio)的線 路間隙時’往往會造成沉積不完全且在線路間隙中產生孔 洞(vo i d )的現象,此時必需要利用電漿内離子轟擊蝕刻與 化學氣相沉積兩者同時進行的方式來解決這種沉積不完全 的問題1在本發明中,產生離子轟擊(i〇n b〇mbardment) 的方式係利用一交流偏壓電源2 2連接於承載晶圓丨8的雙極1236055 V. Description of the invention (5) As shown in Figure 3A, the plasma device with impedance matching function mentioned in the present invention is mainly applied to a high density plasma chemical vapor deposition HDPCVD (high density plasma chemical In the vapor deposition) machine, the HDPCVD machine used in the present invention is an inductively coupled plasma reactor 101. The plasma generation method is to use an AC plasma to generate power 12 to the induction coil 1 4 and use the induction coil 1 4 The generated electromagnetic field generates a high-concentration and low-energy plasma 16. In this embodiment, the AC plasma generates a power source 12. The operating frequency is between about 20 kHz and 3 50 kHz, which is reflected in the HDPCVD process (such as metal (Electrical layer deposition), before carrying out the deposition reaction, it is necessary to first adsorb the wafer 18 on which a dielectric layer is to be deposited on a bipolar electrostatic chuck 201. The bipolar electrostatic chuck 201 is generated by using a direct current power source 24. The electrostatic adsorption force will attract the wafer 18 to the bipolar electrostatic chuck 201; when the process is finished, the bipolar electrostatic chuck 20 1 will provide a discharge circuit to make static electricity faster than a unipolar electrostatic chuck. eliminate To remove the wafer from the reaction chamber. When depositing a dielectric layer in a high-aspect-ratio line gap, 'it often results in incomplete deposition and voids (vo id) in the line gap. At this time, it is necessary to use ion bombardment etching in the plasma. Simultaneously with chemical vapor deposition, this method is used to solve the problem of incomplete deposition. 1 In the present invention, an ion bombardment is generated by using an AC bias power source 2 2 connected to a carrier. Wafer 丨 8 bipolar
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電及凰201和用雙極靜電吸盤201板面面積盥减岸耗入 電漿反應器1 01表面積的矣I φ將1 德 田知的I異,於電漿1 6與雙極靜電吸盤 之間產生一直流電位自我調降的功能,這個由於板面 面積不同而產生雙極靜電吸盤2〇1的直流電位自我調降功 能,將使電聚16内帶正電荷的離子往晶圓18表面鼻擊,以 蝕刻線路上阻擋線路間沉積的多餘沉積物,而形成不具孔 洞(void free)的介電層,在此交流偏壓電源22操作 約為 13. 56MHz。 、 如第二B圖所示,前述之雙極靜電吸盤2〇1具有一内環 電極28與一外環電極3〇,内環電極28與外環電極3〇分別皆 有與直流電源24以及交流偏壓電源2 2連接,其中内環電極 隔離電容阻抗321與外環電極隔離電容阻抗322分別用來阻 檔直流電進入交流偏壓電源2 2,因為電容元件對直流電來 說為斷路(電容阻抗Zc = l/joC,直流電頻率6j = 0,Zc為〇〇) ;另外内環電極隔離電感阻抗34 1與外環電極隔離電感阻 抗3 4 2为別用來阻擔父流電進入直流電源2 4,因為電减元 件對高頻交流電而言近似斷路(電感阻抗ZL=j 6JL,高頻交 流電頻率ω很大時,ZL亦很大)。 由於第三Β圖中内環電極隔離電容阻抗321與外環電極 隔離電容阻抗3 2 2阻抗值因傳輸線的不同而有不同的阻抗 值,會造成雙極靜電吸盤201中内環電極28與外環電極^ 上有不同的功率輸出(功率輸出Ρ 〇 u t為交流偏壓電源2 2功Electricity and phoenix 201 and the use of bipolar electrostatic chuck 201 plate surface area to reduce the consumption of surface area of the plasma reactor 01I φ will be 1 difference between Detian know I, between the plasma 16 and the bipolar electrostatic chuck Generates a DC potential self-adjusting function. This DC potential self-adjusting function that generates a bipolar electrostatic chuck 001 due to the different surface area of the plate will cause positively charged ions in the electropolymerization 16 to go to the surface of the wafer 18. 56MHz。 Click to etch the lines to block the excess deposits deposited between the lines to form a dielectric layer without voids (void free), where the AC bias power supply 22 operates at about 13.56MHz. As shown in Figure 2B, the aforementioned bipolar electrostatic chuck 201 has an inner ring electrode 28 and an outer ring electrode 30, and the inner ring electrode 28 and the outer ring electrode 30 are respectively connected to a DC power source 24 and The AC bias power source 22 is connected. The inner ring electrode isolation capacitor impedance 321 and the outer ring electrode isolation capacitor impedance 322 are used to block the direct current from entering the AC bias power source 22, because the capacitive element is open circuit for DC power (capacitive impedance Zc = l / joC, DC frequency 6j = 0, Zc is 〇〇); In addition, the inner loop electrode isolation inductance impedance 34 1 and the outer loop electrode isolation inductance impedance 3 4 2 are not used to prevent the parent current from entering the DC power supply 2 4, because the power reduction element is approximately open to high-frequency AC power (inductance impedance ZL = j 6JL, when the high-frequency AC power frequency ω is large, ZL is also large). The impedance of the inner ring electrode isolation capacitor impedance 321 and the outer ring electrode isolation capacitor impedance 3 2 2 in the third B figure have different impedance values due to different transmission lines, which will cause the inner ring electrode 28 and the outer ring in the bipolar electrostatic chuck 201 There are different power outputs on the ring electrode ^ (power output Pout is AC bias power supply 2 2 work
五、發明說明(7) 率^generator 減去 率損耗Pimpedance 形下進行離子轟擊 流,進而損壞閘極 壞,就必須使雙極 30上有相同的功率 相同的阻抗值,為 於内環電極隔離電 和交流偏壓電源22 同的阻抗值,進而 功率輸出以防止閘 阻抗功率損耗P i m p e d a n c e,其_阻抗功 為電流平方乘以阻抗值I2*Z),在此^青 晶圓1 8的過程中就會產生晶圓】8表面^ 氧化層,此時為了防止閘極氧化層的破 靜電吸盤201中内環電極28與外環電極 輸出,即内環電極28與外環電極μ上有 此本發明加入了一阻抗匹配電路42連 容阻抗321與外環電極隔離電容阻抗322 之間以使内環電極28與外環電極3〇有相 造成内環電極28與外環電極3〇有相同 極氧化層的破壞。 含-内;;極圖可;;容^❹ 阻抗調整器52,阻抗匹配電路42其/—比端^接51 至與二自動 電源22 ’阻抗匹配電路42另一端連 U 壓 阻抗如與外環電極隔離電容阻抗32 2。内衣電極隔離電容 如第四圖中功率量測 =ΐ:Γ:Γ值後,再換算成雙广 之内王衣電極功率輪出與一外環電極之功率輪出 1236055 五、發明說明(8) 率比較方塊5 1 0所示,透過一功率比較器5丨比較雙極靜電 吸盤2 0 1之内外電極功率輸出差異值以產生一控制訊號, 如自動阻抗调整方塊5 2 〇所示,自動阻抗調整器5 2將可接 收此控制訊號以複數個邏輯驅動馬達調整内環電極可變電 容元件441、外環電極可變電容元件442、内環電極可變電 感元件461與外環電極可變電感元件462的阻抗,使内環 極28的阻抗值與外環電極3〇的阻抗值為相同之阻抗值: 而使内環電極28與外環電極3〇有相同的功率輸 進,高密度電锻化學氣相沉積製程,由 :: 2°”内環電極28與外環繼之功率輸出相同在 子轟擊晶圓18時在晶圓18上不會產生内外側電壓 損壞閘極氧化層。 i而 以上所述僅為本發明之較每 發明之申請專利範圍。十 貝 1 ,並非用以限定本 内仍可予以變化而加以實施,二月=貝貝内谷的範_ 圍。因此,本發明之範# # 荨又化應仍屬本發明之範 靶噚係由下列申請專利範圍所界定。V. Description of the invention (7) Rate ^ generator minus rate loss Pimpedance In order to conduct ion bombardment and damage the gate, the bipolar 30 must have the same power and the same impedance value for the inner ring electrode isolation. The electrical and AC bias power sources 22 have the same impedance value, and thus the power output to prevent the gate impedance power loss P impedance, whose impedance work is the square of the current multiplied by the impedance value I2 * Z). A wafer will be produced in the surface] 8 surface oxide layer, in order to prevent the gate oxide layer from breaking, the inner ring electrode 28 and the outer ring electrode in the electrostatic chuck 201 are output, that is, the inner ring electrode 28 and the outer ring electrode μ have this. The present invention adds an impedance matching circuit 42 between the capacitor impedance 321 and the outer ring electrode isolation capacitor impedance 322 so that the inner ring electrode 28 and the outer ring electrode 30 are in phase, so that the inner ring electrode 28 and the outer ring electrode 30 are the same. Destruction of polar oxide layer. Containing -in ;; pole figure can be; capacity ^ 阻抗 impedance adjuster 52, impedance matching circuit 42 its /-ratio terminal ^ 51 to the two automatic power supply 22 'impedance matching circuit 42 the other end is connected to the U voltage impedance as external Ring electrode isolation capacitor impedance 32 2. The underwear electrode isolation capacitor is as shown in the fourth figure. Power measurement = ΐ: Γ: Γ value, and then converted into the power of the inner robe of Shuangguang and the output of an outer ring electrode. 1236055 V. Description of the invention (8 ) Rate comparison block 5 1 0, through a power comparator 5 丨 compare the power output difference between the internal and external electrodes of the bipolar electrostatic chuck 2 0 1 to generate a control signal, as shown in the automatic impedance adjustment block 5 2 〇, automatic The impedance adjuster 5 2 can receive this control signal to adjust the inner loop electrode variable capacitance element 441, the outer loop electrode variable capacitance element 442, the inner loop electrode variable inductance element 461 and the outer loop electrode by a plurality of logic driving motors. Change the impedance of the inductive element 462, so that the impedance value of the inner loop electrode 28 and the impedance value of the outer loop electrode 30 are the same impedance value: so that the inner loop electrode 28 and the outer loop electrode 30 have the same power input, The high-density electro-chemical forging chemical vapor deposition process consists of: 2 ° ”the inner ring electrode 28 has the same power output as the outer ring. When the sub-bombing wafer 18 does not generate internal and external voltages on the wafer 18 to damage the gate oxidation I. And the above is only the present invention Compared with the scope of patents applied for each invention. Ten shells 1 are not used to limit the scope of this invention and can still be changed and implemented. February = the scope of the Beibei Valley. Therefore, the scope of the present invention # # 催 又 化The targets that should still be within the scope of the present invention are defined by the following patent applications.
$ 12頁 1236055 圖式簡單說明 五、【圖示簡單說明】 第一A圖所示為先前技術中一HDPCVD機台之示意圖; 第一 B圖所示為先前技術中一雙極靜電吸盤内外電極 電性分布俯視圖; 第一 C圖所示為先前技術中一提供離子轟擊之交流偏 壓電源與提供雙極靜電吸盤靜電吸附力之直流電源連接之 等效電路圖;$ 12 页 1236055 Brief description of the diagram 5. [Simplified illustration of the diagram] The first diagram A shows a schematic diagram of an HDPCVD machine in the prior art; the first diagram B shows the inner and outer electrodes of a bipolar electrostatic chuck in the prior art Top view of the electrical distribution; Figure 1C shows the equivalent circuit diagram of the connection between an AC bias power supply that provides ion bombardment and a DC power supply that provides the electrostatic attraction of a bipolar electrostatic chuck in the prior art;
第二A圖所示為先前技術中一雙極靜電吸盤内外電極 功率不同產生晶圓表面電子流之示意圖; 第二B圖所示為先前技術中一因電漿離子轟擊晶圓造 成多晶矽導體層累積電荷過多產生閘極氧化層崩潰而導通 之不意圖, 第三A圖所示為一感應耦合電漿反應器之示意圖; 第三B圖所示為一加上阻抗匹配電路後提供離子轟擊 之交流偏壓電源與提供雙極靜電吸盤靜電吸附力之直流電 源連接之等效電路圖; 第三C圖所示為一阻抗匹配電路内部之等效電路圖; 以及The second diagram A shows a schematic diagram of the electron flow on the surface of the wafer generated by the power difference between the internal and external electrodes of a bipolar electrostatic chuck in the prior art. The second diagram B shows a polycrystalline silicon conductor layer caused by plasma ions bombarding the wafer in the prior art. Excessive accumulated charge causes the gate oxide layer to collapse and become unintentional. Figure 3A shows a schematic diagram of an inductively coupled plasma reactor. Figure 3B shows an ion bombardment circuit with an impedance matching circuit. Equivalent circuit diagram of the connection between an AC bias power source and a DC power source that provides the electrostatic attraction of a bipolar electrostatic chuck; Figure 3C shows an equivalent circuit diagram inside an impedance matching circuit; and
第四圖所示為一調整雙極靜電吸盤内外電極阻抗值之 流程圖。 符號說明:The fourth figure shows a flow chart for adjusting the impedance values of the inner and outer electrodes of the bipolar electrostatic chuck. Symbol Description:
第13頁 1236055 &]式簡早說明 10 HDPCVD 機 台 101 感 應 耦 合 電 漿 反 應 器 12 交 流 電 漿 產 生 電 源 14 感 應 線 圈 16 電 漿 18 晶 圓 20 靜 電 吸 盤 201 雙 極 靜 電 吸 盤 22 交 流 偏 壓 電 源 24 直 流 電 源 2 8 内 環 電 極 30 外 環 電 極 321 内 環 電 極 隔 離 電 容 阻 抗 322 外 環 電 極 隔 離 電 容 阻 抗 341 内 環 電 極 隔 離 電 感 阻 抗 342 外 環 電 極 隔 離 電 感 阻 抗 d6 多 晶 矽 導 體 層 38 閘 極 氧 化 層 40 矽 底 材 42 阻 抗 匹 配 電 路 441 内 環 電 極 可 變 電 容 元 件 442 外 環 電 極 可 變 電 容 元 件 461 内 環 電 極 可 變 電 感 元 件Page 12 1236055 &] Short description 10 HDPCVD machine 101 Inductively coupled plasma reactor 12 AC plasma power 14 Induction coil 16 Plasma 18 Wafer 20 Electrostatic chuck 201 Bipolar electrostatic chuck 22 AC bias power 24 DC power supply 2 8 inner ring electrode 30 outer ring electrode 321 inner ring electrode isolation capacitor impedance 322 outer ring electrode isolation capacitor impedance 341 inner ring electrode isolation inductance impedance 342 outer ring electrode isolation inductance impedance d6 polycrystalline silicon conductor layer 38 gate oxide layer 40 silicon Substrate 42 Impedance matching circuit 441 Inner ring electrode variable capacitance element 442 Outer ring electrode variable capacitance element 461 Inner ring electrode variable inductance element
第14頁Page 14
1236055 圖式簡單說明 46 2 外環電極可變電感元件 50 功率量測器 5 0 0 功率量測方塊 51 功率比較器 510 功率比較方塊 52 自動阻抗調整器 5 2 0 自動阻抗調整方塊1236055 Brief description of drawings 46 2 Variable inductor element of outer ring electrode 50 Power measuring device 5 0 0 Power measuring block 51 Power comparator 510 Power comparing block 52 Automatic impedance adjuster 5 2 0 Automatic impedance adjusting block
第15頁Page 15
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US11289355B2 (en) | 2017-06-02 | 2022-03-29 | Lam Research Corporation | Electrostatic chuck for use in semiconductor processing |
JP7374103B2 (en) | 2018-01-31 | 2023-11-06 | ラム リサーチ コーポレーション | Electrostatic chuck (ESC) pedestal voltage isolation |
US11086233B2 (en) | 2018-03-20 | 2021-08-10 | Lam Research Corporation | Protective coating for electrostatic chucks |
US11183368B2 (en) * | 2018-08-02 | 2021-11-23 | Lam Research Corporation | RF tuning systems including tuning circuits having impedances for setting and adjusting parameters of electrodes in electrostatic chucks |
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