506012 A7 B7 五、發明説明（！） 本申請書係基於並申請2000年6月2日提出之美國臨 時申請號60/208,568之塡寫日的權利。 (請先閲讀背面之注意事項再填寫本頁) 發明背景 本發明係有關使用電漿輔助處理的半導體晶圓製造。 半導體晶圓製造程序大致包括改變晶圓表面或其構件 組成的蝕刻、層沉積及化學處理。當晶圓被裝設於電漿處 理室中之夾盤上時，所有這些程序可依據被界定模式被選 擇性執行於晶圓構件上。 晶圓製造者時常尋求降低執行該程序所需的時間，同 時改善產品品質及降低不良率。 經濟部智慧財產局員工消費合作社印製 選擇性蝕刻操作大致牽涉到蝕刻非常窄且深的凹槽及 接觸孔，而增加蝕刻率的阻礙之一係爲產生黑斑損害。當 如接觸孔、孔徑及電容器之地形基板外形的上表面以電黑 斑這些外形下部而隔離離子及電子平衡流量時，亦被稱爲 模式相依充電損害的黑斑損害係被產生。最先抵達的電子 堆積於基板地形的上部直到該區域被負充電，稍後抵達的 電子則被拒絕或驅逐。由於Coulomb力，稍後抵達電子的 軌道係被累積於這些外形之上部的負電荷所改變。結果， 這些稍後抵達的電子不能抵達高方面比外形的下部。另一 方面，離子被加速向下進入外形且累積於下部，其因而被 負充電。再者，貫穿外形之電子係因其低慣性而朝向外形 的內壁，而多數相對大量離子可因其大慣性而抵達外形的 下部。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4 - 506012 A7 _________ B7_ 五、發明説明（2 ) (請先閱讀背面一之注意事項再填寫本頁) 當電子建造於基.板外形上部而離子建造於基板外形下 部時，相對負電荷累積於外形下部，而相對正電荷累積於 外形上部。當被用來形成金屬氧化半.導體場效電晶體閘絕 緣之薄氧化層放置於被蝕刻外形下部時，此充電現象即成 .爲明顯的問題。被累積於被鈾刻外形下部及標的矽基板之 正電荷之間的電位差變得足以大至產生大量正電流，最終 導致薄氧化層的破裂。因此，黑斑損害已被半導體製造者 確認爲主要的問題。當產業愈來愈薄且氧化層愈來愈薄時 ，黑斑損害已造成更多的問題。再者，該問題僅進一步與 驅動器加遽以增加電漿密度以增加鈾刻率。 現今一般相信使用來自電漿之高能電子可有效降低黑 斑損害。可替代是，加速來自電漿之電子至晶圓表面亦可 爲有效的裝置。此技術中之一般實施係施加相對低頻射頻 偏壓至晶圓上以創造吸引離子至晶圓的自偏壓。然而，爲 了避免黑斑損害，必須於每個低頻射頻偏壓周期放置足夠 之電子於凹槽及孔徑下部以平衡這裡的正離子電荷。 經濟部智慧財產局員工消費合作社印製 藉由提供適當負偏壓於夾盤來加速正離子至晶圓係爲 相當容易的工作，如藉由上述低頻射頻偏壓所產生者。然 而，加速電子至晶圓不需更複雜的技術。 任何用於繪出來自電漿之電子均必須考慮電漿之源阻抗， 通常被稱爲充電源之電流-電壓（Ι-V)特性（其中電漿可被稱 爲充電源）。流入夾盤之電流係劇烈增加爲夾盤偏壓的指數 函數。此可被表不爲方程式： 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -5- 506012 A7 B7 五、發明説明（3 ) I = = Is e + e(v-Vs"Te ; (請先閲讀背面之注意事項再填寫本頁) 其中I爲電流，Is爲飽和電流，e爲電荷，Te爲電壓中之 電子溫度，V爲夾盤上的偏壓，而Vs爲電漿電位。若夾盤 偏壓V接近電漿電位Vs，則電流非常大。當電流實際上大 於離子飽和電流時，電漿會被充滿。當該者發生時，電漿 可當作用於電流的高阻抗電流源。當電漿電流源過滿時， 電漿電位崩潰至電極電位，.電子接著會以非常小之能量湧 進晶圓，且僅增加空間電荷而不需足夠能量進入高方向比 外形的下部。 經濟部智慧財產局員工消費合作社印製 若正偏壓僅以電漿電位緊密遵循最大正電壓於夾盤上 之方式被施加至夾盤上，則後者結果將會產生，此例中夾 盤上之正偏壓僅會提升電漿電位。如先前已被提出之曰本 專利第1 0270419號所揭示者，如圖1A所示，藉由添加短期 正偏壓脈衝至被施加至夾盤之低頻射頻偏壓，可賦予該能 量至電子因而降低黑斑損害。爲了加速電子至晶圓，各脈 衝係被施加至低頻射頻偏壓的正半周期。各脈衝必須具有 一個與夾盤上之低頻射頻偏壓相關的精確相位或時間延遲 ，於各射頻電壓周期之其他部份期間，以各正脈衝加速電 子及以負低頻射頻電壓加速離子。此方法中之各脈衝的精 確時點係爲關鍵。上述專利係揭示，爲了藉由夾盤上之各 正脈衝電壓來加速電子，脈衝存續期間或寬度必須小於電 漿電位的反應時間，且1 〇ns之脈衝存續期間將快得足以加 速電子朝向晶圚而不需提升電漿電位。 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） -6 - 506012 A7 B7 五、發明説明（4 ) (請先閲讀背面之注意事項再填寫本頁) 通常，爲使外套.中之電漿離子以夾盤上之相對低頻射 頻電壓來同步化及被重分配於各射頻期間，射頻電壓必須 具有低於激發及維持電漿之頻率的頻率。因此，射頻電壓 之頻率上限係爲電槳激發頻率。射頻電壓之頻率下限係於 不會產生黑斑損害下被晶圓被暴露於電漿中之最大充電時 間（t。）所決定，也就是f > 1/ t。。”充電時間”一詞係被認知 於技術中。因此，夾盤上之相對低頻射頻電壓的頻率範圍 大致介於幾十萬赫茲及幾百萬赫茲之間。 射頻偏壓通常藉由使用隔直流電容器被耦合至夾盤。 此將使直流自偏壓得以發展於夾盤表面。當一夾盤偏壓周 期之表面上無淨電流時，也就是表面上存在電子及離子流 相等情況下，此夾盤表面上之自偏壓係被單獨決定（進一步 細節見1 963年物理流體6(Phys.Fluids)頁1 346-)。電子流在 射頻偏壓周期的其餘期間將到達射頻偏壓的峰値並維持幾 乎可忽略般小。 ‘ 經濟部智慧財產局員工消費合作社印製 本發明可應用的電漿輔助處理類型中，處理室中之電 漿可被處理被邊界表面包圍。該表面之一係爲射頻偏壓被 耦合至且直流自偏壓被形成其上之被處理的晶圓表面。電 子邊界層或外套被形成之此實體表面上，其電位的變化係 從電漿空間之電位至實體表面之電位（爲簡化起見，假設整 個”前外套”之任何微小電位變化均可被忽略）。圖2C描繪電 漿邊緣處Vp(t)及晶圓表面Vb(t)處之電壓波形。偏壓波形的 負偏置可表示直流自偏壓Vdc。因此，射頻偏壓波形峰値 期間之晶圓表面處（圖2C中之線2A)及稍晚於波形峰値期間 本紙張尺度適用中.國國家標準（CNS ) A4規格（21〇X297公釐） -7- 506012 A7 B7 五、發明説明（5 ) (圖2C中之線2B)的瞬間電位輪廓係分別被顯示於圖2A及 2 B的實線。圖2 A中，從電漿至晶圓表面的瞬間電壓近似固 定’也就是電漿外套已崩潰。然而，圖2B中，電壓單調地 從整個外套降低至晶圓表面。 現在，當如圖1所示之電壓脈衝被疊置於正弦偏壓波 形上時，電位輪廓視偏壓波周期期間脈衝何時被施加而有 不同的表現。例如，如圖2A所示，被疊置於偏壓峰値之時 點h及u之間的方波電壓脈衝於脈衝存續期間會產生電漿 空間電位。此時點期間，晶圓表面接收低能量電子流（係電 漿空間電位增加的原因）；當表面電位被施加正脈衝時，極 具機動性（低慣性）電子會因簡短存在電子相吸而流過表面， 且隨後提升電漿空間電位以維持零的淨電流。然而，若脈 衝被疊置於偏壓峰値之外的最適位置時，電位分佈可如圖 2B所示的不同反應。若脈衝非常快（也就是1-l〇ns)，則電 漿空間電位可維持不變，且電壓分佈不再單調地從整個外 套降低至晶圓表面，但卻降低至凹槽且接著增加至晶圓表 面處之脈衝電壓大小，如圖2B虛線所示。此情況下，抵達 動能小於被給定e △ V之電位能量障礙之外套邊緣的電子（ 其中e爲電荷，而△ V爲電漿空間電位及外套電壓凹槽之間 的電位差）會被驅逐回至電漿，而這些動能大於電位能量障 礙的電子會貫穿外套且被進一步加速至晶圓表面。藉此裝 置，僅高能量的電子（其數目於電漿電子能量分佈中係很少） 貫穿.外套以進一步被加速至晶圓表面。接著，這些非常高 能量的電子貫穿高方向比率的外形且平衡被累積於外形® 本紙張尺度適用中.國國家標準（CNS ) A4規格（2⑴X297公釐 (請先閱讀背面之注意事項再填寫本頁) ·€衣 _ 訂 經濟部智慧財產局員工消費合作社印製 -8 - 506012 A7 B7 五、發明説明（6 ) 部的正電荷。 、. 被揭示於上述專利說明書之方法中的關鍵因子係爲對 應射頻偏壓峰値相關之各脈衝的時點控制。如上述，若脈 衝啓動過早，則射頻偏壓太靠近電漿電位且可能將電漿電 流拉得過緊，其以脈衝電壓使電漿電位升高。結果，電漿 外套邊緣之電子不會獲得任何能量。另一方面，若脈衝啓 動過晚，則射頻偏壓過負之點僅有抵達電漿邊界的極少電 子及非常少能量之電子被產生。被說明於專利說明書之方 法的有效時點控制係非常難以達成，且當產業處理中電漿 及其他處理情況改變時，因爲電漿電位及電子能量兩者均 快速改變，所以該法並不適用於產業標準。 發明簡要 本發明提供一種藉由使用被疊置於低頻射頻電壓上之 非常高頻（VHF)正弦電壓所組成之夾盤偏壓來選擇性加速電 子於電漿系統中的裝置及方法。已被發現夾盤偏壓可選擇 性加速電子至晶圓表面。此偏壓可進一步加速電子至高能 量，使其可抵達高方向比率接觸孔之下部及晶圓模具的窄 凹槽中。該結果可有效降低黑斑損害。 若干圖式的簡單說明 圖1 A及1B係爲顯示依據先前發明（圖1A)及依據本發 明（圖1B)之夾盤偏壓的波形圖。圖2A、2B及2C係爲顯示 偏壓峰値處之脈衝期間的瞬間空間電壓輪廓（圖2A)，被移 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、τ 經濟部智慧財產局員工消費合作社印製 -9- 506012 A7 B7 五、發明説明（7 ) 出偏壓峰値處之脈衝期間的瞬間空間電壓輪廓（圖2 b )，及 瞬間電漿及偏壓（圖2C)。 (請先閲讀背面之注意事項再填寫本頁) 圖3 A爲描繪本發明之第一實施例的電路圖’圖3 b爲 描繪本發明之第二實施例的電路圖，圖3 c爲描繪本發明之 第二實施例的電路圖’圖4A、4B及4C爲用於圖3A及3B 之各電路之一組成之架構替代型式的電路圖。 主要元件對照表 1 2 耦合電路 14 非常局頻產生器 16 低頻射頻產生器 18 夾盤 2 0 電漿反應器系統 2 1 傳輸線 2 2 晶圓 3 0 非常高頻匹配網路 3 2 低頻射頻匹配網路 經濟部智慧財產局員工消費合作社印製 3 4 非常高頻射頻結合電路 3 6 絕緣器 3 8 可變阻抗電路 3 9 T型濾波器 發明的詳細說明 據本發明，除了 本紙張尺度適用中周國家標準（CNS ) A4規格（210X297公釐） -10- 506012 A7 B7 五、發明説明（8 ) 壓，非常高頻（VHF)，較佳爲正弦波的電壓振盪係於射頻範 圍中被疊置於具有相對低頻之射頻偏壓上，因此之後被稱 爲低頻射頻電壓。因此，如圖1 B所示，總夾盤偏壓係包括 被疊置於整個低頻射頻偏壓波上的非常高頻正弦波電壓。 .非常高頻電壓振盪本身提供一個位於接近射頻電壓振盪之 各正峰値之點的短存續期間正電壓，在不需複雜的脈衝時 點系統下，用以確保電子加速相位會發生於各射頻周期期 間。 依據本發明之一實施例，圖1 B之射頻及非常高頻成份 爲正弦波的電壓波形，可被顯示於圖3A之電路安置所提供 。此爲耦合電路1 2，其可結合非常高頻及射頻於夾盤上， 而可維持非常高頻及射頻電源產生器及負載之間的阻抗匹 配。耦合電路1 2被連接於一個非常高頻產生器1 4、一個低 頻射頻產生器1 6及電漿反應器系統20的夾盤1 8之間。耦 合電路1 2係經由傳輸線2 1被電連接至夾盤1 8。夾盤1 8支 撐將被進行電漿輔助製造處理的晶圓22。夾盤1 8、晶圓22 及系統20中之電漿形成電路1 2的負載阻抗。電漿反應器系 統20可爲任何已知被建構用來產生執行晶圓製造處理之電 漿的類型。該系統可運用用以產生電感性耦合或電容器耦 合電漿的成份。 耦合電路1 2之被描繪實施例係包括一個非常高頻匹配 網路30、一個低頻射頻匹配網路32及一個非常高頻-射頻 結合器電路34。非常高頻匹配網路30係特別被設計用來匹 配非常高頻產生器14之輸出阻抗至負載阻抗（以非常高頻頻 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 、言 經濟部智慧財產局員工消費合作社印製 -11 - 506012 A7 _B7 五、發明説明（9 ) 率）。例如，匹配網路30可爲具有一個電感器與一個可變電 容器串聯且一個第二可變電容器接地的L型網路。低頻射 頻匹配網路32係特別被設計用來匹配射頻產生器1 6之輸出 阻抗至負載阻抗（以射頻頻率）。同樣地，匹配網路32可爲 .如圖示之L型網路。射頻-非常高頻結合器電路34可加上（ 或疊置）個別射頻及非常高頻訊號，其中被附著至非常高頻 匹配網路30之電路腳中的濾波器係被設計來拒絕射頻訊號（ 也就是將射頻產生器隔絕非常高頻電源）。有了此電路，吾 人可疊置一個”被匹配”非常高頻訊號於”被匹配”射頻訊號， 並施加最終訊號至夾盤。被傳送自非常高頻產生器1 4之電 源及射頻產生器1 6可獨立被改變。 圖3B顯示一個替代實施例，其中耦合電路之非常高頻 腳之阻抗可獨立被改變。再次，此第二實施例係由一個非 常高頻耦合構件及一個射頻耦合構件組成。非常高頻耦合 構件係由一個阻隔器36及一個可變阻抗電路38組成。如圖 3B所示，阻隔器36可包含一個循環器及一個負載電阻器， 且被要求驅散被導入非常高頻產生器1 4的被反射電源。因 爲非常高頻產生器14的輸出阻抗其本身阻抗並不匹配負載 ，也就是非常高頻匹配網路30並不呈現於圖3 B的電路中， 非常高頻電源會被反射回非常高頻產生器14。循環器可保 護產生器及傾卸電源至電阻器。可變阻抗電路3 8可促進耦 合電路之非常高頻腳之阻抗的自動控制，且於一型式中可 僅包含一個可變電容器。一含意中，此可變電容器可被用 來反應性 與傳輸線2 1相關的電感。如前，射頻耦合構 i紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 、11 經濟部智慧財產局員工消費合作社印製 -12- 506012 A7 _____B7 五、發明説明（10 ) 件包括一個被連接至射頻產生器1 6之輸出及結合器電路34 之輸入的匹配網路32。 (請先閱讀背面之注意事項再填寫本頁) 圖3C呈現第三實施例，其結合上述第一及第二實施例 的優點。非常高頻耦合構件包括一個非常高頻產生器1 4及 —個匹配網路3 0。匹配網路3 0可用來最大化非常高頻電源 轉換器，且循環器3 6可保護非常高頻產生器丨4避免被產生 於電漿中的高頻雜訊。例如，此高頻雜訊可被呈現至夾盤 電路做爲非常高頻載體周圍的低頻側帶。除了 L型匹配網 路，ρ型匹配網路亦被包含於具有額外可變電容器之此實 施例以計數傳輸線2 1的大電感。除了”尖銳”τ型濾波器39 被包含用於隔絕非常高頻電源而不需使用結合器電路34之 外，低頻耦合構件係類似圖3A者。 經濟部智慧財產局員工消費合作社印製 顯示於圖3 A及3 B的電路中，結合器電路3 4係包含兩 個平行的共振濾波器。然而，其他電路配置亦爲可能，其 三例係被顯示於圖4 A、4 B及4 C。圖4 A之結合器電路係由 被連接於射頻電路路徑中且被裁剪以通過射頻電壓及阻隔 非常高頻電壓的低通濾波器，及被連接於非常高頻電路路 徑中且被裁剪以通過非常高頻電壓及阻隔射頻電壓的高通 濾波器組成。圖4B之結合器電路係由被串聯於射頻電路路 徑中以通過射頻電壓及阻隔非常高頻電壓的平行共振電路 ，被與射頻電路路徑並聯以阻擋射頻電壓及通過任何可被 呈現之非常高頻電壓的平行共振電路，被串聯於非常高頻 電路路徑中以通過非常高頻電壓及阻隔射頻電壓的平行共 振電路，及被與非常高頻電路路徑並聯以阻擋非常高頻電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐） -13- 506012 A7 B7 五、發明説明（1彳） 壓及通過任何可被:呈現之射頻電壓的平行共振電路組成。 (請先閱讀背面之注意事項再填寫本頁) 圖4C之結合器電路係由被串聯於射頻電路路徑以通過射頻 電壓及當做非常局頻電壓之開放電路的非常高頻四分之一 波長傳輸線，被串聯於非常高頻電路路徑中以通過非常高 頻電壓及阻隔射頻電壓的平行共振電路，及被與非常高頻 電路路徑做並聯以阻隔非常高頻電壓及當做任何可被呈現 之射頻電壓之短路電路的非常高頻四分之一波長傳輸線。· 被用於較佳實施例的非常高頻電壓係爲一百至幾百萬 赫茲頻率範圍的正弦波電壓，但其可具有其他的波形及頻 率。低頻射頻產生器16可供應較佳爲幾十萬赫茲至幾百萬 赫茲頻率範圍之低頻射頻電壓至電路12，但此電壓可具有 其他値。非常高頻產生器14可要求達1千瓦電源且射頻產 生器16可可要求達3千瓦電源。 經濟部智慧財產局員工消費合作社印製 圖1A及1B係顯示依據先前技術之被施加脈衝夾盤偏 壓（圖1A)及依據本發明之正弦波非常高頻夾盤偏壓（圖1B) 的比較。圖1 A中，針對被施加脈衝之夾盤偏壓，脈衝位準 及時點控制係爲關鍵。圖1 B中，針對正弦波非常高頻夾盤 偏壓，非常高頻電壓之阻抗及大小變化可被要求，但不需 時點控制。 非常高頻電壓的阻抗及大小控制可被人工或自動達成 於耦合電路之處。這些控制値可藉由實驗測試來決定。一 旦所有被支援之處理的規劃圖被建立，則處理裝設之操作 員或系統可人工或自動設立特別處理之對應模式以最小損 害來達成最大的飩刻速率。如圖1 B所示，電子流於低頻射 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -14- 506012 A7 _B7 五、發明説明（12 ) 頻電壓之正峰値處:爲最高，其中藉由使用耦合電路1 2，被 疊置非常高頻電壓的大小係於低頻射頻電壓之正峰値處被 哀減爲近似零。非常筒頻電壓之第一實質未衰減峰値出現 於接近正峰値處，其中產生電子加速相位於低頻射頻電壓 之下降坡上係最有效。耦合電路不應受限於較佳實施例中 的設計。有許多可被用來執行上述任務之電路設計的變化 〇 電路1 2的特殊特質係爲其非常高頻電壓的輸出阻抗非 常高（>> 50Ω)。當此非常高頻電壓被供應至夾盤18時， 若至夾盤1 8之電子流太高，則其自動被衰減；也就是因流 經耦合電路之電流增加而耦合電路之電壓差亦增加的事實 ，所以其可當做電流源。因爲非常高頻頻率充分高於離子 頻率，也就是離子慣性太大而不能遵循非常高頻域，所以 射頻訊號上之非常高頻訊號的疊置對離子能量的效應應不 大。正弦非常高頻電壓因而可當做一系列脈衝。當非常高 頻電壓被與低頻射頻電壓結合且被供應至夾盤偏壓時，總 有一個或若干非常高頻電壓的正半周期發生於加速電子的 正確時點上。其他之非常高頻的正半周期對系統的操作具 有最小的效應。 本發明進一步提供一種用於發現被給定處理的最適源 阻抗。找尋被給定處理的之適阻抗的程序被說明如下：處 理期間，操作員可觀察夾盤上之非常高頻正弦電壓及低頻 射頻電壓，並調整耦合源之非常高頻腳，也就是可變阻抗 電路3 8中的可變電路。如圖1 B所示，非常高頻正弦電壓於 本紙張尺度逍^中國國家標準( CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填穹本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 -15- 506012 A7 B7 五、發明説明（13 ) 低頻周期之正峰値處被衰減爲近似零。藉由調整非常高頻 正弦電壓源的阻抗，其可變化非常高頻電壓開始衰減處之 低頻射頻電壓周期中的動量或相位角。所以衰減大小可被 決定。 非常高頻正弦電壓的大小亦產生影響，而較佳操作範 圍可位於射頻電壓周期內。若非常高頻正弦電壓的大小過 大，則衰減太靠近峰値，若若非常高頻正弦電壓的大小過 小，則衰減開始遠離峰値。.所以吾人可僅藉由調整非常高 頻正弦電壓源的阻抗及大小於低頻射頻電壓曲線處來選擇 操作。因此，非常高頻正弦電壓的阻抗係被即時與處理黑 斑損害產生關連。非常高頻源之阻抗係以一步一步有系統 之方式被調整直到黑斑損害被消除或被降低至可接受的範 圍內。包含其方向之調整可藉由任何傳統的算術來界定。 例如，可變阻抗電路38中的可變電路可於任一方向被小量 地調整，與電壓衰減變化至電容變化相關的斜率可被評估 於兩者方向，接著各斜率可被用來決定調整從既存狀態至 預期狀態之衰減位準所需之方向及大小的改變。不同於每 個脈衝均需時點控制的先前技術，針對各特定處理，本發 明僅需建立一次非常高頻源的最適阻抗。非常高頻源阻抗 的調整可建立於肉眼可見的基礎上且易於達成。 本發明再進一步提供一種處理分析的方法。一例可針 對薄閘晶圓被處理分析。裝置，也就是耦合電路1 2的非常 高頻腳可被啓始調整至一被給定阻抗値，晶圓可被處理且 晶圓上之薄閘可被測量。接著，阻抗値可被改變，另一個 ^紙張尺度適用中國國家標準Y cNS ) A4規格（210 X297公釐） ~ -16- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 506012 Α7 Β7 五、發明説明（14) 晶圓可被處理且晶圓上之薄閘可再被測量。此順序可被重 複任何次數直到最佳阻抗値被決定爲止。 (請先閱讀背面之注意事項再填寫本頁) 本發明再進一步提供一種蝕刻具有高方向比孔徑之晶 圓的方法。因爲孔徑之方向比係於處理期間改變，所以運 作期間亦有耦合電路1 2之非常高頻腳之阻抗的變異。例如 ，處理結束時之黑斑損害較處理開始時更嚴重。該處理於 進一步下探孔徑時需要更高的電路阻抗。吾人需控制耦合 電路1 2之非常高頻頻率處之電路1 2的輸出阻抗及非常高頻 的電源大小，因爲它們兩者均會影響電流-電壓曲線（先前討 論的Ι-V特性）。可能改變非常高頻源之阻抗及大小做爲孔 徑深度的函數，其可於沒有時間達成更好結果的基礎上被 達成。此可以有系統方式被連續或一步一步達成。特別是 ，當孔徑深度增加時，阻抗可依據時間或深度之預定函數 而被增加。當阻抗被增加時，因爲射頻電壓周期峰値被增 加，所以非常高頻電壓的範圍係被衰減或壓縮。當孔徑深 度增加時，來自非常高頻產生器之非常高頻電壓大小或輸 出電源可較佳地被增加。 經濟部智慧財產局員工消費合作社印製 因此，耦合電路之非常高頻構件的阻抗及非常高頻電 源的大小係爲兩個控制參數。這兩個參數可分別被控制來 降低黑斑損害或獲得高蝕刻率。這兩個參數之控制設計以 達成更佳的蝕刻結果。當以上說明涉及本發明之較佳實施 例時，應了解到只要不背離其精神均可做許多修改。 ' 因此’目前被揭示之實施例可各方面被考慮爲說明作 用而不受限，本發明之範圍係被附帶申請專利範圍所指定 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297/ϋ ~ 一 -17- 506012 Μ Β7五、發明説明（15 )而非上述說明，且申請專利範圍之同等意義及範圍的所有 改變係預期被涵蓋其中。 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -18-506012 A7 B7 V. Description of the Invention (!) This application is based on and applies for the right to the date of the United States Provisional Application No. 60 / 208,568, filed on June 2, 2000. (Please read the notes on the back before filling out this page) BACKGROUND OF THE INVENTION The present invention relates to the manufacture of semiconductor wafers using plasma-assisted processing. The semiconductor wafer manufacturing process generally includes etching, layer deposition, and chemical treatment that change the composition of the wafer surface or its components. When a wafer is mounted on a chuck in a plasma processing room, all these procedures can be selectively performed on wafer components according to a defined pattern. Wafer makers often seek to reduce the time required to perform this procedure, while improving product quality and reducing defect rates. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The selective etching operation generally involves etching very narrow and deep grooves and contact holes. One of the obstacles to increasing the etching rate is the occurrence of dark spots. When the upper surface of the topography of the substrate, such as contact holes, apertures, and capacitors, is electrically blackened and the lower part of the shape is used to isolate ions and electrons from the equilibrium flow, black spot damage, also known as mode-dependent charging damage, is generated. The first arriving electrons accumulate on top of the substrate terrain until the area is negatively charged, and the later arriving electrons are rejected or expelled. Due to the Coulomb force, the orbital system that arrives at the electrons later is changed by the negative charge accumulated above these shapes. As a result, these later arriving electrons cannot reach the lower aspect of the high aspect ratio. On the other hand, the ions are accelerated downward into the shape and accumulate in the lower part, which is thus negatively charged. Furthermore, the electrons penetrating the outer shape are directed toward the inner wall of the outer shape due to their low inertia, and most relatively large ions can reach the lower part of the outer shape due to their large inertia. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -4-506012 A7 _________ B7_ V. Description of the invention (2) (Please read the precautions on the first page before filling this page) When the upper part of the outer shape of the board is built and the ions are built on the lower part of the outer shape of the substrate, relatively negative charges are accumulated in the lower part of the outer shape, and relatively positive charges are accumulated in the upper part of the outer shape. This charging phenomenon becomes an obvious problem when it is used to form a metal oxide half. The thin oxide layer of the conductor field effect transistor insulation is placed under the etched shape. The potential difference between the positive charges accumulated in the lower part of the engraved outline and the target silicon substrate becomes large enough to generate a large amount of positive current, which eventually leads to the cracking of the thin oxide layer. Therefore, dark spot damage has been identified as a major problem by semiconductor manufacturers. As the industry is getting thinner and the oxide layer is getting thinner, dark spot damage has caused more problems. Furthermore, the problem is only further increased with the driver to increase the plasma density to increase the uranium etch rate. Today it is generally believed that the use of high-energy electrons from plasma is effective in reducing dark spots. Alternatively, accelerating electrons from the plasma to the wafer surface can also be an effective device. A common implementation in this technique is to apply a relatively low frequency RF bias to the wafer to create a self-bias that attracts ions to the wafer. However, in order to avoid dark spot damage, enough electrons must be placed in the groove and the lower part of the aperture at each low frequency RF bias period to balance the positive ion charge here. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs It is quite easy to accelerate positive ions to the wafer system by providing an appropriate negative bias to the chuck, such as by the above-mentioned low frequency RF bias generator. However, accelerating electronics to wafers does not require more sophisticated technology. Any source used to draw electrons from the plasma must consider the source impedance of the plasma, which is often referred to as the current-voltage (I-V) characteristic of the charge source (where the plasma can be referred to as the charge source). The current flowing into the chuck increases dramatically as an exponential function of the chuck bias. This can be expressed as an equation: The paper size is applicable. National National Standard (CNS) A4 specification (210X297 mm) -5- 506012 A7 B7 V. Description of the invention (3) I = = Is e + e (v- Vs "Te; (Please read the notes on the back before filling this page) where I is the current, Is is the saturation current, e is the charge, Te is the electron temperature in the voltage, V is the bias voltage on the chuck, and Vs Is the plasma potential. If the chuck bias voltage V is close to the plasma potential Vs, the current is very large. When the current is actually greater than the ion saturation current, the plasma will be full. When this occurs, the plasma can be used as High-impedance current source of current. When the plasma current source is too full, the plasma potential collapses to the electrode potential. The electrons will then flow into the wafer with very small energy and only increase the space charge without entering the high energy. The direction is lower than the shape of the profile. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The positive bias on the chuck will only increase in this example Plasma potential. As disclosed in previously mentioned Japanese Patent No. 1 0270419, as shown in Figure 1A, this energy can be imparted by adding a short-term positive bias pulse to a low-frequency RF bias applied to the chuck. The electrons thus reduce the dark spot damage. In order to accelerate the electrons to the wafer, each pulse is applied to the positive half cycle of the low frequency RF bias. Each pulse must have an accurate phase or time related to the low frequency RF bias on the chuck Delay, during other parts of each RF voltage cycle, accelerating electrons with positive pulses and ions with negative low frequency RF voltages. The precise timing of each pulse in this method is critical. The above patents disclose that in order to Each positive pulse voltage on the disk accelerates the electrons. The duration or width of the pulse must be shorter than the plasma potential response time, and the 10ns pulse duration will be fast enough to accelerate the electrons toward the crystal lattice without increasing the plasma potential. This paper size applies to Chinese national standards (CNS> A4 specification (210X297mm) -6-506012 A7 B7 V. Description of invention (4) (Please read the note on the back first Please fill in this page again) Generally, in order to synchronize and redistribute the plasma ions in the jacket with the relatively low-frequency RF voltage on the chuck, the RF voltage must be lower than The frequency of the frequency. Therefore, the upper limit of the frequency of the RF voltage is the electric paddle excitation frequency. The lower limit of the frequency of the RF voltage is the maximum charging time (t.) By which the wafer is exposed to the plasma without causing dark spots. Decided, that is f > 1 / t. The term "charging time" is recognized in technology. Therefore, the frequency range of the relatively low-frequency RF voltage on the chuck is approximately several hundred thousand hertz and several million hertz. RF bias is usually coupled to the chuck by using a DC blocking capacitor. This will allow DC self-bias to develop on the chuck surface. When there is no net current on the surface of a chuck bias period, that is, the existence of electrons and ions on the surface is equal, the self-bias on the chuck surface is determined separately (for further details, see 1963 Physical Fluids) 6 (Phys. Fluids) page 1 346-). The electron flow will reach the peak of the RF bias and remain almost negligible during the rest of the RF bias cycle. ‘Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Among the types of plasma-assisted processing that can be applied to the present invention, the plasma in the processing chamber can be surrounded by the boundary surface of the processing. One of the surfaces is the processed wafer surface to which the RF bias is coupled and a DC self-bias is formed. The potential change on the physical surface on which the electronic boundary layer or jacket is formed is from the potential in the plasma space to the potential on the physical surface (for simplicity, any small potential changes throughout the "front jacket" can be ignored) ). Figure 2C depicts the voltage waveforms at Vp (t) at the edge of the plasma and Vb (t) at the wafer surface. The negative bias of the bias waveform can represent a DC self-bias Vdc. Therefore, at the surface of the wafer during the peak of the RF bias waveform (line 2A in FIG. 2C) and later on during the peak of the waveform, this paper size is applicable. National Standard (CNS) A4 specification (21 × 297 mm) ) -7- 506012 A7 B7 V. Explanation of the invention (5) (The line 2B in FIG. 2C) The instantaneous potential contours are shown in the solid lines in FIGS. 2A and 2B, respectively. In Figure 2A, the instantaneous voltage from the plasma to the wafer surface is approximately fixed, that is, the plasma jacket has collapsed. However, in FIG. 2B, the voltage is monotonically lowered from the entire casing to the wafer surface. Now, when a voltage pulse as shown in Fig. 1 is superimposed on a sinusoidal bias waveform, the potential profile behaves differently when the pulse is applied during the period of the bias wave. For example, as shown in FIG. 2A, a square-wave voltage pulse superimposed between the points h and u at the time of the bias peak 値 generates a plasma space potential during the pulse duration. During this time, the wafer surface receives a low-energy electron flow (because of the increase in plasma space potential); when a positive pulse is applied to the surface potential, highly mobile (low inertia) electrons will flow due to the brief existence of electron attraction. Across the surface, and then increase the plasma space potential to maintain a net current of zero. However, if the pulses are superimposed on the optimal position outside the bias peak, the potential distribution can respond differently as shown in Figure 2B. If the pulse is very fast (that is, 1-10ns), the plasma space potential can be maintained, and the voltage distribution no longer monotonously decreases from the entire jacket to the wafer surface, but it decreases to the groove and then increases to The magnitude of the pulse voltage at the wafer surface is shown by the dashed line in Figure 2B. In this case, the electrons reaching the edge of the outer sheath with a kinetic energy smaller than the potential energy barrier given by e △ V (where e is the charge, and △ V is the potential difference between the plasma space potential and the voltage groove of the jacket) will be expelled back To the plasma, and these electrons with kinetic energy greater than the potential energy barrier will penetrate the jacket and be further accelerated to the wafer surface. With this device, only high-energy electrons (the number of which is small in the plasma electron energy distribution) pass through the jacket to be further accelerated to the wafer surface. Then, these very high-energy electrons penetrate the shape of the high-direction ratio and the balance is accumulated in the shape. This paper size is applicable. National Standards (CNS) A4 specifications (2⑴X297 mm (please read the precautions on the back before filling in this Page) · € _ Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -8-506012 A7 B7 V. Positive charge of the invention description (6) Department. The key factors disclosed in the method of the above patent specification To control the timing of the pulses related to the RF bias peak. As mentioned above, if the pulse starts too early, the RF bias is too close to the plasma potential and the plasma current may be pulled too tight. The plasma potential rises. As a result, the electrons on the edge of the plasma jacket will not gain any energy. On the other hand, if the pulse starts too late, the point where the RF bias is too negative will only have very few electrons and very little energy reaching the plasma boundary. The electrons are generated. The effective time point control method described in the patent specification is very difficult to achieve, and when the plasma and other processing conditions in the industrial process change, Both the plasma potential and the electron energy change rapidly, so this method is not applicable to industry standards. SUMMARY OF THE INVENTION The present invention provides a method consisting of using a very high frequency (VHF) sinusoidal voltage stacked on a low frequency radio frequency voltage. Device and method for chuck bias to selectively accelerate electrons in plasma system. It has been found that chuck bias can selectively accelerate electrons to the wafer surface. This bias can further accelerate electrons to high energy so that they can be accelerated. Reach the lower part of the high-direction ratio contact hole and the narrow groove of the wafer mold. This result can effectively reduce the dark spot damage. A brief description of some figures Figure 1 A and 1B are based on the previous invention (Figure 1A) and the basis The waveform diagram of the chuck bias voltage of the present invention (Figure 1B). Figures 2A, 2B and 2C show the instantaneous space voltage profile during the pulse at the peak of the bias voltage (Figure 2A). Standard (CNS) A4 specification (210X 297 mm) (Please read the notes on the back before filling out this page), τ Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs -9-506012 A7 B7 V. Description of the invention ( 7) The instantaneous spatial voltage profile during the pulse at the peak of the bias (Figure 2b), and the instant plasma and bias (Figure 2C). (Please read the precautions on the back before filling this page) Figure 3 A In order to depict a circuit diagram of the first embodiment of the present invention 'FIG. 3 b is a circuit diagram depicting a second embodiment of the present invention, and FIG. 3 c is a circuit diagram depicting a second embodiment of the present invention' FIG. 4A, 4B and 4C are used 3A and 3B is a circuit diagram of an alternative type of architecture composed of one of the circuits. Comparison table of main components 1 2 Coupling circuit 14 Very local frequency generator 16 Low frequency RF generator 18 Chuck 2 0 Plasma reactor system 2 1 Transmission line 2 2 Wafer 3 0 Very high-frequency matching network 3 2 Low-frequency radio-frequency matching network Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 3 4 Very high-frequency radio frequency combining circuit 3 6 Insulator 3 8 Variable impedance circuit 3 9 T Detailed description of the invention of the type filter According to the present invention, in addition to the paper size applicable to the National Standard (CNS) A4 specification (210X297 mm) -10- 506012 A7 B7 V. Description of the invention (8) Voltage, very high frequency (VHF ), Preferably sine wave Based on pressure oscillations in the RF range to be stacked having a relatively low frequency of the RF bias, so after it referred to as a low frequency RF voltage. Therefore, as shown in Figure 1B, the total chuck bias system includes a very high frequency sine wave voltage that is superimposed on the entire low frequency radio frequency bias wave. The very high-frequency voltage oscillation itself provides a short period of positive voltage near the point of the positive peaks of the RF voltage oscillations. In the absence of a complex pulse time point system, it is used to ensure that the electronic acceleration phase will occur in each RF cycle. period. According to an embodiment of the present invention, the RF and very high frequency components of FIG. 1B are voltage waveforms of a sine wave, which can be displayed as provided by the circuit arrangement of FIG. 3A. This is a coupling circuit 12 that can combine very high frequency and radio frequency on the chuck while maintaining impedance matching between the very high frequency and radio frequency power generator and load. The coupling circuit 12 is connected between a very high frequency generator 14, a low frequency radio frequency generator 16 and a chuck 18 of a plasma reactor system 20. The coupling circuit 1 2 is electrically connected to the chuck 18 via a transmission line 21. The chuck 18 supports the wafer 22 to be subjected to a plasma assisted manufacturing process. The chuck 18, the wafer 22 and the plasma in the system 20 form the load impedance of the circuit 12. The plasma reactor system 20 may be of any type known to be configured to generate a plasma to perform a wafer manufacturing process. The system can use components used to generate inductive or capacitor coupled plasmas. The depicted embodiment of the coupling circuit 12 includes a very high frequency matching network 30, a low frequency radio frequency matching network 32, and a very high frequency-radio frequency combiner circuit 34. The very high frequency matching network 30 series is specially designed to match the output impedance of the very high frequency generator 14 to the load impedance (applicable to paper standards of very high frequency frequencies. National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page), printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -11-506012 A7 _B7 V. Description of Invention (9) Rate). For example, the matching network 30 may be an L-shaped network having an inductor in series with a variable capacitor and a second variable capacitor grounded. The low frequency RF matching network 32 series is specially designed to match the output impedance of the RF generator 16 to the load impedance (at RF frequency). Similarly, the matching network 32 may be an L-shaped network as shown. The RF-VHF combiner circuit 34 can add (or stack) individual RF and VHF signals. The filter attached to the circuit pins of the VHF matching network 30 is designed to reject RF signals. (That is to isolate the RF generator from very high frequency power). With this circuit, we can stack a "matched" very high frequency signal over a "matched" RF signal and apply the final signal to the chuck. The power and RF generator 16 transmitted from the very high frequency generator 14 can be independently changed. Figure 3B shows an alternative embodiment in which the impedance of the very high frequency pins of the coupling circuit can be changed independently. Again, this second embodiment is composed of a very high frequency coupling member and a radio frequency coupling member. The very high frequency coupling element is composed of a blocker 36 and a variable impedance circuit 38. As shown in FIG. 3B, the blocker 36 may include a circulator and a load resistor, and is required to dissipate the reflected power source introduced into the very high frequency generator 14. Because the output impedance of the very high frequency generator 14 does not match the load itself, that is, the very high frequency matching network 30 is not shown in the circuit of FIG. 3B, the very high frequency power will be reflected back to the very high frequency to generate器 14。 14. The circulator protects the generator and dumps power to the resistor. The variable impedance circuit 38 can promote the automatic control of the impedance of the very high frequency pin of the coupling circuit, and may include only one variable capacitor in one type. In a sense, this variable capacitor can be used to react the inductance associated with the transmission line 21. As before, the paper size of the RF-coupling structure i applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page), 11 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-12 -506012 A7 _____B7 V. Invention description (10) The part includes a matching network 32 connected to the output of the RF generator 16 and the input of the combiner circuit 34. (Please read the notes on the back before filling out this page.) Figure 3C shows the third embodiment, which combines the advantages of the first and second embodiments described above. The very high frequency coupling component includes a very high frequency generator 14 and a matching network 30. The matching network 30 can be used to maximize the very high frequency power converter, and the circulator 36 can protect the very high frequency generator 丨 4 from high frequency noise generated in the plasma. For example, this high frequency noise can be presented to a chuck circuit as a low frequency sideband around a very high frequency carrier. In addition to the L-type matching network, the p-type matching network is also included in this embodiment with an additional variable capacitor to count the large inductance of the transmission line 21. The low-frequency coupling member is similar to that shown in Fig. 3A, except that a "sharp" τ-type filter 39 is included to isolate a very high-frequency power source without using a combiner circuit 34. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The circuit shown in Figures 3 A and 3 B. The combiner circuit 34 contains two parallel resonant filters. However, other circuit configurations are possible, and three examples are shown in Figures 4 A, 4 B, and 4 C. The coupler circuit of FIG. 4A consists of a low-pass filter connected to the RF circuit path and cut to pass the RF voltage and blocking very high frequency voltage, and connected to the very high frequency circuit path and cut to pass It consists of very high frequency voltage and high-pass filter that blocks RF voltage. The combiner circuit of FIG. 4B is a parallel resonance circuit that is connected in series in the RF circuit path to pass the RF voltage and block very high frequency voltage. It is parallel to the RF circuit path to block the RF voltage and pass any very high frequency that can be presented. Voltage parallel resonance circuits, which are connected in series in the very high frequency circuit path to pass the very high frequency voltage and block the RF voltage, and are connected in parallel to the very high frequency circuit path to block the very high frequency electricity. This paper is suitable for China National Standard (CNS) A4 specification (210X: 297 mm) -13- 506012 A7 B7 V. Description of the invention (1 彳) It consists of a parallel resonant circuit that presses and passes any RF voltage that can be: (Please read the precautions on the back before filling this page.) The coupler circuit in Figure 4C consists of a very high frequency quarter-wavelength transmission line that is connected in series to the RF circuit path to pass the RF voltage and the open circuit as a very local frequency voltage. Parallel resonance circuits that are connected in series in the very high frequency circuit path to pass the very high frequency voltage and block the RF voltage, and are connected in parallel with the very high frequency circuit path to block the very high frequency voltage and as any RF voltage that can be presented A very high frequency quarter-wavelength transmission line of a short circuit. The very high frequency voltage used in the preferred embodiment is a sine wave voltage in the frequency range of one hundred to several million hertz, but it may have other waveforms and frequencies. The low frequency radio frequency generator 16 can supply a low frequency radio frequency voltage to the circuit 12 in a frequency range of preferably several hundred thousand hertz to several million hertz, but this voltage may have other chirps. The very high frequency generator 14 may require up to 1 kW of power and the RF generator 16 may require up to 3 kW of power. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Figures 1A and 1B show the pulse chuck bias (Figure 1A) applied according to the prior art and the sine wave very high frequency chuck bias (Figure 1B) according to the present invention. Compare. In Figure 1A, for the chuck bias to which pulses are applied, the pulse level and timing control are the key. In Figure 1B, for the sine wave very high frequency chuck bias, the impedance and the change of the very high frequency voltage can be required, but no time point control is required. Very high frequency voltage impedance and magnitude control can be achieved manually or automatically at the coupling circuit. These controls can be determined by experimental tests. Once all supported processing plans are established, the operator or system of the processing installation can manually or automatically set up a special processing corresponding mode to achieve the maximum engraving rate with minimal damage. As shown in Figure 1B, the size of the paper flowing at low frequency is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -14- 506012 A7 _B7 V. Description of the invention (12) Positive peak voltage The highest is: where the size of the very high-frequency voltage superimposed on the positive peak of the low-frequency RF voltage is reduced to approximately zero by using the coupling circuit 12. The first substantially undecayed peak voltage of the very barrel frequency voltage appears near the positive peak voltage, and it is most effective to generate the electron acceleration phase on the falling slope of the low frequency RF voltage. The coupling circuit should not be limited to the design in the preferred embodiment. There are many circuit design changes that can be used to perform the above tasks. The special characteristic of Circuit 12 is that its very high frequency voltage output impedance is very high (> > 50Ω). When this very high-frequency voltage is supplied to the chuck 18, if the electron flow to the chuck 18 is too high, it is automatically attenuated; that is, the voltage difference of the coupling circuit is also increased because the current flowing through the coupling circuit increases. The fact that it can be used as a current source. Because the very high frequency is sufficiently higher than the ion frequency, that is, the ion inertia is too large to follow the very high frequency domain, so the superposition of the very high frequency signal on the radio frequency signal should have little effect on the ion energy. The sinusoidal very high frequency voltage can therefore be treated as a series of pulses. When very high frequency voltages are combined with low frequency radio frequency voltages and supplied to the chuck bias, there is always one or more positive half cycles of very high frequency voltages occurring at the correct point in time to accelerate the electrons. Other very high frequency positive half cycles have minimal effects on system operation. The invention further provides an optimum source impedance for finding a given process. The procedure for finding the proper impedance for a given process is explained as follows: During the process, the operator can observe the very high frequency sinusoidal voltage and low frequency RF voltage on the chuck, and adjust the very high frequency pin of the coupling source, which is variable Variable circuit in impedance circuit 38. As shown in Figure 1B, the very high-frequency sinusoidal voltage is at the standard of this paper ^ Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling the dome page), 1T Ministry of Economic Affairs wisdom Printed by the Consumer Affairs Cooperative of the Property Bureau -15-506012 A7 B7 V. Description of the Invention (13) The positive peak of the low frequency period is attenuated to approximately zero. By adjusting the impedance of the very high frequency sinusoidal voltage source, it can change the momentum or phase angle in the low frequency RF voltage cycle where the very high frequency voltage begins to decay. So the amount of attenuation can be determined. The magnitude of the very high frequency sinusoidal voltage also has an effect, and the preferred operating range can be within the RF voltage cycle. If the magnitude of the very high frequency sinusoidal voltage is too large, the attenuation is too close to the peak chirp. If the magnitude of the very high frequency sinusoidal voltage is too small, the attenuation begins to be far away from the peak chirp. So we can only choose to operate by adjusting the impedance and magnitude of the very high frequency sinusoidal voltage source at the low frequency RF voltage curve. Therefore, the impedance of the very high frequency sinusoidal voltage is immediately related to the treatment of dark spots. The impedance of very high frequency sources is adjusted step by step in a systematic way until the dark spots are eliminated or reduced to an acceptable range. Adjustments including their orientation can be defined by any conventional arithmetic. For example, the variable circuit in the variable impedance circuit 38 can be adjusted in a small amount in either direction. The slope related to the change in voltage attenuation to the change in capacitance can be evaluated in both directions, and then each slope can be used to determine Changes in direction and magnitude required to adjust the attenuation level from an existing state to an expected state. Unlike the prior art, where each pulse requires point-in-time control, the present invention only needs to establish the optimum impedance of a very high frequency source once for each specific process. The adjustment of the very high-frequency source impedance can be based on the naked eye and is easy to achieve. The invention further provides a method for processing analysis. An example can be processed and analyzed for thin gate wafers. The very high-frequency pin of the device, that is, the coupling circuit 12 can be initially adjusted to a given impedance, the wafer can be processed, and the thin gate on the wafer can be measured. Then, the impedance 値 can be changed, and another ^ paper size applies the Chinese national standard Y cNS) A4 size (210 X297 mm) ~ -16- (Please read the precautions on the back before filling this page) Order the intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 506012 Α7 Β7 V. Description of the Invention (14) The wafer can be processed and the gates on the wafer can be measured again. This sequence can be repeated any number of times until the optimal impedance 値 is determined. (Please read the precautions on the back before filling this page) The present invention further provides a method for etching a crystal circle with a high specific aperture. Because the direction ratio of the aperture is changed during processing, there is also variation in the impedance of the very high frequency pins of the coupling circuit 12 during operation. For example, dark spots are more severe at the end of a treatment than at the beginning of the treatment. This process requires higher circuit impedances when drilling further down the aperture. We need to control the output impedance of the circuit 12 at the very high frequency of the coupling circuit 12 and the size of the power supply at the very high frequency, because both of them will affect the current-voltage curve (I-V characteristics previously discussed). It is possible to change the impedance and size of very high frequency sources as a function of hole depth, which can be achieved without having time to achieve better results. This can be achieved systematically or step by step. In particular, as the aperture depth increases, the impedance can be increased according to a predetermined function of time or depth. When the impedance is increased, the range of very high frequency voltages is attenuated or compressed because the RF voltage period peak value 增 is increased. As the aperture depth increases, the magnitude of the very high frequency voltage or output power from the very high frequency generator can be preferably increased. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, the impedance of the very high frequency components of the coupling circuit and the size of the very high frequency power are two control parameters. These two parameters can be individually controlled to reduce dark spot damage or achieve high etch rates. The control of these two parameters is designed to achieve better etching results. When the above description relates to a preferred embodiment of the present invention, it should be understood that many modifications can be made without departing from the spirit thereof. 'Thus' the presently disclosed embodiments may be considered in all aspects for illustrative purposes and are not limited. The scope of the present invention is specified by the scope of the accompanying patent application. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 × 297 / ϋ ~ I-17- 506012 Μ B7 V. Invention description (15) instead of the above description, and all changes in the meaning and scope of the patent application scope are expected to be covered. (Please read the precautions on the back before filling this page ) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -18-