TWI234841B - Structure and manufacturing process of semiconductor capacitor containing ruthenium metallic electrode - Google Patents

Abstract

The present invention relates to a structure and manufacturing process method for semiconductor containing metal/dielectric layer/metallic capacitor, wherein the disclosed semiconductor structure at least includes one substrate, one insulation layer, one metallic lower electrode, one dielectric layer, one metallic upper electrode, one glue layer, one barrier layer, and one inter-layer dielectrics. The barrier layer is a polysilicon layer used to prevent metal material from diffusing to cause contamination for the subsequent processes; and the barrier layer is also used to prevent metal material from oxidation due to direct contact with the inter-layer dielectrics. Moreover, the two-layer structure, one layer of TiMN and the other layer of TiW alloy, is used to enhance the adhesion between the barrier layer and interface of the metallic upper electrode.

Description

A7 B7 1234841 V. Description of the invention () Field of the invention: (Please read the notes on the back before filling out this page) The present invention is related to a semiconductor capacitor structure and manufacturing process, especially the semiconductor capacitor structure with ruthenium metal electrode and Its process. BACKGROUND OF THE INVENTION: In recent years, the trend in the semiconductor manufacturing industry is to reduce the size of memory cells to increase the degree of accumulation and the memory capacity of memory chips. As the line width of semiconductors continues to grow from sub-microns, the characteristics of memory still need to be maintained. For example, the minimum amount of stored charge required by a capacitor in a dynamic random access memory (DRAM) is still constant, and about 30 fF per memory cell must still be maintained in order to maintain the high reliability of the memory. For a highly integrated semiconductor device, the capacitance of a planar capacitor is also reduced because the area of the planar capacitor is reduced. One of the ways to improve is to increase the area of the capacitors stacked in a unit area, for example: forming a stacked capacitor to increase the capacitance value, or other types of capacitors such as trench capacitors or crown capacitors. Its purpose is also to increase the capacitance area of the unit memory cell to improve its efficiency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. On the other hand, due to the reduction in the memory cell unit area, the dielectric materials used in capacitors in previous components, such as silicon oxide and silicon nitride, have insufficient dielectric constant ( The dielectric constant of silicon oxide is about 4, and the dielectric constant of silicon nitride is about 7). Because if you want to reduce the thickness of the dielectric layer of silicon oxide or silicon nitride, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1234841 A7, Invention Description () To improve the capacitance of the capacitor, the spleen; 〃, J will increase the leakage current by σ due to the tunneling effect of the surface charge, and the thickness of the capacitor of the salty oxidized stone or nitrided stone will also have a fixed limit. Mizuki, J ’s solution to the above problem is the introduction of the higher electricity system I

The material replaces the traditional oxidized stone or nitrided stone, such as Ta205 or BST and other high-dielectric constant materials used in Section M (dielectric system of Ta205).

, Spoon is 20 ~ 24). For example, on a metal electrode in a MIM (Metal-Insulator_Metal) capacitor (for example: titanium nitride TiN, tungsten W, rhenium > (Bu Zhi, Bu) Tungsten Wf ^ ...), Ding a2 is deposited. Equivalent Oxide Thickness (EOT) of 5 layers can be reduced to 20 people. In this MIM structure, if a nail (Ru) is used as the lower electrode, the EOT of this capacitor can be reduced to 10 people. However, ruthenium is a material that is "incompatible with the current semiconductor process", so after using ruthenium as the upper electrode, a Poly layer should be used as a barrier layer to prevent the diffusion of ruthenium and the oxidation of ruthenium. However, the adhesion between ruthenium and is extremely poor, and the Poly layer cannot be directly plated on the upper electrode of ruthenium. Therefore, there is currently a need for an improved capacitor structure and method to provide a suitable capacitor design for semiconductor devices under the trend of shrinking semiconductor devices. Object and Summary of the Invention: One of the main objects of the present invention is to provide a semiconductor capacitor having a metal / dielectric layer / metal structure and a process for manufacturing the same. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) .... install ......... order ......... (Please read the back first (Notes on this page are reproduced on this page) 1234841

5. Description of the Invention (Another object of the present invention is to provide a semiconductor capacitor structure with a ruthenium metal electrode and a process for improving the storage capacity of the semiconductor capacitor. Another object of the present invention is to provide a semiconductor with a ruthenium metal electrode. Capacitance structure and its process' high dielectric constant of semiconductor capacitor, and solve the adhesion (adhesion), oxidation between nail metal electrode and dielectric metal dielectric layer (Die 1 ectrics; abbreviated π η, called + w / LD) (Oxidation) and method, and the problems between interfaces such as Contamination. According to the above-mentioned purpose, the present invention discloses a semiconductor structure and manufacturing method with a metal / dielectric layer / metal valley. That is, a substrate, an insulating layer, a ruthenium metal lower electrode, a dielectric layer, a ruthenium metal upper electrode, a glue layer, and a stone barrier are sequentially formed in the semiconductor structure. Layer and a metal dielectric layer. Among them, the polycrystalline silicon barrier layer is used to prevent the diffusion of the nail metal material and cause contamination in subsequent processes, and to prevent the ruthenium metal material from directly contacting. The metal dielectric layer is oxidized. The adhesive layer system has a two-layer structure, which is a titanium tungsten nitride (TiVVN) layer and a titanium tungsten (TiW) alloy layer, which are used to solve the barriers of ruthenium metal materials and polycrystalline silicon barriers. The problem of peeling due to poor adhesion between the layers. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs. : The invention of the invention said that the order was placed in a simplified form. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1234841 A7 B7. 5. Description of the invention () The purpose, viewpoint and advantages of the invention are better understood. At the same time, please refer to the following diagrams of the present invention for explanation: (Please read the precautions on the back before filling in this page) The first A to D diagrams show the cross-sectional view of the structure of the semiconductor capacitor of the present invention; the second diagram shows the semiconductor capacitor of the present invention Schematic diagram of X-ray diffraction of the titanium nitride tungsten layer in the adhesion layer formed in the structure; and the third A to D diagrams show scanning electron microscopy using several adhesion layers in the semiconductor capacitor structure Schematic illustration of comparison of mirror magnification. Comparison of circle numbers: 100 semiconductor substrate 110 insulation layer 120 insulation layer α \ 130 ruthenium metal lower electrode 140 oxide layer or photoresist layer 150 dielectric layer 160 ruthenium metal upper electrode 170 adhesive layer 172 nitride Ferro-titanium layer 174 Titanium-tungsten alloy layer 180 Polycrystalline silicon barrier layer 190 Dielectric metal dielectric layer Detailed description of the invention: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs With the development trend of DRAM technology below 0 μm, The structure design and manufacturing process of MI MM capacitors must provide sufficient capacitance values for highly stacked paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) 1234841. 5. Description of the invention () Early memory cells. Among them, the most attractive mim capacitor structure is the use of-ruthenium metal material as the lower electrode in the structure, and on the nail metal material / oxidized dioxetane a205 layer as the dielectric of the capacitor structure material. Because the crystal 袼 in the ruthenium metal material is in the direction of < 〇〇1 > and the lattice direction of the dingxin 〇5 material is similar, when butyl a2 05 is deposited on the ruthenium metal material,

Ta205 is mainly aligned along the < 〇〇1 > lattice direction of the ruthenium metal and is distorted. In this way, the dielectric coefficient of Ding a205 material after distortion will increase greatly, from the original dielectric coefficient of 20-24, to about clang, the increase is about double, which effectively improves the unit memory. Capacitance required in the cell. However, the above-mentioned MIM capacitor structure still has many problems. That is, in the subsequent manufacturing process of a semiconductor device using a capacitor made of a ruthenium metal material, the ruthenium metal material easily reacts with oxygen atoms of the dielectric metal dielectric layer to be oxidized, and the adhesion between the two interfaces is not good. In addition, ruthenium metal materials also have concerns about contaminating subsequent semiconductor process components and equipment. To sum up, the present invention is used for isolating the ruthenium metal material and the dielectric metal dielectric layer. In one embodiment, the barrier layer can be made of polycrystalline silicon to isolate the ruthenium metal material and the dielectric metal dielectric layer. Effect to prevent subsequent oxidation and pollution problems of ruthenium metal materials. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs However, there is also a problem of poor adhesion between the interface of the ruthenium metal material and the polycrystalline silicon barrier layer, and peeiing often occurs at the interface. The MIM capacitor structure disclosed in the present invention uses an adhesive layer between the upper electrode of ruthenium metal and the polycrystalline silicon barrier layer to solve the adhesion between the interfaces 297 mm.) This paper size applies the Chinese National Standard (CNS) A4 specification ( 21〇1234841 V. Description of the invention (Poor problem. To be clear, the ^ ^ ^ a is covered with two sublayers, one is covered with ruthenium and the other is a titanium tungsten layer. First read the notes on the back and fill in this page with Fqi.) The metal adhesive layer is added to the top electrode of the nail metal. It is added between the compatibility and the upper electrode and the Shixi barrier layer to increase the ruthenium metal. Adhesive bonding between the upper electrode and the ITO gate layer, the titanium tungsten alloy layer and the polycrystalline silicon resist layer. It should be noted that the adhesive layer containing oxygen atoms is not suitable for the present invention because of the oxygen-containing adhesion Oxygen atoms in the layer will oxidize the upper electrode and reduce its conductivity. Receiving electricity at π ^ The following will describe the structure and manufacturing method of the semiconductor capacitor of the present invention with an embodiment. Make the first A ~ D picture description system A structural cross-sectional view of a semiconductor capacitor of the present invention, wherein 'refer to FIG.-A' firstly provides a semiconductor substrate 100, which includes the main parts of a general semiconductor device, such as: gate structure, source / drain Areas, shallow trench structures, plugs, etc. An insulating layer 110, such as an oxide layer, is then deposited over the semiconductor substrate 100. Then, at least one of the capacitor structure stomach required for the semiconductor element is formed in the insulating layer 110. The opening 120 ′, for example, forms a crown-type capacitor structure, etc. After the openings are formed, a ruthenium metal lower electrode 130 is formed on the bottom of each insulating layer opening 120 and on the surface of the inner side wall, of which the ruthenium metal lower electrode 13 is formed. It is electrically connected to the substrate 100. It is explained here that since many of the methods used in the above processes are well-known techniques in traditional techniques such as lithography, etching, chemical vapor deposition, and physical vapor deposition The method and the like will not be described in detail here. Next, referring to the first figure B, the paper is deposited on the lower electrode 130 of ruthenium metal. CNS) A4 specification (210 X 297 g) κι 1234841 V. Description of the invention (an oxide layer or a photoresist layer 140 to fill and cover the ruthenium metal lower electrode 130 and each insulation layer opening 120. Then chemical mechanical polishing method The insulating layer opening 120 is cut, and the thickness of the chemical mechanical polishing method is as shown by the dashed line in the first B figure, in order to substantially remove the ruthenium metal lower electrodes 130 on the upper surfaces of the edges of both sides of the insulating layer opening 120. Then Then, the oxide layer or the photoresist layer 140 is removed by etching to complete the process of the electrode under the semiconductor capacitor structure. Referring to the first figure C, a dielectric layer 150, such as a Ta205 layer, is then deposited over the ruthenium metal lower electrode ι30. Among them, Ta (0C2H5) 5 is generally used for chemical vapor deposition to deposit an amorphous (Amorphous) pentoxide button film 15. After that, it is heated to red to provide energy to recrystallize the pentoxide button 150 to increase the dielectric constant of the pentoxide button 150. Among them, the aforementioned dielectric layer 15 can also be selected from one of Ti02, BST, SBT, and PZT. After the completion of the deposition of the second pentoxide film 150, the sputtering process of the upper electrode ι60 of the ruthenium metal is performed next to complete the MIM capacitor structure in the semiconductor device. Referring to the first diagram D, an adhesion layer 170 is then formed on the MIM capacitor. Firstly, by means of magnetron DC sputtering, a power of about 200 watts is used to form a titanium tungsten alloy layer composed of 5% to 15% by weight of titanium metal and 95% to 85% by weight of tungsten metal. In an environment with an air pressure of about 5 mTorr and a temperature of about 300 C ~ 400 ° C, a mixture of argon and nitrogen at a ratio of 90:10 was passed through to nitridize the titanium-tungsten alloy layer to A titanium tungsten nitride layer 172 having a thickness of about 50 to 300 angstroms. Next, continue with the previous steps. · Installation -------- Order --------- (Please read the notes on the back before filling out this page) 1234841 A7 B7 V. Description of the invention () (please read the precautions on the back before filling in this page), but stop the nitrogen flow to form a titanium tungsten alloy layer 174 with a thickness of about 20 ~ 100 angstroms at the nitriding Above the titanium-tungsten layer 172, the completed adhesion layer 170 can solve the problem of poor adhesion between the interface of the ruthenium metal upper electrode 160 and the subsequent barrier layer interface. Referring to the second figure, the X-ray diffraction schematic diagram of the titanium nitride tungsten layer in the adhesive multi-layer formed in the semiconductor capacitor structure of the present invention is described. The figure shows the process of sputtering titanium-tungsten alloy according to the ambient temperature. As the value increases, the peak value (Peak Value) of the titanium-tungsten nitride alloy gradually becomes apparent. Secondly, 'a barrier layer 180 is formed on the adhesive multilayer 170. In this embodiment, the barrier layer 180 may be a polycrystalline silicon layer' to achieve the effect of isolating the ruthenium metal material in the subsequent process. To prevent subsequent oxidation or pollution of ruthenium metal materials. Finally, a dielectric metal layer 190 is formed on the polycrystalline silicon barrier layer ι80, and a subsequent semiconductor device process is performed. According to the above description, in order to show the adhesive layer with good adhesion in the capacitor structure of the present invention, the third A to D diagrams respectively show the scanning electron microscope (SEM) magnification test of the comparative test without the adhesive layer and several adhesive layer materials. Results graph. Among them, the test environment is performed at a severe test temperature, such as: 7500c. The test results are described as follows: · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (1) If the upper electrode of ruthenium metal in the semiconductor capacitor structure is in direct contact with the polycrystalline silicon barrier layer, there is no adhesion mentioned above Floor. The test results are shown in the third graph A, which shows that due to high-temperature thermal expansion, multiple bumps are generated between the interface of the upper electrode of ruthenium metal and the compound silicon barrier layer, which shows the ruthenium metal in the semiconductor valley structure. Upper electrode and polycrystalline spar barrier layer The paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 x 297 meals) Λ7 1234841 5. Description of invention () The adhesion effect between () is not good. (2) If an adhesive cladding layer is added to the above semiconductor capacitor structure to form a ruthenium metal upper electrode, short nitride, tantalum metal, and polycrystallite barrier layer, the test results under the above test conditions are shown in Figure 3B. . Due to the high-temperature thermal expansion, multiple bumps are still generated between the interface of the ruthenium metal electrode and the polycrystalline silicon barrier layer. Although the number of protrusions has been reduced compared with the second A picture, the adhesion effect of tantalum nitride and button metal to improve the adhesion between the upper electrode of ruthenium metal and the barrier layer of polycrystalline silicon is not good. Significant. (3) If another adhesion layer is added to the above semiconductor capacitor structure to form a ruthenium metal upper electrode, titanium nitride, titanium metal, and a polycrystalline silicon barrier layer, the test results under the above test conditions are shown in the third C chart . Due to the high temperature thermal expansion, there are also multiple protrusions between the interface of the upper electrode of ruthenium metal and the barrier layer of the polycrystalline silicon. Compared with the third A picture, the number of protrusions is also reduced, but the The number of protrusions is also quite large, and the improvement effect is not significant. (4) The semiconductor capacitor structure disclosed in the present invention, that is, an adhesive multi-layer composed of a tungsten nitride layer and a titanium-tungsten alloy layer is arranged between the upper electrode of ruthenium metal and the polycrystalline silicon barrier layer. The test result is shown in the third D figure. That is, although the high-temperature thermal expansion test 'has produced only one bump between the upper electrode of ruthenium metal and the interface of the polycrystalline silicon barrier layer. It should be noted that this test is performed at the severe 75CTC test temperature. The results of this test show the number of protrusions. Compared with any of the previous test results in the third A to C chart, the electrode and the barrier layer of the present invention The quantity generated between the interfaces has been greatly reduced, and the improved adhesion effect is very significant. In fact, the temperature in the subsequent process of the present invention has not exceeded the equipment .-------- Order --------- ί Please read the precautions on the back before filling this page.) 12Printed by the Consumer Cooperative of the Property Bureau 10 1234841 A7 ------ V. Description of the invention () 400QC, the adhesion effect of the semiconductor capacitor structure disclosed in the present invention should be able to meet the requirements of the product manufacturing process. In summary, the capacitor structure disclosed in the present invention uses a barrier layer to isolate the oxidation or pollution of the ruthenium metal material in subsequent processes, and an adhesive multi-layer is used to solve the poor adhesion between the barrier layer and the ruthenium metal material. The problem also indirectly solves the problem of poor adhesion between the traditional ruthenium metal material and the dielectric metal dielectric layer, and achieves the purpose of raising the capacitance in the semiconductor device. As will be understood by those familiar with this technology, the above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. "Effective changes or modifications" should be included in the scope of patent applications described below. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

This paper size applies to China National Standard (CNS) A4 (210 X

(Please read the precautions on the back before filling this page) · Equipment ---------- Order ---------

Claims (1)

1234841 A8 B8 C8 D8 Printed by the Ministry of Economic Affairs 4 ^ 7¾Printed by Industrial and Consumer Cooperatives 6. Scope of patent application Patent scope: 1. A semiconductor structure with a metal / dielectric layer / metal (MIM) capacitor. The semiconductor structure contains at least : A substrate; an insulating layer on the substrate, and the insulating layer has at least one opening; a lower electrode of ruthenium, located on the bottom and inner sidewall surfaces of each of the insulating layer openings, and connected to the substrate It is electrically connected; a dielectric layer is located on the lower electrode of ruthenium metal and the upper surface of the insulating layer; an upper electrode of ruthenium metal is located on the dielectric layer; an adhesive layer is located on the upper electrode of ruthenium metal The adhesive layer includes: a titanium tungsten nitride layer on the ruthenium metal upper electrode; and a titanium tungsten alloy layer on the titanium tungsten nitride layer; a polycrystalline silicon barrier layer on the On the adhesive layer; and a metal dielectric layer (ILD) on the polycrystalline silicon barrier layer. 2. The semiconductor structure according to item 1 of the scope of patent application, wherein the above-mentioned titanium nitride tungsten layer is Nitridize — consisting of 5% to 15% of titanium metal and 95% to 85% of mineral metal A titanium crane alloy layer is formed. 3. The semiconductor structure according to item 1 of the scope of the patent application, wherein the thickness of the titanium nitride tungsten layer is about 50 to 300 angstroms. Please read the note at the back of the page I. The binding line and the paper scale are applicable to the Chinese national standard (CNS &gt; A4 size (210X 297 mm)) 1234841 8 8 8 8 ABCD patent application park 4. If the scope of patent application is item 1 The semiconductor structure in which the above-mentioned titanium-tungsten alloy layer is composed of 5% to 15% of titanium metal and 95% to 85% of tungsten metal. 5. The semiconductor structure according to item 1 of the patent application scope, wherein the above-mentioned titanium-tungsten layer The thickness of the alloy layer is about 20 to 100 angstroms. 6 · For the semiconductor structure in the first scope of the patent application, the above dielectric layer is selected from the group consisting of the following materials: Ta205, Ti02, BST, SBT, PZT One of the ethnic groups. Please read the note of ιδ-item before reloading. 7. If the semiconductor structure of the scope of patent application No. 1, the above substrate further includes the gate structure and source / drain region. 8 · 如The semiconductor structure according to item 1 of the patent application, wherein the above-mentioned insulating layer further includes a silicon oxide layer. 9. The semiconductor structure according to item 1 of the patent application, wherein the above-mentioned insulation layer opening further includes a crown-shaped structure. Printed by the Ministry of Line Economy, 4-3.5, and Industrial Cooperative Cooperative 10. A semiconductor structure with a capacitor using ruthenium metal as an electrode. The capacitor is located in the opening of an insulating layer of a semiconductor substrate. The semiconductor structure includes at least: Ruthenium metal lower electrode; a dielectric layer located on the ruthenium metal lower electrode and the upper surface of the insulating layer 13 dimensions. Commonly used Chinese national standard (CNS) A4 specification (210X 297 mm) A8 1234841 device D8 | VI. Application Patent Fan Yuan!! Above; a ruthenium metal upper electrode, located on the dielectric layer; (Please read the note on the back of the item Ϋ-item before washing this page) An adhesive layer, the adhesive layer also includes: A titanium tungsten nitride layer over the ruthenium metal upper electrode; and a titanium tungsten alloy layer over the titanium tungsten nitride layer; a polycrystalline silicon barrier layer over the adhesion cladding layer; and A metal dielectric layer is located on the polycrystalline silicon barrier layer. 11. The semiconductor structure according to item 10 of the patent application scope, wherein the above-mentioned titanium nitride crane layer is Nitridize—from 5% to 15 % Of titanium metal with 95% ~ 85% Titanium-tungsten alloy layer composed of tungsten metal. 12. The semiconductor structure according to item 10 of the scope of patent application, wherein the thickness of the above-mentioned titanium nitride tungsten layer is about 50 to 300 angstroms. Semiconductor structure, wherein the above-mentioned titanium-tungsten alloy layer is composed of 5% to 15% of titanium metal and 95% to 85% of tungsten metal. 14. The semiconductor structure according to item 10 of the patent application scope, wherein the above-mentioned titanium-tungsten layer The thickness of the alloy layer is about 20 to 100 angstroms. Printed by Wisdom of the Ministry of Economic Affairs / ^ Μ Industrial and Consumer Cooperatives 15. If the semiconductor structure under the scope of patent application No. 10, the above dielectric layer is selected from the following materials Ta205, Ti〇2, BST, SBT, One of the groups formed by PZT.氡 Paper string dimensions are generally Chinese National Standards (CNS) M specifications (210X 297 mm) A8 B8 C8 D8 1234841 6. Scope of patent application (please read the precautions on the back before washing this page) 16.—A kind of metal / Dielectric layer / metal capacitor semiconductor manufacturing method, the method includes at least the following steps: providing a substrate; forming an insulating layer on the substrate; forming at least one opening in the insulating layer; forming a ruthenium metal lower electrode on each The bottom and inner sidewall surfaces of the openings of the insulating layers are electrically connected to the substrate; a dielectric layer is formed on the lower electrode of the ruthenium metal and an upper surface of the insulating layer; and an upper electrode of the ruthenium metal is formed on the dielectric. Over the electrical layer; forming a titanium tungsten nitride layer over the ruthenium metal upper electrode; forming a first titanium crane alloy layer over the titanium nitride crane layer; forming a polycrystalline silicon barrier layer over On the adhesive layer; and forming a dielectric metal dielectric layer on the polycrystalline stone barrier layer. 17. The method according to item 16 of the patent application range, wherein the step of forming the titanium tungsten nitride layer further comprises sputtering the upper electrode of the ruthenium metal at a temperature between about 300 ° C and 400 ° C. , Forming a second titanium tungsten alloy layer composed of 5% to 15% of titanium metal and 95% to 85% of tungsten metal. Printed by the Ministry of Economic Affairs of the Intellectual Property Co., Ltd. 18. The method of claim 17 in the scope of patent application, wherein the step of forming the titanium nitride tungsten layer further includes nitritizing the second titanium tungsten alloy layer. Nine papers. ¾ scale applies to Chinese national standard (CNS M4 specification (210X 297 mm) 1234841 A8 B8 C8 D8 patent application country, 19. If the method of the 18th scope of the patent application, the above-mentioned method to form the titanium nitride tungsten The step of forming the layer further includes forming the gasification layer having a thickness of about 50 to 300 angstroms. 20. The method according to item 16 of the patent application scope, wherein the above-mentioned step of forming the first titanium tungsten alloy layer is more The titanium-tungsten nitride layer is sputter-formed at a temperature of about 300 ° C to 400 ° C to form a titanium alloy consisting of 5% to 15% titanium and 95% to 85% tungsten. The first titanium-tungsten alloy layer. 21. The method according to item 20 of the scope of patent application, wherein the step of forming the first crane alloy layer further includes forming the first titanium-tungsten layer with a thickness of about 20 to 100 angstroms. Alloy layer. 22. The method according to item 16 of the patent application, wherein the step of forming the dielectric layer further includes forming one selected from the group consisting of Ta205, Ti02, BST, SBT, and PZT. The dielectric layer. 2 3. The method of claim 16 in the patent scope, wherein the above is provided The step of the substrate further includes forming a gate structure and a source / drain region in the substrate. --------- ^! (Please read the note on the back-item before writing this page) When the Ministry of Wisdom, the Consumers ’Cooperative Cooperative, printed the special request, Shen Buru ’s 24-layer marginal enveloping package contains the method described above. The fragmentation of the layer 6 The oxygen method is described in the method Item 6 1 Fan Li specially requested to apply for the application of the Chinese National Standard (CNS) M specification (210 × 297 mm) 1234841 I --- 丨 VI. The scope of the patent application. Includes a step-by-step opening of the edge. The structure is structured to form a crown-equation system. The half-capacity type is a 26-electrode voltage. The bottom of the body has a base and a half of the surface of the guide. The upper layer of the surface must be completely polarized: the next step is to step down. The gold column ruthenium is powered down. One side is formed into the shape of the shape The upper layer fra should be at the pole ^ ¾ The upper layer is gold ruthenium ^-(Please read the notes on the back before filling in this page) The Ministry of Economic Affairs, Smart Money, -l ^ jm Industrial Cooperative Cooperative Printed to form an adhesive layer, It further includes: forming a titanium tungsten nitride layer on the ruthenium metal upper electrode; and forming a ^ th Qinhe alloy layer on the gasified Qinhe layer 'forming a polycrystalline silicon barrier layer on the Adhering to the cladding layer; and forming a dielectric metal dielectric layer on the crystalline silicon barrier layer. 27. For the method of claim 26 in the scope of patent application, wherein the step of forming the titanium tungsten nitride layer further includes forming a flash plating method on the ruthenium metal upper electrode at a temperature between about 300 ° C and 400oC, A second titanium tungsten alloy layer composed of 5% to 15% titanium metal and 95% to 85% tungsten metal. 28. The method of claim 26, wherein the step of forming the titanium tungsten nitride layer further includes nitriding the second titanium tungsten alloy layer. t Paper size applies to Chinese national standard () A4 size (210X297 mm) A8 B8 C8 D8 (2) Applying for a patent application Fan Guo 1234841 The second example is the method of claim 28, wherein the step of forming the titanium nitride tungsten layer further includes forming a titanium tungsten layer with a thickness of about $ 50 ~ 3. * <Communication 30. The method of applying patent scope 帛 26, wherein the above-mentioned step of forming the -titanium-tungsten alloy layer further includes sputtering on the titanium-tungsten nitride layer at a temperature of about 30. Between 0 ° C and 400 ° c, the first titanium-tungsten alloy composed of 5% to 95% of titanium metal and 95% to 85% of tungsten metal is formed. 31. If the scope of patent application is 帛 30, the method The step of forming the first titanium-tungsten alloy layer described above further includes forming the first titanium-tungsten alloy layer with a thickness of about 200˜100 Angstroms. 32. The method according to item 26 of the scope of patent application, wherein the step of forming the dielectric layer further includes forming the medium selected from one of the group consisting of Ta205, Ti02, BST, SBT, and PZT. Electrical layer. ^ ------ 1T ------ ^ (please read the note on the back first and then fill in this page) Ministry of Economic Affairs, Smart Wealth 4 ^ ¾Printed by Industrial and Consumer Cooperatives, Paper: ¾-foot leather China National Standard i CNS) / U specifications (210X 297 mm)