1234350 五、發明說明（1) 發明所屬之技術領域： 本發明係有關於一種具負回授之差動電壓產生器，特 別有關於一種應用於類比數位轉換器之差動電壓產生器。 先前技術： 切換式電容類比數位轉換器可提供快速且具效率的類 比數位轉換功能’如第1圖所示，係為一典型之切換式電 容類比數位轉換器10，其係為管線式多級（multi —stage pipelined )的電路，圖中包括了第一級u至第!^級12，每 一級11 1 2皆提供了一至數位元的數位資料至一數位修正 電路1 5 ’使輸入之類比訊號1 7經每一級11 1 2轉換成對應 之數位訊號，其中，該每一級11 1 2係為一切換式電容電 路，根據每一級11 1 2所響應之時脈訊號（例如：ph丨i以 及Phi 2)去跟一類比的臨界參考電壓及\心比較，以產 生數位輸出訊號。 因此，為了使類比數位轉換器1 〇能正常運作，需要相 位及時脈訊號產生器2 0以及參考電壓產生器3 〇以產生相位 及時脈訊號以及參考電壓。因此，相位及時脈訊號產生号 20用來產生相位（41 )phi 1以當作每一級η 12的取樣相 位；及產生時脈（0 2)phi 2以當作每一級11 12的取樣時1234350 5. Description of the invention (1) The technical field to which the invention belongs: The present invention relates to a differential voltage generator with negative feedback, and particularly to a differential voltage generator applied to an analog digital converter. Prior art: Switched-capacitor analog-to-digital converters can provide fast and efficient analog-to-digital conversion functions. 'As shown in Figure 1, it is a typical switched-capacitor analog-to-digital converter 10, which is a pipelined multistage (Multi-stage pipelined) circuit, the figure includes the first stage u to the first stage 12; each stage 11 1 2 provides one to a few digits of digital data to a digital correction circuit 1 5 'to make the analog of input The signal 1 7 is converted into a corresponding digital signal by each stage 11 1 2, wherein each stage 11 1 2 is a switched capacitor circuit, and according to the clock signal responded by each stage 11 1 2 (for example: ph 丨 i And Phi 2) compare it with an analog critical reference voltage and the core to generate a digital output signal. Therefore, in order for the analog-to-digital converter 10 to operate normally, a phase clock signal generator 20 and a reference voltage generator 30 are required to generate a phase clock signal and a reference voltage. Therefore, the phase and clock signal generation number 20 is used to generate phase (41) phi 1 as the sampling phase of each stage η 12; and the clock (0 2) phi 2 is used as the sampling time of each stage 11 12
脈。參考電壓產生器30則用來產生參考電壓及V f以A 作每一級11 1 2的參考電壓。本發明即是有關於P該參考電@ 壓產生器30。 第2圖係顯示一傳統之參考電壓產生器3 〇，用以產生 一參考電壓Vrefp，標號31的電路與標號30相同，其用以產pulse. The reference voltage generator 30 is used to generate a reference voltage and V f with A as the reference voltage of each stage 11 1 2. The present invention is related to the reference voltage @voltage generator 30. FIG. 2 shows a conventional reference voltage generator 3 0 for generating a reference voltage Vrefp. The circuit with reference number 31 is the same as the reference number 30.
0697-1024nW(nl);P2003-014-TlV-A;MIKE6277.ptd 第 5 頁 1234350 發明說明（2) 生另一參考電壓vrefn。參 電壓源V+盥電产嗎可 座生益30包含有一連接於 π仫I拉^ 之間之源極隨輕器32，1中嗲雷^馬 3 5係麵接至接地端 中4電机源 的驅動，經過=回=隨：器32的閉極則受放大器“ 輸出的參考電壓V，么接〜放大器34的輪入端，並以其 極隨麵器3 2可提ΓΛ /Λ Λ 電壓。如此，該源 路使；出電壓維持在和電壓U相關的電壓1準由上負回 因為=率用Γ高速類比數位轉換器中， 午扪切換會產生雜訊/干擾，因此需加一大雷交 值之外部電容cEXT去濾掉高頻，然而此種 積且需要增加一額外的接腳（PIN)。 用電路面 一第3圖所不則為另一習知的參考電壓產生器，如圖所 不，此產生器係使用一運算放大器4〇(〇P-AMp)，經由 授將輸出接回至反向端（inverted terminai)。 、° ^ 雖然上述運算放大器不需要外部電容即可運用在高頻 寬的電路上，但是運算放大器耗電量較大，且所 面積亦較大。 $路 發明内容： 有鑑於此，本發明的目的就在於提供一可降低耗電量 且縮小電路面積之參考電壓產生器。 為達上述目的，本發明提供一參考電壓產生器，其具 有一輸出端俾產生一輸出電壓，係包括：一位移器，接收 一第一參考電壓並產生一位移使該輸出端上的輸出電壓位 移於該第一參考電壓與該輸出電壓之間；及一回授電路，0697-1024nW (nl); P2003-014-TlV-A; MIKE6277.ptd page 5 1234350 Description of the invention (2) Generate another reference voltage vrefn. The reference voltage source V + is an electric power generator. The product 30 contains a source connected between π 仫 I and ^^, a light source 32,1, a thunder, a horse 3, and a 5 series surface connected to a ground. 4 a motor Driven by the source, the closed pole of the device 32 is subject to the reference voltage V output by the amplifier, so it is connected to the wheel-in terminal of the amplifier 34, and its pole follower 32 can be raised ΓΛ / Λ Λ In this way, the source circuit keeps; the output voltage is maintained at a voltage 1 related to the voltage U. It is returned from the top to the negative because the rate is Γ. In high-speed analog digital converters, noisy switching will generate noise / interference. An external capacitor cEXT with a large lightning value is used to filter out high frequencies, but this product requires an additional pin (PIN). Using a circuit surface as shown in Figure 3 is not generated for another conventional reference voltage. As shown in the figure, this generator uses an operational amplifier 4〇 (〇P-AMp), and the output is returned to the inverted terminai through the input. 、 ° ^ Although the above operational amplifier does not require external capacitors It can be used in high-frequency circuits, but the op amp consumes more power and has a larger area. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a reference voltage generator capable of reducing power consumption and circuit area. To achieve the above object, the present invention provides a reference voltage generator having an output terminal. Generating an output voltage includes: a shifter that receives a first reference voltage and generates a displacement to shift the output voltage on the output terminal between the first reference voltage and the output voltage; and a feedback circuit,
1234350 五、發明說明（3) ί ί ϊ ΐ ί電壓及一第二參考電壓去控制該位移使該輸出 更明續為易了僅讓本Λ明Λ上述和其他目的、特徵、和優點能 作詳細說明如下： f又佳κ轭例，並配合所附圖示， 實施方式： 來老Ϊ4Λ係顯。示本發明—較佳實施例之電路示意圖，該 sl.f/1產生益係包括分壓電路5、一位移器6(ievei Shlfter)、一回授電路7，以及一遽波器8。1234350 V. Description of the invention (3) ί ί ϊ ΐ ί voltage and a second reference voltage to control the displacement to make the output more concise and easy. Only the above and other purposes, features, and advantages of this Λ 明 Λ can be made. The detailed description is as follows: f is a good κ yoke example, and in conjunction with the attached figure, implementation mode: Lailao Ϊ4Λ system display. A circuit diagram of the preferred embodiment of the present invention is shown. The sl.f / 1 generating benefit system includes a voltage divider circuit 5, a shifter 6 (ievei Shlfter), a feedback circuit 7, and an echo waver 8.
^CC :壓電路5由電阻R,及匕所組成，其係耦接至一電壓源 用以，生一參考電及另一參考電㈣㈣。 位移益6包含有一當作源極隨耦器之_s電晶體6〇， 二電流源之NM0S電晶體61以及一當作定電流源之腿仍 電曰曰體62 ;其巾該NM0S電晶體6〇的㈣極係減到一電壓 ，，其源極當作-輸出端63，問極則為—輸人端俾用以 接收該第一參考電壓。眾所皆知的是，當一電晶體的 閘極做為輸入端，源極當作其輸出端時，則豆電晶體可告 作一源極隨耦器。即該源極隨耦器的輸出會與輸入端有二 固疋的電壓差vgs並π跟隨π其輸入端的電壓位移。此位移量 決定於源極隨耦器的偏壓值，位移器6中的位移量即由源 極隨耦器60所決定。在第4圖中，二電流源61、62決定流 經電晶體60的電流，其中電晶體61為可控電流源，電晶體 62則為定電流源，NM0S電晶體61具有一汲極端連接至輸出 端63，一源極端耦接至接地端（GND)，以及一閘極連接至^ CC: The voltage circuit 5 is composed of a resistor R and a dagger, which is coupled to a voltage source for generating a reference voltage and another reference voltage. Displacement benefit 6 includes a _s transistor 60 which is a source follower, a NM0S transistor 61 which is a current source, and a leg 62 which is a constant current source. The NM0S transistor is The 〇 pole of 60 is reduced to a voltage, and its source is regarded as the-output terminal 63, and the interrogation pole is-the input terminal is used to receive the first reference voltage. It is well known that when the gate of a transistor is used as the input terminal and the source is used as its output terminal, the soybean transistor can be regarded as a source follower. That is to say, the output of the source follower and the input terminal have a fixed voltage difference vgs and π follows the voltage displacement of the input terminal. This amount of displacement is determined by the bias value of the source follower, and the amount of displacement in the displacer 6 is determined by the source follower 60. In Figure 4, two current sources 61 and 62 determine the current flowing through the transistor 60. The transistor 61 is a controllable current source and the transistor 62 is a constant current source. The NMOS transistor 61 has a drain terminal connected to Output terminal 63, a source terminal is coupled to the ground terminal (GND), and a gate is connected to
1234350 五、發明說明（4) Ϊ = 出端，瞧電晶體62則連接於輸出端63 及接地埏（或低電源端）之間。 71該:中授Λ路:包括有一差動放大器70以及-低通渡波器 、中:差動放大器70包括有一反向輪入端（inverted 1ΠΡ^ 非反向輸入端（non-i nverted input)及一輸 5端2 Γί非反向輸入端係耦接至該位移器6的輸出端 63，该反向輸入端則接收一第二參考電壓、η ,其 Π J_S電晶體61俾控制其電壓的偏移量。該低通濾 ί )的電容:接於位移器6輸入端以及一接地端(低電源 =際操作時，若t輸出端63上的電壓位準❹高（Μ" 大於第二參考電壓時aut>Vref2)，該差動放大器 70輸出知上的差動電壓會增大，增大之電壓值使得在電晶 ^61閘極端上的電壓增加’並使得流經電晶體“的電流量 增加。除此之外，因為輸出端63的電壓位準被拉高，使得 二IT曰0上間-源極接面上的電壓降低’進而使得流經 a阳體60的電流減小。因為，流經電晶體6丨的電流增 加及&經電晶體6〇的電流下降，使得輸出端Μ上的電壓會 被下拉:直到當輸出端電壓等於參考電壓（ν_ = ν^2)。相 反的，當輸出端63上的電壓位準被拉低而小於參考電壓時 (V〇ut < Vref2 )，連帶的該差動放大器非反向輸入端的電壓 曰被拉，並使传差動放大器70輸出端上的電壓下降，使 間極電壓下降而使得流經電晶體61的電流量減少；除此之 外因為輪出端6 3的電壓位準被拉低，使得電晶體6〇閘一1234350 V. Description of the invention (4) Ϊ = output terminal, the transistor 62 is connected between the output terminal 63 and the ground terminal (or low power terminal). 71 This: Middle Λ Road: Includes a differential amplifier 70 and -low-pass ferrule, Medium: The differential amplifier 70 includes an inverted round-in terminal (inverted 1ΠP ^ non-i nverted input) And an input 5 terminal 2 Γί non-inverting input terminal is coupled to the output terminal 63 of the shifter 6, the inverting input terminal receives a second reference voltage, η, whose Π J_S transistor 61 电压 controls its voltage The capacitance of the low-pass filter: is connected to the input of the shifter 6 and a ground (low power = international operation, if the voltage level at the output 63 of the t is high (M " greater than the first When the reference voltage is aut > Vref2), the differential voltage on the output of the differential amplifier 70 will increase, and the increased voltage value will increase the voltage at the gate of the transistor 61, and will flow through the transistor " In addition, because the voltage level of the output terminal 63 is pulled up, the voltage at the upper-source interface of the two ITs is reduced, and the current flowing through the anode 60 is reduced. Because the current flowing through transistor 6 丨 increases and the current through transistor 60 decreases, the output terminal The voltage on M will be pulled down: until when the output voltage is equal to the reference voltage (ν_ = ν ^ 2). Conversely, when the voltage level on the output 63 is pulled lower than the reference voltage (V〇ut < Vref2), the voltage of the non-inverting input terminal of the differential amplifier is pulled, and the voltage at the output terminal of the differential amplifier 70 is reduced, the inter-electrode voltage is reduced, and the amount of current flowing through the transistor 61 is reduced; In addition, because the voltage level of the wheel output 63 is pulled down, the transistor 60 is turned off.
1234350 五、發明說明（5) $ f接面上的電壓升高，進而使得流經關〇§電晶體6〇的電 /’il 2加。因為流經電晶體6 1的電流下降及流經電晶體6 〇的 電流增加，使得輸出端63上的電壓會被拉回，直到當輸出 端電壓等於參考電壓（V_ = v_)。 、 藉由上述，藉由位移器6中電晶體60及電晶體61可快 速，穩定的控制輸出電壓的位移，且此設計不需要外部 電谷。因此’本發明可提供較小的電路面積及較低的耗電 量。 .本發明亦可應用於全差動電壓產生器（fu 1 1 y differential reference voltage generators)上，如第1234350 V. Description of the invention (5) The voltage on the $ f junction rises, which in turn causes the electricity flowing through the transistor 60 to increase / 'il 2 plus. Because the current flowing through the transistor 61 decreases and the current flowing through the transistor 60 increases, the voltage at the output terminal 63 will be pulled back until the voltage at the output terminal is equal to the reference voltage (V_ = v_). Based on the above, the transistor 60 and the transistor 61 in the displacer 6 can quickly and stably control the displacement of the output voltage, and this design does not require an external valley. Therefore, the present invention can provide a smaller circuit area and a lower power consumption. The present invention can also be applied to full differential voltage generators (fu 1 1 y differential reference voltage generators), such as
5圖所示’其係由兩差動放大器所組成，係包括二位移器 6、6 ，二回授電路7、7’ ，及二濾波器8、8，。其中龍0S 1晶體60、61及62的電路係與前一實施例相同，在此不再 資述，本實施例主要不同處係為分壓電路5，具有一電壓控 制輸出vcm以控制第二參考電壓Vref2及第四參考電壓電壓 位準；位移器6’的電晶體元件全部皆為PM0S電晶體。其中 位移器6’具有一當作源極隨耦器之PM0S電晶體6〇，，一當 作電流源之PM0S電晶體6 1，以及一當作定電流源之pm〇s電 晶體62’ ；其中該PM0S電晶體6〇’的汲極係耦接到一接地端 (GND)，其源極當作一輸出端63，，閘極則為一輸入端俾用 以接收一第四參考電壓VreH。該PM0S電晶體61，為可控電流 源’電晶體62’則為定電流源，PM0S電晶體61，具有一汲極 端連接至輸出端6 3 ’ ，一源極端耦接至電壓源（ycc)，以及 閘極連接至該回授電路了，的輸出端’pjjOS電晶體62，則 1麵 0697-1024nW(nl);P2003-014-Bf-A;MIKE6277.ptd 第 9 頁 1234350__ 五、發明說明（6) 連接於輸出端6 3 ’及電壓源（Vcc:)之間。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。As shown in Fig. 5 ', it is composed of two differential amplifiers, including two shifters 6, 6, two feedback circuits 7, 7', and two filters 8, 8. The circuit of the Dragon 0S 1 crystal 60, 61, and 62 is the same as the previous embodiment, and will not be described here. The main difference in this embodiment is the voltage dividing circuit 5, which has a voltage control output vcm to control the first The second reference voltage Vref2 and the fourth reference voltage voltage level; all the transistor elements of the shifter 6 'are PMOS transistors. The shifter 6 'has a PM0S transistor 60 as a source follower, a PM0S transistor 61 as a current source, and a PM0s transistor 62' as a constant current source; The drain of the PM0S transistor 60 ′ is coupled to a ground terminal (GND). The source is regarded as an output terminal 63, and the gate is an input terminal. It is used to receive a fourth reference voltage VreH. . The PM0S transistor 61 is a controllable current source, and the transistor 62 is a constant current source. The PM0S transistor 61 has a drain terminal connected to the output terminal 6 3 ′ and a source terminal coupled to a voltage source (ycc). , And the gate is connected to the feedback circuit, the output terminal 'pjjOS transistor 62, then one side 0697-1024nW (nl); P2003-014-Bf-A; MIKE6277.ptd Page 9 1234350__ 5. Description of the invention (6) Connected between the output terminal 63 'and the voltage source (Vcc :). Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
0697-10241TWF(nl);P2003-014-HV-A;MIKE6277.ptd 第10頁 1234350 圖式簡單說明 第1圖所示係為一習知之切換式電容類比數位轉換器； 第2圖係顯示一傳統之參考電壓產生器； 第3圖所示則為另一習知的參考電壓產生器； 第4圖係顯示本發明一較佳實施例之電路示意圖； 第5圖係顯示本發明另一較佳實施例之電路示意圖。 相關符號說明： 1 0〜類比數位轉換器； 11〜第一級； 1 2〜第k級； 1 5〜數位修正電路； 2 0〜相位及時脈訊號產生器； 30、31〜參考電壓產生器； 3 2〜源極隨耦器； 34〜放大器； 3 5〜電流源； 40〜運算放大器； 5〜分壓電路； 6、6 ’〜位移器； 60、61、62 〜NMOS 電晶體； 63〜輸出端； 7〜迴授電路； 70〜差動放大器； 7 1〜低通濾、波器；0697-10241TWF (nl); P2003-014-HV-A; MIKE6277.ptd Page 10 1234350 Brief description of the diagram Figure 1 shows a conventional switched capacitor analog-to-digital converter; Figure 2 shows a Traditional reference voltage generator; Figure 3 shows another conventional reference voltage generator; Figure 4 shows a schematic circuit diagram of a preferred embodiment of the present invention; Figure 5 shows another comparison of the present invention Circuit diagram of the preferred embodiment. Explanation of related symbols: 10 ~ analog digital converter; 11 ~ first stage; 12 ~ kth stage; 15 ~ digital correction circuit; 20 ~ phase clock signal generator; 30, 31 ~ reference voltage generator ; 3 2 ~ source follower; 34 ~ amplifier; 3 5 ~ current source; 40 ~ operational amplifier; 5 ~ voltage divider circuit; 6, 6 '~ shifter; 60, 61, 62 ~ NMOS transistor; 63 ~ output end; 7 ~ feedback circuit; 70 ~ differential amplifier; 7 1 ~ low pass filter, wave filter;
0697-1024nW(nl);P2003.014-Tlf.A;MIKE6277.ptd 第11頁 1234350 圖式簡單說明 8、8 ’〜濾波器； 60’ 、61 ’ 、62’ 〜PM0S 電晶體 ΐ^Β 0697-10241TW(nl);P2003-014-TW-A;MIKE6277.ptd 第12頁0697-1024nW (nl); P2003.014-Tlf.A; MIKE6277.ptd Page 11 1234350 Schematic description of 8, 8 '~ filter; 60', 61 ', 62' ~ PM0S transistorΐ ^ Β 0697 -10241TW (nl); P2003-014-TW-A; MIKE6277.ptd Page 12