1233644 (1) 玖、發明說明 【發明所屬之技術領域】 本發明是有關於電漿蝕刻具有矽膜與鄰接在矽膜的無 機材料膜的半導體晶圓等的被處理基板的矽膜的電漿蝕刻 方法及裝置。 【先前技術】 在半導體裝置的製造工程方面，乃在半導體晶圓上形 成多結晶矽膜等的矽膜或絕緣膜等的多層膜後，施行電漿 蝕刻，形成所定的配線圖案。 爲了施行此種電漿蝕刻，使用各種裝置。其中以容量 結合型平行平板電漿蝕刻裝置爲主流。容量結合型平行平 板電漿處理裝置是在處理室內配置一對平行平板電極（上 部及下部電極），處理氣體同時導入處理室內，對電極的 至少一方施加高頻電力，而在電極間形成高頻電場。經由 該高頻電場形成處理氣體的電漿，針對被處理基板施行電 漿飽刻處理。 於此種電漿處理裝置中，是對下部電極供給13.56〜 4 Ο Μ Η z左右的高頻電力，並施行蝕刻。 在此種條件下，以例如Si02等的無機系材料膜作爲 遮罩，並用來蝕刻多結晶矽膜等矽膜的時候，爲了針對無 機材料膜提高蝕刻選擇比，故以較高壓的壓力條件進行蝕 刻。 但是像習知以較高壓的壓力條件進行蝕刻的時候，雖 -7- 1233644 (2) 然針對矽膜的無機材料膜提高蝕刻選擇比，但會有蝕刻形 狀控制性差的問題。此種問題不光是以無機材料膜作爲遮 罩而用的時候，就連在矽膜的基層形成無機材料膜的時候 也同樣會發生。 【發明內容】 本發明是有鑑於相關事情的發明，其目的在於提供一 種蝕刻鄰接在無機系材料膜的矽膜之際，能夠依然維持高 蝕刻選擇比，且形狀控制性良好的電漿蝕刻方法及裝置。 若根據本發明人等的檢討結果，多結晶矽膜等的矽膜 蝕刻，會受到電漿密度的支配，對於離子能量的助益小， 且Si 02或SiN膜等的無機系材料膜的蝕刻，需要電漿密 度與離子能量這兩者。因而電漿密度高，且離子能量低於 某種程度的話，針對無機系材料膜的矽膜就能提高蝕刻選 擇比。此時，電漿的離子能量是間接性地與蝕刻之際的電 極的自我偏壓電壓配合。因而，爲了針對無機系材料膜的 矽膜提高蝕刻選擇比，故結局是需要在高電漿密度且低偏 壓的條件下進行蝕刻。 一方面，爲了使蝕刻的形狀控制性變良好，故製程需 要以低壓進行。但是在上述條件的時候，就能在更低壓的 製程實現高蝕刻選擇比。亦即只要能實現高電漿密度及低 自我偏壓電壓，就能在更低壓條件下針對無機系材料膜的 矽膜提高蝕刻選擇比，就能使高蝕刻選擇比和良好的蝕刻 形狀控制性倂立。 1233644 (3) 若根據本發明人等的更進一步檢討結果，明確判斷施 加於電極的高頻電力的頻率很高的話，就能實現電漿密度 高且自我偏壓電壓小的狀態。 本發明乃爲一種電漿蝕刻方法，其特徵爲： 具備有：於處理室內面對面配置一對電極，且在兩電 極間配置著鄰接有矽膜與無機材料膜的被處理基板地，利 用一方的電極來支撐該被處理基板的配置工程；和對至少 一方的電極施加高頻電力，並於前述一對電極間形成高頻 電場的同時，對處理室內供給處理氣體，且經由前述電場 形成處理氣體的電漿，且經由該電漿對前述被處理基板的 前述矽膜施以電漿蝕刻的蝕刻工程；於前述蝕刻工程中， 施加在前述至少一方的電極的高頻電力的頻率爲50〜 1 5 0MHz。 若根據本發明，施加於電極的高頻電力的頻率爲50〜 15 0MHz，比習知高的緣故，即使在更低壓的條件下，還 是能實現高電漿密度與低自我偏壓電壓，矽膜就能針對無 機系材料膜以高蝕刻選擇比且良好的形狀控制性來蝕刻。 施加於電極的高頻電力的頻率爲7〇〜100MHz，特別 是1 00MHz更好。 而於前述蝕刻工程中，前述高頻電力的功率密度以 0.15 〜5W/ cm2爲佳。 而於前述蝕刻工程中，前述處理室內的電漿密度以5 xlO9 〜2xl01Gcm·3爲佳。 而於前述蝕刻工程中，前述處理室內的壓力以〗3. 3 Pa -9 - 1233644 (4) 以下爲佳。 而本發明乃爲一種電漿蝕刻方法，其特徵爲： 具備有：在處理室內面對面配置一對電極，且在兩電 極間配置著鄰接有矽膜與無機材料膜的被處理基板地，利 用一方的電極來支撐該被處理基板的配置工程；和對至少 〜方的電極施加高頻電力，並於前述一對電極間形成高頻 電場的同時，對處理室內供給處理氣體，且經由前述電場 形成處理氣體的電漿，經且由該電漿對前述被處理基板的 前述矽膜施以電漿蝕刻的蝕刻工程；於前述蝕刻工程中， 處理氣體爲包括HBr氣體及Cl2氣體的任一種，前述處理 室內的電漿密度爲5xl09〜2xl01GcnT3，且電極的自我偏 壓電壓爲200V以下。 若根據本發明，在以前述處理室內的電漿密度爲5χ 1〇9〜2xl01C)Cnr3，且電極的自我偏壓電壓爲200V以下的 條件下，形成包括HBr氣體及<：12氣體的任一種氣體的電 漿的緣故，就能針對無機系材料以高蝕刻選擇比且良好的 形狀控制性來蝕刻矽膜。 以上，前述無機系材料膜是由例如矽氧化物、矽氮化 物、矽酸氮化物以及矽碳化物的至少一種所形成。 而前述高頻電力以施加於支撐前述被處理基板的電極 爲佳。此時，可使支撐被處理基板的電極，重疊於前述高 頻電力’並施加3.2〜13.56MHz的第二高頻電力。像這樣 藉由重疊更低頻率的第二高頻電力，就能調整電漿密度以 及離子引入作用，確保相對於無機系材料膜的蝕刻選擇比 -10- 1233644 (5) 外，還可令矽膜的鈾刻速率更爲上昇。 重疊的第二高頻電力以13·56ΜΗζ爲佳。重疊 電力的頻率爲13.56MHz的時候，其功率密度以〇 cm2以下爲佳。而施加3. 2〜13·56ΜΗζ的第二高頻 時候，支撐前述被處理基板的電極的自我偏壓 200V以下爲佳。 而本發明乃爲一種電漿蝕刻裝置’其特徵爲： 具備有：收容鄰接有矽膜與無機系材料膜的被 板的處理室、和設在前述處理室內，其一方支撐著 處理基板的一對電極；和對前述處理室內供給處理 處理氣體供給系統；和對前述處理室內施以排氣的 統；和對前述電極中的至少一方供給電漿形成用的 力的高頻電源；由前述高頻電源所產生的高頻電力 爲 50 〜150MHz。 由前述高頻電源所產生的高頻電力的頻率 10 0MHz，特別是以100MHz爲佳。 最好前述®頻電力的功率密度爲0.15〜5W / cm 而前述處理室內的壓力以13.3Pa以下爲佳。 而最好是對支撐前述被處理基板的電極施加前 電力。 而最好前述電漿蝕刻裝置是更具備有：使支撐 處理基板的電極，重疊於前述高頻電力，並施力 13.56MHz的第二高頻電力的第二高頻電源。此時 前述第二局頻電力的頻率爲13·56ΜΗζ。而最好前 的高頻 • 64 W/ 電力的 電壓以 處理基 前述被 氣體的 排氣系 高頻電 的頻率 爲70〜 述高頻 前述被 □ 3 · 2 〜 ，最好 述第二 -11 - 1233644 (6) 高頻電力的功率密度爲0.64W/cm2以下。 可是，自帕申定律 （Paschen’s law)，放電開始電壓 VS是於氣體壓力p和電極間距離d之積pd爲某値時取得 極小値（帕申最小値），取得帕申最小値的積pd之値則是 高頻電力的頻率愈大就愈小。因而，高頻電力的頻率很大 的時候，放電開始電壓VS很小，放電很容易而穩定的緣 故，氣體力壓力P爲一定的話，需要縮小電極間距離d。 因此，本發明以電極間距離未滿5 0mm爲佳。而電極間距 離未滿50mm，就能縮短在處理室內的氣體滯留時間。藉 此、反應生成物就會很有效率地被排出，也可獲得減低蝕 刻停止的效果。 而最好更具備有：在前述一對電極間的電漿區域周圍 形成磁場的磁場形成手段。 施加的高頻電力的頻率很高的時候，蝕刻速率會產生 周邊部比給電位置的中央部還高的現象，但藉由在一對電 極間的電漿區域周圍形成磁場，發揮電漿封閉效果，即使 施加的高頻電力的頻率很高的時候，處理空間的被處理基 板的蝕刻速率，在被處理基板的邊緣部（周邊部）和中央部 是大致相等的。亦即蝕刻速率可均勻化。 前述磁場形成手段是形成在前述一對電極間的電漿區 域周圍的磁場強度以0.03〜0·045Τ(3 00〜450Gauss)爲佳。 而在支撐被處理基板的電極周圍設有聚焦環，前述電 漿區域周圍形成磁場之際，聚焦環上的磁場強度爲 O.OOlT(lOGauss)以上，被處理基板上的磁場強度以o.ooi 丁 -12- 1233644 (7) 以下爲佳。 藉由聚焦環上的磁場強度爲0.001T以上，在聚焦環 上產生電子的漂移運動，周邊部的電漿密度就會上昇，電 漿密度就會均勻化。一方面，藉由被處理基板上的磁場強 度爲實際上不會影響被處理基板的0.001T以下，就能防 止充電損耗。 【實施方式】 實施發明的最佳形態 以下參照所附圖面針對本發明的實施形態做說明。 第1圖是表示用於本發明實施的電漿蝕刻裝置的斷面 圖。該蝕刻裝置是構成氣密，具備有由小徑的上部1 a與 大徑的下部1 b所形成的段差的圓筒狀處理室1。處理室i 的壁部是例如鋁製品。 在處理室1內設有水平支撐被處理基板的晶圓W的支 撐台2。支撐台2是用例如鋁所構成，介著絕緣板3被支撐 在導體的支撐台4上。並在支撐台2的上方外周設有以導電 性材料或絕緣性材料所形成的聚焦環5。晶圓W的直徑爲 200mm的時候，聚焦環5以240〜2 8 0mm爲佳。支撐台2、 絕緣板3、支撐台4以及聚焦環5是利用包括滾珠螺桿7的滾 珠螺桿機構成爲可昇降。支撐台4下方的昇降驅動部分是 用不銹鋼（SUS)製的波紋管8覆蓋。處理室1是接地。而在 支撐台2中設有冷媒流路（圖未示），可冷卻支撐台2。而在 波紋管8的外側設有波紋管套9。 -13- 1233644 (8) 在支撐台2的略中央連接著供給高頻電力的給 。在該給電線1 2介著匹配箱1 1連接高頻電源1 〇。由 源1 〇將所定頻率的高頻電力供給至支撐台2。一方 支撐台2的上方互相平行地面對面的設有後述的淋 16。淋浴噴頭16接地。因而支撐台2是作爲下部電 能，且淋浴噴頭1 6是作爲上部電極的機能，亦即3 與淋浴噴頭16是構成一對平板電極。 再者，該些電極間的距離以設定在未滿5 0 m m 其理由乃如下所示。 根據帕申定律（Paschen’s law)，放電開始電壓 在氣體壓力P與電極間距離d之積pd爲某値時獲 値（帕申最小値），爲帕申最小値之積pd的値則是 力的頻率愈大就愈小。因而，如本實施形態，高頻 頻率很大的時候，爲了使放電開始電壓VS變小， 電且穩定，若氣體壓力p爲一定的話，就須要縮小 距離d。因此，電極間距離以未滿5 0 mm爲佳。而 距離未滿50mm，就能縮短在處理室內的氣體滯留 藉此能有效排出反應生成物，也可獲得減低蝕刻停 而且電極間距離變小的話，被處理基板的晶圓 表面的壓力分佈（中心部與周邊部的壓力差）變大。 會發生蝕刻均勻性降低等問題。爲了不按氣體流量 差小於0.2 7Pa(2mTor〇，電極間距離以35mm以上爲 在支撐台2的表面上設有靜電吸附晶圓W的靜 電線1 2 高頻電 面，在 浴噴頭 極的機 €撐台2 爲佳。 VS會 得極小 局頻電 電力的 容易放 電極間 電極間 時間。 止的效 W的 此時， 使壓力 佳。 電夾頭 -14- 1233644 (9)1233644 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a plasma for etching a silicon film of a substrate to be processed such as a semiconductor wafer having a silicon film and an inorganic material film adjacent to the silicon film. Etching method and device. [Previous technology] In the semiconductor device manufacturing process, a silicon film such as a polycrystalline silicon film or a multilayer film such as an insulating film is formed on a semiconductor wafer, and then plasma etching is performed to form a predetermined wiring pattern. In order to perform such a plasma etching, various devices are used. Among them, a capacity-combined parallel plate plasma etching apparatus is the mainstream. The capacity-combined parallel plate plasma processing device is a pair of parallel plate electrodes (upper and lower electrodes) arranged in the processing chamber. The processing gas is introduced into the processing chamber at the same time. High-frequency power is applied to at least one of the electrodes to form high-frequency between the electrodes. electric field. A plasma of a processing gas is formed through the high-frequency electric field, and a plasma saturation treatment is performed on a substrate to be processed. In this type of plasma processing apparatus, high-frequency power of about 13.56 to 4 Μ Η z is supplied to the lower electrode and etching is performed. Under such conditions, when an inorganic material film such as Si02 is used as a mask and is used to etch a silicon film such as a polycrystalline silicon film, in order to improve the etching selection ratio for the inorganic material film, it is performed under a higher pressure condition. Etching. However, when it is known that etching is performed under a relatively high pressure condition, although -7- 1233644 (2) raises the etching selection ratio for the inorganic material film of the silicon film, there is a problem that the control of the etching shape is poor. This problem occurs not only when an inorganic material film is used as a mask, but also when an inorganic material film is formed on the base layer of a silicon film. SUMMARY OF THE INVENTION The present invention has been made in view of related matters, and an object thereof is to provide a plasma etching method capable of maintaining a high etching selectivity ratio while maintaining a high etching selectivity while etching a silicon film adjacent to an inorganic material film. And device. According to the results of the review by the present inventors, the etching of silicon films such as polycrystalline silicon films will be governed by the plasma density, which will have little help for ion energy, and the etching of inorganic material films such as Si 02 or SiN films. Both plasma density and ion energy are required. Therefore, if the plasma density is high and the ion energy is lower than a certain level, the silicon film of the inorganic material film can increase the etching selection ratio. At this time, the ion energy of the plasma is indirectly matched with the self-bias voltage of the electrode during etching. Therefore, in order to improve the etching selectivity ratio for the silicon film of the inorganic material film, it is necessary to perform the etching under the conditions of high plasma density and low bias voltage. On the one hand, in order to improve the shape controllability of the etching, the process needs to be performed at a low pressure. However, under these conditions, a high etching selectivity can be achieved in a lower pressure process. That is, as long as high plasma density and low self-bias voltage can be achieved, the etching selection ratio can be improved for the silicon film of the inorganic material film under lower voltage conditions, and the high etching selection ratio and good etch shape controllability can be achieved. Stand up. 1233644 (3) According to the results of a further review by the present inventors, if the frequency of the high-frequency power applied to the electrodes is clearly determined, a high plasma density and a small self-bias voltage can be achieved. The present invention is a plasma etching method, comprising: a pair of electrodes are arranged face to face in a processing chamber, and a substrate to be processed adjacent to a silicon film and an inorganic material film is arranged between the two electrodes, and one of them is used. An electrode to support the placement process of the substrate to be processed; and applying high-frequency power to at least one of the electrodes and forming a high-frequency electric field between the pair of electrodes, supplying a processing gas into the processing chamber, and forming the processing gas through the electric field. An etching process in which plasma etching is performed on the silicon film of the substrate to be processed through the plasma; in the etching process, the frequency of the high-frequency power applied to at least one of the electrodes is 50 to 1 5 0MHz. According to the present invention, the high-frequency power applied to the electrode has a frequency of 50 to 150 MHz, which is higher than the conventional one. Even under lower voltage conditions, high plasma density and low self-bias voltage can be achieved. Silicon The film can be etched with a high etching selection ratio and good shape controllability with respect to the inorganic material film. The frequency of the high-frequency power applied to the electrode is 70 to 100 MHz, and more preferably 100 MHz. In the foregoing etching process, the power density of the high-frequency power is preferably 0.15 to 5 W / cm2. In the aforementioned etching process, the plasma density in the processing chamber is preferably 5 × 10 9 to 2 × 10 Gcm · 3. In the aforementioned etching process, the pressure in the processing chamber is preferably equal to or lower than 3.3 Pa -9-1233644 (4). The present invention is a plasma etching method, which is characterized in that: a pair of electrodes are arranged face to face in a processing chamber, and a substrate to be processed adjacent to a silicon film and an inorganic material film is arranged between the two electrodes, and one side is used. Placement process for supporting the substrate to be processed; and applying high-frequency power to at least one of the electrodes and forming a high-frequency electric field between the pair of electrodes, supplying a processing gas into the processing chamber, and forming the gas through the electric field. Plasma of a processing gas, and an etching process in which plasma etching is performed on the silicon film of the substrate to be processed by the plasma; in the foregoing etching process, the processing gas is any of HBr gas and Cl2 gas. The plasma density in the processing chamber is 5xl09 ~ 2xl01GcnT3, and the self-bias voltage of the electrode is below 200V. According to the present invention, under a condition that the plasma density in the processing chamber is 5 × 109 to 2 × 10C) Cnr3 and the self-bias voltage of the electrode is 200 V or less, any one including HBr gas and <: 12 gas is formed. Because of a gas plasma, the silicon film can be etched with high etching selectivity and good shape control for inorganic materials. As described above, the inorganic material film is formed of, for example, at least one of silicon oxide, silicon nitride, silicate nitride, and silicon carbide. The high-frequency power is preferably applied to an electrode supporting the substrate to be processed. At this time, the electrode supporting the substrate to be processed can be superimposed on the aforementioned high-frequency power 'and a second high-frequency power of 3.2 to 13.56 MHz can be applied. By overlapping the second high-frequency power at a lower frequency like this, the plasma density and ion introduction effect can be adjusted, and the etching selection ratio with respect to the inorganic material film can be ensured. In addition to -10- 1233644 (5), The uranium engraving rate of the film increased even more. The overlapping second high-frequency power is preferably 13.56MΗζ. When the frequency of overlapping power is 13.56MHz, its power density is preferably below 0 cm2. On the other hand, when a second high frequency of 3. 2 to 13.56 MΗζ is applied, the self-bias voltage of the electrode supporting the substrate to be processed is preferably 200 V or less. The present invention is a plasma etching apparatus. The plasma etching apparatus includes a processing chamber for accommodating a substrate adjacent to a silicon film and an inorganic material film, and a processing chamber provided in the processing chamber, one of which supports a processing substrate. A counter electrode; and a processing process gas supply system to the processing chamber; a system for exhausting the processing chamber; and a high-frequency power supply for supplying a force for forming a plasma to at least one of the electrodes; The high-frequency power generated by the high-frequency power supply is 50 ~ 150MHz. The frequency of the high-frequency power generated by the aforementioned high-frequency power source is 100 MHz, particularly preferably 100 MHz. It is preferable that the power density of the aforementioned frequency power is 0.15 to 5 W / cm, and the pressure in the processing chamber is preferably 13.3 Pa or less. It is preferable to apply pre-power to the electrodes supporting the substrate to be processed. Preferably, the plasma etching apparatus further includes a second high-frequency power source in which electrodes supporting the processing substrate are superimposed on the high-frequency power and a second high-frequency power of 13.56 MHz is applied. At this time, the frequency of the second local-frequency power is 13.56 MHz. And the best high-frequency • 64 W / electricity voltage is based on the above-mentioned gas exhaust system. The frequency of the high-frequency electricity is 70 ~ The high-frequency is □ 3 · 2 ～, preferably the second-11 -1233644 (6) The power density of high frequency power is 0.64W / cm2 or less. However, since Paschen's law, the discharge start voltage VS is obtained when the product pd of the gas pressure p and the distance d between the electrodes is a certain minimum (Paschen's minimum), and the product of Paschen's minimum The other is that the higher the frequency of high-frequency power, the smaller it becomes. Therefore, when the frequency of the high-frequency power is high, the discharge start voltage VS is small, and the discharge is easy and stable. Therefore, if the gas pressure P is constant, it is necessary to reduce the distance d between the electrodes. Therefore, in the present invention, the distance between the electrodes is preferably less than 50 mm. The distance between the electrodes is less than 50mm, which can shorten the gas retention time in the processing chamber. Thereby, the reaction product can be efficiently discharged, and the effect of reducing the etch stop can be obtained. It is more preferable to further include magnetic field forming means for forming a magnetic field around the plasma region between the pair of electrodes. When the frequency of the applied high-frequency power is high, the etching rate may be higher in the peripheral portion than in the central portion of the feeding position. However, the plasma sealing effect is exerted by forming a magnetic field around the plasma region between a pair of electrodes. Even when the frequency of the applied high-frequency power is high, the etching rate of the substrate to be processed in the processing space is approximately equal to the edge portion (peripheral portion) and the central portion of the substrate to be processed. That is, the etching rate can be made uniform. The magnetic field forming means is preferably such that the magnetic field intensity formed around the plasma region between the pair of electrodes is 0.03 to 0.045T (300 to 450 Gauss). A focus ring is provided around the electrode supporting the substrate to be processed, and when a magnetic field is formed around the aforementioned plasma region, the magnetic field intensity on the focus ring is greater than 0.0001T (lOGauss), and the magnetic field intensity on the substrate to be processed is o.ooi D-12-1233644 (7) The following is preferred. When the magnetic field intensity on the focusing ring is 0.001T or more, a drifting movement of electrons occurs on the focusing ring, and the plasma density in the peripheral portion increases, and the plasma density becomes uniform. On the one hand, the charge loss can be prevented by the magnetic field intensity on the processed substrate being 0.001T or less which does not actually affect the processed substrate. [Embodiment] Best Mode for Carrying Out the Invention An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a sectional view showing a plasma etching apparatus used in the practice of the present invention. This etching apparatus is air-tight and includes a cylindrical processing chamber 1 having a step formed by an upper portion 1 a having a small diameter and a lower portion 1 b having a large diameter. The wall portion of the processing chamber i is, for example, an aluminum product. In the processing chamber 1, a support table 2 for horizontally supporting a wafer W of a substrate to be processed is provided. The support base 2 is made of, for example, aluminum, and is supported by a conductor support base 4 through an insulating plate 3. A focusing ring 5 made of a conductive material or an insulating material is provided on the upper periphery of the support table 2. When the diameter of the wafer W is 200 mm, the focus ring 5 is preferably 240 to 280 mm. The support stand 2, the insulating plate 3, the support stand 4, and the focus ring 5 are raised and lowered by a ball screw mechanism including a ball screw 7. The lift driving part under the support table 4 is covered with a corrugated tube 8 made of stainless steel (SUS). The processing chamber 1 is grounded. A refrigerant flow path (not shown) is provided in the support table 2 to cool the support table 2. A bellows sleeve 9 is provided on the outside of the bellows 8. -13- 1233644 (8) A supply of high-frequency power is connected to the center of the support base 2. A high-frequency power source 10 is connected to the power supply line 12 through the matching box 11. A high-frequency power of a predetermined frequency is supplied from the source 10 to the support table 2. A shower 16 to be described later is provided above one of the support bases 2 opposite to each other in parallel to the ground. The shower head 16 is grounded. Therefore, the support table 2 serves as the lower electric power, and the shower head 16 functions as the upper electrode, that is, 3 and the shower head 16 constitute a pair of flat electrodes. The reason why the distance between these electrodes is set to less than 50 mm is as follows. According to Paschen's law, the discharge start voltage is obtained when the product pd of the gas pressure P and the distance d between the electrodes is a certain value (Paschen's minimum value), and 値, which is the product of Paschen's minimum value, is the force. The higher the frequency, the smaller. Therefore, as in the present embodiment, when the high-frequency is high, in order to make the discharge start voltage VS small, electrically and stable, if the gas pressure p is constant, the distance d must be reduced. Therefore, the distance between the electrodes is preferably less than 50 mm. If the distance is less than 50mm, the gas retention in the processing chamber can be shortened, and the reaction products can be effectively discharged. It is also possible to reduce the etch stop and reduce the distance between the electrodes. Pressure difference between the outer part and the peripheral part) becomes larger. Problems such as a decrease in etching uniformity may occur. In order not to reduce the gas flow difference to less than 0.2 7Pa (2mTor0, the distance between the electrodes should be 35mm or more as the electrostatic line 1 2 high-frequency electrical surface on the surface of the support table 2 to electrostatically adsorb the wafer W. € Support platform 2 is better. VS will get very small local frequency electric power and it is easy to put the time between the electrodes. At this time, the pressure is good at this time. Electric chuck -14-1233644 (9)
6。該靜電夾頭6是在絕緣體6b之間介設著電極6a而構成 。在電極6a連接直流電源1 3。然後由直流電源1 3對電極 6a施加電壓，藉此例如利用庫倫力來吸附半導體晶圓W 〇 在支撐台2的內部形成圖未示的冷媒流路。在其中循 環適當的冷媒5藉此就可將晶圓W控制在所定的溫度。 而且爲了將來自冷媒的冷熱效率良好的傳遞到晶圓W，故 在晶圓W的背面設有供給He氣體的氣體導入機構（圖未 示）。更在聚焦環5的外側設有擋板14。擋板14是通過支撐 台4及波紋管8而與處理室1導通。 在處理室1的頂壁部分，以面對支撐台2的方式設置淋 浴噴頭16。淋浴噴頭16是在其下面設有多數的氣體吐出孔 18，且在其上部具有氣體導入部16a。然後在其內部形成 空間17。在氣體導入部16a連接氣體供給配管15a，在該 氣體供給配管1 5 a的另一端，連接用來供給由蝕刻用的反 應氣體以及稀釋氣體所組成的處理氣體的處理氣體供給系 統統1 5。 反應氣體是用鹵化系的氣體，稀釋氣體可用Αι*氣體 、He氣體等一般領域所用的氣體。 此種處理氣體是從處理氣體供給系統統1 5介著氣體供 給配管15a以及氣體導入部16a而送至淋浴噴頭16的空間 1 7，並從氣體吐出孔1 8被吐出，就能蝕刻形成在晶圓 W 的膜。 在處理室1的下部1 b的側壁形成排氣口 1 9，在該排氣 •15- 1233644 (10) 口 1 9連接具有真空幫浦的排氣系統20。然後使真空幫 動，藉此就能令處理室1內減壓至所定真空度。一方 在處理室1的下部1 b的側壁上側，設有晶圓W的搬入 、和開關該搬入出口的閘閥24。 一方面，在處理室1的上部1 a的周圍，同心狀地 環形磁石21在支撐台2與浴噴頭16之間的處理空間周 成磁場。該環形磁石21可利用旋轉機構25在配置的中 周邊（於周方向）旋轉。 環形磁石2 1乃如第2圖的水平斷面圖所示，由永 石製成的複數個整流子片磁石22是以利用圖未示的支 件支撐的狀態而構成環狀配置。此例是將十六個整流 磁石22以環狀（同心圓狀）配置成多電極狀態。亦即於 磁石21中，鄰接的整流子片磁石22彼此的磁極方向是 相逆向的方式被配置。因而磁力線乃如圖所示，形成 接的整流子片磁石22間，只在處理空間的周邊部形成 0·02 〜0·2Τ(200〜2000Gauss)，最好爲 0.03 〜0· (300.50Gauss)的磁場。一方面，晶圓配置區域實際上 磁場狀態。規定如前述的磁場強度，要是磁場太強的 就會成爲造成洩漏磁場的原因，要是磁場太弱的話， 不到電漿封閉效果。最適當的磁場強度亦存在於裝置 等。 亦即適當的磁場強度範圍是因裝置而異。 而在處理空間的周邊部形成如前述磁場的時候， 聚焦環5上的磁場強度爲0.001T(10GauSS)以上。此時 浦作 面， 出口 配置 圍形 心軸 久磁 撐構 子片 環形 以互 在鄰 例如 045 T 是無 話， 就得 構造 希望 會在 -16- 1233644 (11) 聚焦環上產生電子的漂移運動（EXB漂移），晶圓周邊部的 電漿密度會上昇，電漿密度就能均勻化。一方面，由防止 晶圓W的充電耗損觀點來看，希望晶圓W的存在部分的 磁場強度爲〇.〇〇lT(10GauSS)以下。 在此，晶圓配置區域實際上無磁場是指在晶圓配置區 域形成受到蝕刻處理影響的磁場。亦即實際上也包括存在 著不受晶圓處理影響的磁場的情形。 第2圖所示的狀態，是對晶圓周邊部施加例如磁束密 度0.42mT(4.2GauSS)以下的磁場。藉此發揮封閉電漿的機 會b 。 若藉由此種多電極狀態的環形磁石形成磁場，對應處 理室1之壁部的磁極部分（例如第2圖以P所示的部分）可能 會產生局部性消除的現象。因而利用上述旋轉機構25使環 形磁石2 1沿著處理室的圓周方向旋轉。藉此針對處理室壁 迴避局部性磁極抵接（位置），就能防止處理室壁被局部性 消除。 上述各整流子片磁石22是利用圖未示的整流子片磁石 旋轉機構構成垂直方向的軸於中心自由的旋轉。如此藉由 使整流子片磁石22旋轉，就能實際在形成多電極磁場的狀 態與未形成多電極磁場的狀態間進行切換。因條件而有使 多電極磁場有效作用的情形和不作用的情形。因而就能像 這樣切換形成多電極磁場的狀態和不形成的狀態，藉此配 合條件選擇適當的狀態。 磁場的狀態是配合整流子片磁石的配置進行變化，藉 -17- 1233644 (12) 由使整流子片磁石的配置做各種變化，就能形成各種磁場 強度槪況。因而，欲獲得所需要的磁場強度槪況，最好配 置整流子片磁石。 再者，整流子片磁石的數量於此例中未限定。而其斷 面形狀並不限於此例的長方形，可採用圓形、正方形、梯 形等任意的形狀。構成整流子片磁石2 2的磁石材料也未特 別限定，例如可應用稀土類系磁石、鐵素體系磁石、鋁鎳 鈷磁石等公知的磁石材料。 上述構成的電漿蝕刻裝置是可應用於蝕刻鄰接於 Si 02、SiN等無機系材料膜的多結晶矽的情形。以下針對 使用上述構成的電漿蝕刻裝置來進行此種蝕刻情形的處理 動作做說明。 蝕刻對象的晶圓W乃例如第3圖所示，在基板3 1上形 成多結晶矽膜32，在該矽膜32上具有作爲硬遮罩而形成所 定圖案的無機系材料膜3 3的構成。或是，晶圓W乃如第4 圖所示’在矽基板41之上形成作爲閘氧化膜而由Si 02製 成的無機系材料膜42，在該無機系材料膜42之上形成成爲 閘極的多結晶矽膜43，更在該多結晶矽膜43之上具有形成 成爲遮罩的所定圖案的光阻膜44的構成。 無機系材料膜3 3是以一般作爲硬遮罩而用的材料所構 成。舉例有矽氧化物、矽氮化物、矽酸氮化物、矽碳化物 等適合的材料。亦即無機系材料膜3 3最好是由該些的至少 一種所製成。 對該些構造的晶圓W蝕刻多結晶矽膜3 2或4 3。先打 -18- 1233644 (13) 開閘閥24，利用搬送手臂將晶圓W搬入處理室1內，載置 在支撐台2上。然後，退開搬送手臂並閉合閘閥24，支撐 台2就會上昇到第1圖所示的位置。並利用排氣系統20的真 空幫浦，介著排氣口 19該處理室1內成爲所定的真空度。 然後，對處理室1內自處理氣體供給系統1 5導入所定 的處理氣體例如HBr氣體爲例如0.02〜0.4L/min(20〜 400 S ccm)，該處理室1內維持在所定壓力。在此狀態下， 自高頻電源10對支撐台2供給頻率爲50〜150MHz，最好爲 70〜10 0M Hz的高頻電力。相當於此時的單位面積的功率 亦即功率密度以約〇·15〜約5.0 W/ cm2的範圍爲佳。此時 自直流電源13對靜電夾頭6的電極6a施加所定電壓，晶圓 W就能經由例如庫倫力被吸附在靜電夾頭6上。 像這樣對屬於下部電極的支撐台2施加高頻電力，藉 此就能在屬於上部電極的淋浴噴頭1 6與屬於下部電極的支 撐台2間的處理空間形成高頻電場。藉此供給至處理空間 的處理氣體就會電漿化，藉由其電漿蝕刻晶圓 W上的多 結晶矽膜。 該鈾刻工程之際，利用多電極狀態的環形磁石2 1，在 處理空間的周圍形成如第2圖所示的磁場。此時會發揮電 漿封閉效果，如本實施形態連易產生電漿不均勻的高頻率 狀況，晶圓 W的蝕刻速率也可均勻化。而因條件也有不 形成此種磁場的情形。其狀況是使整流子片磁石22旋轉， 在處理空間的周圍實際上不形成磁場的狀態也可進行處理 -19- 1233644 (14) 形成上述磁場的時候，可利用設在支撐台2上的晶圓 W的周圍的導電性或絕緣性的聚焦環5，更進一步提高電 漿處理的均勻化效果。亦即晶圓周邊部的電漿密度高，晶 圓周邊部的蝕刻速率比晶圓中心部的蝕刻速率大的時候， 使用以矽或SiC等的導電性材料形成的聚焦環，藉此直至 聚焦環區域均作爲下部電極機能的緣故，電漿形成區域會 擴大到聚焦環5上，就會提昇促進晶圓W的周邊部的電漿 處理的蝕刻速率的均勻性。一方面，晶圓周邊部的電漿密 度低，晶圓周邊部的蝕刻速率比晶圓中心部的蝕刻速率小 的時候，使用以石英等絕緣性材料形成的聚焦環，藉此無 法在聚焦環5與電漿中的電子或離子之間獲得電荷，因此 封閉電漿的作用增大，並可提昇蝕刻速率的均勻性。 爲了調整電漿密度及離子引入作用，可以重疊電漿生 成用的前述高頻和引入電漿中的離子的第二高頻。具體乃 如第5圖所示，除電漿生成用的高頻電源1〇外，離子引入 用的第二高頻電源26可連接在匹配箱1 1，並重疊該些。此 時，離子引入用的第二高頻電源26的頻率以3.2〜 13·56ΜΗζ爲佳，在該範圍以13·5 6MHz特別好。藉此因控 制離子能量的參數增加，爲了確保針對需要足夠的無機系 材料膜的蝕刻選擇比外，很容易設有欲更加上昇多結晶矽 膜的蝕刻速率的最適當處理條件。 可是，若根據本發明人等的檢討結果，多結晶矽膜的 蝕刻會受到電漿密度的支配，對離子能量的助益小，且以 無機系材料的蝕刻需要電漿密度和離子能量這兩者。因而 -20- 1233644 (15) 如第3圖及第4圖所示，鄰接於無機系材料膜的多 的蝕刻中，爲了提高相對於無機系材料膜的鈾亥(j 行蝕刻，故需要電漿密度高且離子能量低的情形 機系材料的蝕刻所需要的離子能量降低，支配多 刻的電漿密度高的話，多結晶矽膜會選擇性地鈾 ，因爲電漿的離子能量是與蝕刻之際的電極的自 壓間接性對應，所以爲了以高蝕刻選擇比來蝕刻 膜’結局必須以高電漿密度且低自我偏壓電壓的 蝕刻。一方面，爲了該蝕刻的形狀控制性變良好 低壓來進行蝕刻，但滿足上述條件的話，就能在 製程實現高蝕刻選擇比。亦即實現高電漿密度及 壓電壓的話，連更低壓的條件下，也能提高相對 材料膜的多結晶矽膜的蝕刻選擇比，使高蝕刻選 好的蝕刻形狀控制性並存。而因此施加於電極的 的頻率爲5 0〜1 5 ΟΜΗζ的話，就能明確判斷比習矢 以下參照第6圖說明此情形。第6圖是表示高 頻率爲40MHz、100MHz的自我偏壓電壓的絕對倔 和電漿密度的關係圖。橫軸爲自我偏壓電壓的 Vdc | ，縱軸爲電漿密度。在此，電漿氣體不會 刻氣體，採用評估用的Ar。再者，於各頻率中 變所施加的高頻功率，就會改變電漿密度Ne及 電壓的絕對値| Vdc|之値。就是’連同各頻率 所施加的高頻功率愈大電漿密度N e及自我偏壓 對値I V d c |也變得愈大。而電漿密度是利用微 結晶矽膜 選擇比進 。就是無 結晶矽蝕 刻。在此 我偏壓電 多結晶石夕 條件進行 ，必須以 更低壓的 低自我偏 於無機系 擇比與良 高頻電力 口高。 頻電力的 I I Vdc | 絕對値I 實際的蝕 ，藉由改 自我偏壓 也是隨著 電壓的絕 波干擾器 -21 - 1233644 (16) 測定。 如第6圖所示，高頻電力的頻率爲習知4 Ο Μ Η z的時候 ，爲了提高多結晶矽膜的蝕刻速率使電漿密度上昇的話， | Vdc |也會變大上昇。一方面，高頻電力的頻率比習知 高ΙΟΟΜΗζ的時候，即使電漿密度上昇，|Vdc|還是不 太會上昇，約抑制在1 00V以下。亦即發現能實現高電漿 密度及低自我偏壓電壓。亦即，像習知較低頻率的時候， 於低壓下，實際蝕刻方面，多結晶矽膜的蝕刻速率上昇的 話，同程度下無機系材料膜也會被蝕刻，而無法得到良好 選擇蝕刻性的一方，經觀察得知可藉由1 OOMHz高的頻率 ，以相對於無機系材料膜的高蝕刻選擇比來蝕刻多結晶砂 膜。 而由第6圖即可理解，認爲於低壓下，爲了高電發密 度及低自我偏壓電壓以比習知更高選擇比來飽刻多結晶石夕 膜’形成氬氣體電漿的時候，以電漿密度爲1 X 1 O^cm·3以 上，且電極的自我偏壓電壓爲100V以下，或電發密度爲5 xlOIGCnr3以上，且電極的自我偏壓電壓爲20〇v以下的條 件來形成電漿爲佳。而且爲了滿足此種電漿條件，推測高 頻電力必須爲50MHz以上。 因而，電漿形成用的高頻電力的頻率乃如上述爲 50MHz以上。但是電漿形成用的高頻電力的頻率超過 150MHz的話’電獎的均勻性會受損。因此，電漿形成用 的高頻電力的頻率以150MHz以下爲佳。特別是爲了有效 發揮上述效果’電漿形成用的高頻電力的頻率以7〇〜 -22- 1233644 (17) 1 Ο Ο Μ Η z 爲佳。 蝕刻之際的處理室內壓力以13.3 Pa( 10 OmT)以下爲佳 。由相對於無機系材料膜的多結晶矽膜的蝕刻選擇比和蝕 刻形狀控制性並立的觀點來看，處理室內壓力以 4Pa(30mT)以下爲佳。更重視蝕刻形狀控制性的話，處理 室內壓力以1.33pa(10mT)以下更佳。 其次，爲了把握相對於多結晶矽膜的實際蝕刻速率及 無機系材料膜的蝕刻選擇比，針對進行屬於多結晶矽膜及 無機系材料膜的Si02的全面形成膜蝕刻的實驗結果做說 明。 在此，晶圓是用200mm晶圓，蝕刻氣體是供給HBP 氣體：0.2L/min(壓力爲0.133Pa時只爲0.02L/min)，電極 間間隙爲27mm、處理室內壓力爲4Pa來施行蝕刻處理。 第7A圖是於高頻電力功率爲500 W( 1.59 W/ cm2)、 1000W(3.18W/cm2)、1500W(4.77W/cm2)的各情況下表 示相對於高頻電力爲100MHz時的晶圓位置的多結晶矽膜 的蝕刻速率之値的圖。第7B圖是高頻電力功率爲 5 00W(1.59W/cm2)、1 000W(3.18W/cm2)、1 500W(4.77 W/ cm2)的各情況下表示相對於高頻電力爲40MHz時的晶 圓位置的多結晶砂膜的触刻速率之値的圖。而第8圖是於 40MHz及100MHz的各情況下表示高頻電力功率和多結晶 矽膜的蝕刻速率的關係圖。第9圖是於40MHz及l〇OMHz 的各情況下表不局頻電力功率和S i Ο2膜的鈾刻速率的關 係圖。第10圖是於40MHz及100MHz的各情況下表示高頻 -23- 1233644 (18) 電力功率和多結晶矽膜的蝕刻速率的關係，以及相當於高 頻電力功率和蝕刻選擇的多結晶矽膜的蝕刻速率/ Si02膜 的蝕刻速率比（第10圖中記載爲蝕刻選擇比）的關係圖。第 1 1圖是於40MHz及100MHz的各情況下表示相當於多結晶 矽膜的蝕刻速率和蝕刻選擇比的多結晶矽膜的蝕刻速率/ Si02膜的蝕刻速率比（第1 1圖也記載爲蝕刻選擇比）的關係 圖。 由該些圖看來，多結晶矽膜的刻速率，一旦高頻電力 功率增加就會變大的傾向，但在4 0 Μ Η z的蝕刻速率和在 1 0 0 Μ Η ζ的蝕刻速率就沒有太大的差距。而以相同氣體壓 力以及相同功率，多結晶矽膜在40MHz的蝕刻速率和在 10 0MHz的蝕刻速率是相同程度，但Si 02膜的蝕刻速率則 是4 0MHz的情形比100MHz的情形高。因而，確認 100MHz的情形比40MHz的情形是相當於針對Si02膜的多 結晶矽膜的蝕刻選擇比，多結晶矽膜的蝕刻速率/ Si02膜 的蝕刻速率比很高。亦即由評估用取樣的實驗結果來看， 確認於4Pa中，使用100MHz的高頻電力，以高蝕刻選擇 比蝕刻多結晶矽膜的可能性比4〇MHz還高。多結晶矽膜 的蝕刻速率和蝕刻選擇比是選替的關係，高頻電力功率太 大的話，多結晶矽膜的蝕刻速率增大，但蝕刻選擇比降低 。因而，100MHz的高頻電力的功率密度以5W/cm2(約 1 5 00W)以下爲佳。 一方面，以100MHz在功率密度低的方向，多結晶矽 膜的蝕刻速率會降低，且相對於Si02膜的蝕刻選擇比會 -24- 1233644 (19) 提昇。蝕刻對象膜的基層爲Si02等閘氧化膜的時候，其 厚度爲通常的數nm程度的緣故，Si 02蝕刻速率必須下降 到0 . 1 n m / m i η等級。例如1 . 3 3 P a (1 0 m T 〇 r r)的壓力條件時 ，在1.5W/cm2(約5 00W)的功率密度，多結晶矽膜的蝕刻 速率爲lOOnm/ min，蝕刻選擇比爲70，Si02的蝕刻速率 爲1.43nm/ min。因而，Si02的蝕刻速率下降到O.lnm/ min等級的緣故，假設功率密度必須下降到0·1 5〜0.3W/ cm2(約50〜100 W)程度。考慮以上各點的話，最低的高頻 電力功率以〇.3W/cm2以上爲佳，更好是0.15W/cm2(約 5 0W)以上。只以蝕刻選擇性觀點來看，高頻電力功率以 1.5W/cm2(約5 00W)以下爲佳。 其次，HBr氣體的流量會在0.02〜0.2L/min之間變 化，處理室內壓力會在〇.1 33〜13.3 Pa之間變化，而高頻 電力功率固定爲5 00W，其他以上述條件進行蝕刻。 第12A圖是表示蝕刻之際的處理室內壓力和高頻電力 爲100MHz時以及40MHz時的多結晶矽膜的蝕刻速率的關 係圖，第1 2B圖是表示蝕刻之際處理室內壓力和高頻電力 爲100MHz時以及40MHz時的3丨02膜的蝕刻速率的關係圖 。第13圖是於40MHz及100MHz的各情況下表示相當於處 理室內壓力和蝕刻選擇比的多結晶矽膜的蝕刻速率/ Si02 膜的蝕刻速率之比（於第1 3圖中記載爲蝕刻選擇比）的關係 圖。第14圖是於40MHz及100MHz的各情況下表示相當於 處理室內壓力和多結晶矽膜的蝕刻速率的關係以及相當於 高頻電力功率和蝕刻選擇比的多結晶矽膜的蝕刻速率/ -25- 1233644 (20)6. This electrostatic chuck 6 is configured by interposing an electrode 6a between insulators 6b. A DC power source 13 is connected to the electrode 6a. Then, a voltage is applied to the electrode 6a by the DC power source 13 to thereby, for example, use a Coulomb force to adsorb the semiconductor wafer W 0 to form a refrigerant flow path (not shown) inside the support table 2. By circulating an appropriate refrigerant 5 therein, the wafer W can be controlled at a predetermined temperature. In addition, in order to efficiently transfer cold and heat from the refrigerant to the wafer W, a gas introduction mechanism (not shown) for supplying He gas is provided on the back surface of the wafer W. A baffle 14 is further provided on the outside of the focus ring 5. The baffle plate 14 communicates with the processing chamber 1 via the support table 4 and the bellows 8. On the top wall portion of the processing chamber 1, a shower head 16 is provided so as to face the support table 2. The shower head 16 is provided with a plurality of gas discharge holes 18 on its lower surface, and has a gas introduction portion 16a on its upper portion. A space 17 is then formed inside it. A gas supply pipe 15a is connected to the gas introduction portion 16a, and a process gas supply system 15 for supplying a process gas composed of a reaction gas for etching and a diluent gas is connected to the other end of the gas supply pipe 15a. The reaction gas is a halogenated gas, and a diluent gas may be a gas used in general fields such as Ai * gas and He gas. This processing gas is sent from the processing gas supply system 15 to the space 17 of the shower head 16 through the gas supply pipe 15a and the gas introduction part 16a, and is discharged from the gas discharge hole 18, and can be formed by etching. Film for wafer W. An exhaust port 19 is formed in a side wall of the lower portion 1 b of the processing chamber 1, and an exhaust system 20 having a vacuum pump is connected to the exhaust port 15-1233644 (10). Then, the vacuum chamber is operated to reduce the pressure in the processing chamber 1 to a predetermined vacuum degree. On the upper side of the side wall of the lower portion 1b of the processing chamber 1, a wafer W is carried in and a gate valve 24 for opening and closing the carrying in port is provided. On the one hand, around the upper portion 1a of the processing chamber 1, a concentric ring magnet 21 forms a magnetic field around the processing space between the support table 2 and the shower head 16. The ring magnet 21 can be rotated by the rotation mechanism 25 at the center periphery (in the circumferential direction) of the arrangement. As shown in the horizontal cross-sectional view of Fig. 2, the ring magnet 21 is formed by a plurality of commutator plate magnets 22 made of permanent stone in a state of being supported by a support (not shown). In this example, sixteen rectifying magnets 22 are arranged in a ring (concentric circle) in a multi-electrode state. That is, in the magnet 21, the magnetic pole directions of the adjacent commutator piece magnets 22 are arranged so as to be opposite to each other. Therefore, the magnetic field lines are formed between the commutator piece magnets 22 as shown in the figure, and only 0. 02 to 0. 2T (200 to 2000 Gauss) is formed on the periphery of the processing space, and preferably 0.03 to 0. Magnetic field. On the one hand, the wafer configuration area is actually a magnetic field. It is stipulated that the intensity of the magnetic field as described above, if the magnetic field is too strong, will cause the leakage magnetic field, and if the magnetic field is too weak, the plasma sealing effect will not be achieved. The most appropriate magnetic field strength also exists in devices and the like. That is, the proper range of magnetic field strength varies from device to device. When a magnetic field as described above is formed in the peripheral portion of the processing space, the magnetic field intensity on the focus ring 5 is 0.001 T (10 GauSS) or more. At this time, the exit surface is configured with a ring-shaped mandrel long magnetic support sub-rings to be adjacent to each other. For example, 045 T is speechless. You must construct the structure to hope that electron drift will occur on the -16-1233644 (11) focus ring. With the movement (EXB drift), the plasma density in the peripheral part of the wafer will increase, and the plasma density will be uniform. On the other hand, from the viewpoint of preventing the charge loss of the wafer W, it is desirable that the magnetic field strength of the portion where the wafer W exists is not more than 0.0001T (10GauSS). Here, the fact that there is no magnetic field in the wafer arrangement area means that a magnetic field affected by the etching process is formed in the wafer arrangement area. That is, it actually includes the case where a magnetic field is not affected by the wafer processing. In the state shown in Fig. 2, a magnetic field having a magnetic flux density of 0.42 mT (4.2 GauSS) or less is applied to the peripheral portion of the wafer. Take advantage of this opportunity to close the plasma b. If a magnetic field is formed by such a multi-electrode ring magnet, the magnetic pole portion corresponding to the wall portion of the processing chamber 1 (for example, the portion indicated by P in Fig. 2) may be partially eliminated. Therefore, the ring magnet 21 is rotated by the rotation mechanism 25 in the circumferential direction of the processing chamber. By avoiding the local magnetic pole abutment (position) to the processing chamber wall, the processing chamber wall can be prevented from being locally eliminated. Each of the commutator piece magnets 22 described above uses a not-shown commutator piece magnet rotation mechanism to freely rotate around the center of the axis in the vertical direction. By rotating the commutator sheet magnet 22 in this manner, it is possible to actually switch between the state where the multi-electrode magnetic field is formed and the state where the multi-electrode magnetic field is not formed. Depending on the conditions, there may be cases where the multi-electrode magnetic field is effective and ineffective. Therefore, the state in which the multi-electrode magnetic field is formed and the state in which it is not formed can be switched in this manner, and the appropriate state can be selected by the matching conditions. The state of the magnetic field is changed in accordance with the configuration of the commutator plate magnets. -17-1233644 (12) Various changes in the configuration of the commutator plate magnets can form various magnetic field strength conditions. Therefore, to obtain the required magnetic field strength, it is best to configure a commutator plate magnet. In addition, the number of commutator plate magnets is not limited in this example. The cross-sectional shape is not limited to the rectangle in this example, and any shape such as a circle, a square, or a ladder can be used. The magnet material constituting the commutator plate magnet 22 is also not particularly limited, and for example, well-known magnet materials such as rare earth magnets, ferrite magnets, aluminocobalt magnets, and the like can be applied. The plasma etching apparatus configured as described above is applicable to the case of etching polycrystalline silicon adjacent to an inorganic material film such as Si 02 or SiN. In the following, a processing operation in the case of performing such an etching using the plasma etching apparatus configured as described above will be described. The wafer W to be etched is, for example, as shown in FIG. 3, and a polycrystalline silicon film 32 is formed on a substrate 31. The silicon film 32 has an inorganic material film 33 as a hard mask to form a predetermined pattern. . Alternatively, as shown in FIG. 4, the wafer W is formed on the silicon substrate 41 with an inorganic material film 42 made of SiO 2 as a gate oxide film, and is formed on the inorganic material film 42 as a gate. The polycrystalline silicon film 43 has a structure in which a photoresist film 44 having a predetermined pattern as a mask is formed on the polycrystalline silicon film 43. The inorganic material film 33 is composed of a material generally used as a hard mask. Examples of suitable materials include silicon oxide, silicon nitride, silicate nitride, and silicon carbide. That is, the inorganic material film 33 is preferably made of at least one of these. A polycrystalline silicon film 32 or 43 is etched on the wafers W of these structures. First hit -18- 1233644 (13) Open the gate valve 24, use the transfer arm to carry the wafer W into the processing chamber 1, and place it on the support table 2. Then, when the transfer arm is retracted and the gate valve 24 is closed, the support table 2 is raised to the position shown in Fig. 1. A vacuum pump of the exhaust system 20 is used, and a predetermined degree of vacuum is obtained in the processing chamber 1 through the exhaust port 19. Then, a predetermined processing gas such as HBr gas is introduced into the processing chamber 1 from the processing gas supply system 15 at, for example, 0.02 to 0.4 L / min (20 to 400 S ccm), and the processing chamber 1 is maintained at a predetermined pressure. In this state, the high-frequency power is supplied from the high-frequency power source 10 to the support table 2 at a frequency of 50 to 150 MHz, preferably 70 to 100 MHz. The power per unit area at this time, that is, the power density is preferably in the range of about 0.15 to about 5.0 W / cm2. At this time, a predetermined voltage is applied from the DC power source 13 to the electrode 6a of the electrostatic chuck 6, and the wafer W can be attracted to the electrostatic chuck 6 by, for example, Coulomb force. By applying high-frequency power to the supporting table 2 belonging to the lower electrode in this manner, a high-frequency electric field can be formed in the processing space between the shower head 16 belonging to the upper electrode and the supporting table 2 belonging to the lower electrode. The processing gas supplied to the processing space is thus plasmatized, and the polycrystalline silicon film on the wafer W is etched by the plasma. During the uranium engraving process, a multi-electrode ring magnet 21 is used to form a magnetic field as shown in Fig. 2 around the processing space. At this time, the plasma sealing effect is exerted. As in this embodiment, even if a high frequency condition of plasma unevenness is easily generated, the etching rate of the wafer W can be made uniform. Depending on the conditions, such a magnetic field may not be formed. The situation is that the commutator sheet magnet 22 is rotated, and processing can be performed in a state where a magnetic field is not actually formed around the processing space. 19-1233644 (14) When the above magnetic field is formed, a crystal provided on the support table 2 can be used. The conductive or insulating focusing ring 5 around the circle W further improves the uniformity effect of the plasma treatment. That is, when the plasma density of the peripheral portion of the wafer is high, and the etching rate of the peripheral portion of the wafer is higher than the etching rate of the central portion of the wafer, a focusing ring made of a conductive material such as silicon or SiC is used to focus until For the reason that the ring region functions as the lower electrode, the plasma formation region is enlarged to the focus ring 5, and the uniformity of the etching rate that promotes the plasma treatment of the peripheral portion of the wafer W is improved. On the other hand, when the plasma density of the peripheral portion of the wafer is low and the etching rate of the peripheral portion of the wafer is lower than the etching rate of the central portion of the wafer, a focusing ring made of an insulating material such as quartz is used. The charge is obtained between 5 and the electrons or ions in the plasma, so the effect of sealing the plasma is increased, and the uniformity of the etching rate can be improved. In order to adjust the plasma density and ion introduction effect, the aforementioned high frequency for plasma generation and the second high frequency of ions introduced into the plasma may be overlapped. Specifically, as shown in FIG. 5, in addition to the high-frequency power source 10 for plasma generation, the second high-frequency power source 26 for ion introduction can be connected to the matching box 11 and overlapped therewith. At this time, the frequency of the second high-frequency power source 26 for ion introduction is preferably 3.2 to 13.56 MHz, and particularly preferably 13.56 MHz in this range. As a result of the increase in the parameter controlling ion energy, in order to ensure an adequate etching selection ratio for an inorganic material film, it is easy to set the optimum processing conditions for further increasing the etching rate of the polycrystalline silicon film. However, according to the review results of the inventors, the etching of the polycrystalline silicon film will be dominated by the plasma density, which will have little help for ion energy, and the etching of inorganic materials requires both plasma density and ion energy. By. Therefore, -20-1233644 (15) As shown in FIG. 3 and FIG. 4, in many etchings adjacent to the inorganic material film, in order to increase the uranium oxide (j line etching) with respect to the inorganic material film, electricity is required. In the case of high plasma density and low ion energy, the ion energy required for the etching of machine materials is reduced. If the plasma density that governs multiple times is high, the polycrystalline silicon film will selectively uranium because the ion energy of the plasma is related to the etching. In this case, the self-pressure of the electrode is indirect. Therefore, in order to etch the film with a high etching selection ratio, the etching must be performed with a high plasma density and a low self-bias voltage. On the one hand, the shape controllability of the etching is improved. Etching is performed at a low voltage, but if the above conditions are met, a high etching selection ratio can be achieved in the process. That is, if high plasma density and voltage are achieved, even at lower voltages, the polycrystalline silicon of the material film can be improved. The etch selection ratio of the film coexists with the control of the etch shape selected for high etch. Therefore, if the frequency applied to the electrode is 50 to 1 5 ΜΗζ, it is possible to clearly determine the following parameters. This situation is illustrated in Figure 6. Figure 6 is a graph showing the relationship between the absolute chirp of self-bias voltage and plasma density at a high frequency of 40 MHz and 100 MHz. The horizontal axis is Vdc | and the vertical axis is plasma. Density. Plasma gas will not be engraved. Ar is used for evaluation. In addition, changing the applied high-frequency power at each frequency will change the absolute density of the plasma density Ne and the voltage 値 | Vdc |値. That is, the higher the high-frequency power applied to each frequency, the greater the plasma density N e and the self-bias voltage 値 IV dc | become. The plasma density is selected using a microcrystalline silicon film. No crystalline silicon etching. Here I bias the polycrystalline silicon under the condition of the electric voltage, it must be lower than the low self bias of the inorganic system and the high-frequency power port is higher. Frequency power II Vdc | Absolute 値 I actual Corrosion, by changing the self-bias voltage, is also measured with the voltage of the Absolute Jammer-21-1233644 (16). As shown in Figure 6, when the frequency of high-frequency power is the conventional 4 0 Μ Η z, Increasing the etch rate of polycrystalline silicon film increases plasma density Then, | Vdc | will also increase and increase. On the one hand, when the frequency of high-frequency power is 100 MHz higher than the conventional one, even if the plasma density increases, | Vdc | will not rise much, and it will be suppressed below about 100V. That is to say, it is found that high plasma density and low self-bias voltage can be achieved. That is, when the low etching frequency is known, the etching rate of polycrystalline silicon film is increased at low voltage, and the inorganic system is the same degree. The material film is also etched, and it is not possible to obtain a good selective etching property. It has been observed that the polycrystalline sand film can be etched at a high frequency of 100 MHz with a high etching selection ratio relative to the inorganic material film. It can be understood from FIG. 6 that it is considered that at a low voltage, for the purpose of high electric density and low self-bias voltage, a polycrystalline stone film is formed with a higher selection ratio than conventional when forming an argon gas plasma. Based on the conditions that the plasma density is 1 X 1 O ^ cm · 3 or more, and the self-bias voltage of the electrode is 100 V or less, or the electric emission density is 5 x 10 OIGCnr3 or more, and the self-bias voltage of the electrode is 200 V or less. Plasma formation is preferred. In addition, in order to satisfy such a plasma condition, it is estimated that the high-frequency power must be 50 MHz or more. Therefore, the frequency of the high-frequency power for plasma formation is 50 MHz or more as described above. However, if the frequency of the high-frequency power for plasma formation exceeds 150 MHz, the uniformity of the 'electric prize' will be impaired. Therefore, the frequency of the high-frequency power for plasma formation is preferably 150 MHz or less. In particular, in order to effectively exert the above-mentioned effect, the frequency of the high-frequency power for plasma formation is preferably 70--22-1233644 (17) 1 〇 Μ Η z. The pressure in the processing chamber during etching is preferably 13.3 Pa (10 OmT) or less. From the standpoint that the etching selectivity and the shape controllability of the polycrystalline silicon film with respect to the inorganic-based material film are compatible, the pressure in the processing chamber is preferably 4 Pa (30 mT) or less. If the control of the etching shape is more important, the pressure in the processing chamber is preferably 1.33 Pa (10 mT) or less. Next, in order to grasp the actual etching rate with respect to the polycrystalline silicon film and the etching selection ratio of the inorganic material film, the experimental results of performing a full-scale film etching of Si02, which belongs to the polycrystalline silicon film and the inorganic material film, will be explained. Here, the wafer is a 200mm wafer, the etching gas is supplied with HBP gas: 0.2L / min (only 0.02L / min when the pressure is 0.133Pa), the gap between the electrodes is 27mm, and the pressure in the processing chamber is 4Pa for etching. deal with. Figure 7A shows the wafer when the high-frequency power is 500 W (1.59 W / cm2), 1000 W (3.18 W / cm2), and 1500 W (4.77 W / cm2). A plot of the etch rate of a polycrystalline silicon film at a location. Figure 7B shows the crystals when the high-frequency power is 500W (1.59W / cm2), 1,000W (3.18W / cm2), and 1,500W (4.77W / cm2). Plot of the engraving rate of polycrystalline sand film in a circular position. Fig. 8 is a graph showing the relationship between the high-frequency power and the etching rate of the polycrystalline silicon film in each case at 40 MHz and 100 MHz. Fig. 9 is a relationship diagram between the power of the local frequency power and the uranium etch rate of the Si02 film at each of the cases of 40MHz and 100MHz. Figure 10 shows the relationship between high-frequency -23-1233644 (18) electric power and etching rate of polycrystalline silicon film, and the polycrystalline silicon film corresponding to high-frequency electric power and etching selection in each case at 40MHz and 100MHz. The relationship between the etching rate / etching rate ratio of Si02 film (the etching selection ratio is shown in FIG. 10). Fig. 11 shows the etching rate of the polycrystalline silicon film / etching rate ratio of the Si02 film corresponding to the etching rate and etching selection ratio of the polycrystalline silicon film in each case at 40 MHz and 100 MHz. (Fig. 11 is also described as Etch selection ratio). From these figures, the etch rate of the polycrystalline silicon film tends to increase once high-frequency power is increased, but the etch rate at 40 Μ Η z and the etch rate at 100 Μ ζ ζ Not much difference. With the same gas pressure and the same power, the etching rate of polycrystalline silicon film at 40MHz is the same as that of 100MHz, but the etching rate of Si 02 film is higher at 40MHz than at 100MHz. Therefore, it is confirmed that the case of 100 MHz is equivalent to the etching selection ratio of the polycrystalline silicon film for the Si02 film compared to the case of 40 MHz, and the etching rate ratio of the polycrystalline silicon film / etching rate of the Si02 film is high. That is, from the experimental results of the evaluation sampling, it was confirmed that the possibility of etching a polycrystalline silicon film with a high etching selection ratio using a high-frequency power of 100 MHz at 4 Pa is higher than 40 MHz. The etching rate and etching selection ratio of polycrystalline silicon film is an alternative relationship. If the high-frequency power is too large, the etching rate of polycrystalline silicon film increases, but the etching selection ratio decreases. Therefore, the power density of 100 MHz high-frequency power is preferably 5 W / cm2 or less (about 1500 W). On the one hand, at 100MHz in the direction of low power density, the etching rate of the polycrystalline silicon film will decrease, and the etching selection ratio relative to the Si02 film will increase -24-1233644 (19). When the base layer of the film to be etched is a gate oxide film such as Si02, the thickness of the film is usually several nm, so the etching rate of Si 02 must be reduced to a level of 0.1 n m / m i η. For example, under a pressure condition of 1.3 3 P a (10 m T 〇rr), at a power density of 1.5 W / cm2 (about 500 W), the etching rate of the polycrystalline silicon film is 100 nm / min, and the etching selection ratio is 70, the etching rate of Si02 is 1.43nm / min. Therefore, because the etching rate of SiO2 has dropped to the level of 0.1 nm / min, it is assumed that the power density must be reduced to a level of 0.1 to 5 to 0.3 W / cm2 (about 50 to 100 W). Taking the above points into consideration, the lowest high-frequency power is preferably 0.3 W / cm2 or more, and more preferably 0.15 W / cm2 (about 50 W) or more. From the viewpoint of etching selectivity, the high-frequency power is preferably 1.5 W / cm2 or less (about 500 W). Secondly, the flow rate of HBr gas will change between 0.02 ~ 0.2L / min, the pressure in the processing chamber will change between 0.13 ~ 13.3 Pa, and the high-frequency power will be fixed at 500W. Others will be etched under the above conditions. . FIG. 12A is a graph showing the relationship between the pressure in the processing chamber during etching and the etching rate of the polycrystalline silicon film at 100 MHz and 40 MHz, and FIG. 12B is a graph showing the pressure in the processing chamber during etching and high-frequency power. It is a relationship diagram of the etching rate of a 3 | 02 film at 100MHz and 40MHz. Figure 13 shows the ratio of the etching rate of the polycrystalline silicon film to the etching rate of the Si02 film corresponding to the pressure in the processing chamber and the etching selection ratio in each case at 40MHz and 100MHz (the etching selection ratio is shown in Figure 13). ) Diagram. Figure 14 shows the relationship between the pressure in the processing chamber and the etching rate of the polycrystalline silicon film and the etching rate of the polycrystalline silicon film corresponding to high-frequency power and etching selectivity in each case at 40MHz and 100MHz / -25 -1233644 (20)
Si〇2膜的蝕刻速率之比（於第14圖中也記載爲蝕刻選擇比） 的關係圖。第15圖是於40MHz及100MHz的各情況下表示 相當於多結晶矽膜的蝕刻速率和鈾刻選擇比的多結晶矽膜 的鈾刻速率/ S i 0 2膜的触刻速率之比（於第1 5圖中也記載 爲蝕刻選擇比）的關係圖。 由該些圖看來，爲相同高頻電力功率及處理室內壓力 的話，確認1 00MHz時多結晶矽膜的蝕刻速率比40MHz時 略高，蝕刻選擇比也很高。而爲相同高頻電力功率的話， 確認1 0 0 Μ Η z時比4 0 Μ Η z時能以更低壓力得到高蝕刻選擇 比。更如第1 5圖所示，以相同高頻電力功率及蝕刻速率， 亦確認蝕刻選擇比在100MHz的時候比40MHz的時候還高 〇 由該些情形，確認1 00MHz時，在有利於蝕刻形狀控 制性的低壓條件下可得到很高的蝕刻選擇比，可實現高蝕 刻選擇性和良好蝕刻形狀控制性的這兩者。 壓力的影響中，40MHz或100MHz，確認在高壓方面 ，多結晶矽膜的蝕刻速率及蝕刻選擇比良好。然而由多結 晶矽膜的蝕刻形狀控制性的觀點來看，確認低壓方面具體 是以13.3Pa以下爲佳。 其次，針對使用實際的蝕刻氣體（HBr)，把握（測定） 施加100MHz高頻電力時的自我偏壓電壓的絕對値| Vdc I和電漿密度的結果做說明。 第16圖是針對高頻電力的頻率爲100MHz，以HBr氣 體形成電漿的情形下，比較自我偏壓電壓的絕對値和電漿 -26· 1233644 (21) 密度的關係圖。橫軸爲自我偏壓電壓的絕對値I Vdc I ， 縱軸爲電漿密度。電漿密度是利用微波千擾器測定。 此時的處理室內壓力爲2.7Pa(20mTorr)。而100MHz 的高頻電力的功率會在500〜2000W之間變化，藉此電漿 密度及自我偏壓電壓的絕對値| Vdc |會改化。更在 100MHz的高頻電力的功率爲500W的時候，13MHz的第 二高頻電力會在〇W、200W、600W重疊。 由第16圖即可明白，連各頻率在內，也是施加的高頻 功率愈大，電漿密度Ne及自我偏壓電壓的絕對値| Vdc I也愈大。 如第16圖所示，實際的蝕刻氣體的電漿，與Ar氣體 的電漿相比（參照第6圖），會有電漿密度略低的傾向。而 更低頻率的第二高頻電力（13MHz)會重疊，其功率增大的 話，會有自我偏壓電壓變高的傾向。 而由第16圖即可明白，第二高頻電力未重疊的時候， 即使電漿密度上昇，I Vdc |還是不太會上昇，會抑制在 約1 〇〇V以下。亦即發現可實現高電漿密度及低自我偏壓 電壓。 第17圖是針對第二高頻電力未重疊的時候，高頻電力 的高頻電力功率和多結晶矽膜的蝕刻速率的關係，以及相 當於高頻電力的高頻電力功率和蝕刻選擇比的多結晶矽膜 的蝕刻速率/ Si02膜的蝕刻速率之比的關係而示的圖。 高頻電力功率變大的話，因多結晶矽膜的蝕刻速率變 大，但選擇比變小，故以約1 5 0 0 W (約4 · 7 7 W / c m2)以下爲 -27- 1233644 (22) 佳。一方面，因功率變小的話，蝕刻速率變小，但選擇比 變大，故以約5 00W(約1.5W/cm2)以上爲佳。 由第16圖及第17圖可以確認利用100MHz的高頻率， 可得到需要的多結晶矽的蝕刻速率，且多結晶矽膜相對於 無機系材料膜可用高蝕刻選擇比進行蝕刻。 而由第16圖及第17圖即可理解，於低壓下，高電漿密 度及低自我偏壓電壓可以比習知利用更高選擇比且需要的 蝕刻速率來蝕刻多結晶矽膜，故考慮電漿密度爲5 X 1 09〜 2xl01()cnr3，且電極的自我偏壓電壓以200V以下爲佳。 再者，處理氣體除含有HBr氣體的氣體外，也可使 用含有Cl2氣體的氣體，但後者的情形下亦確認適當的電 漿密度的範圍具有與上述同樣的範圍。 一方面，第18圖是針對高頻電力的高頻電力功率固定 爲500W，而第二高頻電力的高頻電力功率爲重疊的情形 下，第二高頻電力的高頻電力功率和多結晶矽膜 蝕刻速 率的關係’以及相當於第二高頻電力的高頻電力功率和蝕 刻選擇比的多結晶矽膜的蝕刻速率/ Si02膜的蝕刻速率之 比的關係而示的圖。 由第16圖及第18圖即可明白，13MHz的第二高頻電 力重疊，其功率增大的話，蝕刻速率上昇的一方，電極的 自我偏壓電壓也會增大。自我偏壓電壓變大的話，、蝕刻 選擇比會有降低的傾向，直至自我偏壓電壓200V就是第 二高頻電力功率約200 W(約0.64 W/ cm2)能將蝕刻選擇比 維持在容許範圍。 -28- 1233644 (23) 因而重疊的第二高頻電力的功率（偏壓功率）增加，藉 此蝕刻選擇比即可維持1 0以上還能提高蝕刻速率。 以上的試驗中，電極間間隙爲2 7mm，但如上所述， 電極間距離太小的話，被處理基板的晶圓W的表面壓力 分佈（中心部與周邊部的壓力差）變大，而產生蝕刻均勻性 降低等問題。因而，實際的電極間距離以35〜50mm更好 。此情形參照第1 9圖做說明。 第1 9圖是將電漿氣體使用Ar氣體時的Ar氣體流量和 晶圓中心部和晶圓周邊部的壓力差△ P的關係與電極間間 隙25mm和4 0mm的情形做比較而示的圖。如第19圖所示 ，間隙爲40mm的這方，壓成差ΔΡ比2 5mm小。而間隙 2 5mm的時候，會隨著Ar氣體流量一起上昇，而壓力差 △P會有急遽變大的傾向，氣體流量爲0.3 L/ min程度以 上，會超過不會發生蝕刻均勻性降低等問題的容許最大壓 力差△ P的0.27Pa(2mTorr)。對此，間隙40mm的時候，不 必根據氣體流量，壓力差就會不於0.27Pa(2mT〇r〇。因而 ，假設電極間間隙約爲35mm以上的話，不必根據氣體流 量，就能確保不會發生蝕刻均勻性降低等問題的容許最大 壓力差。 再者，本發明並不限於上述實施形態，可做各種變更 。例如上述實施形態中，矽膜是表示使用多結晶矽膜，但 並不限於此，也可使用單結晶矽膜或非晶質矽膜等其他矽 膜。 而上述實施形態中，磁場形成手段是使用由永久磁石 -29- 1233644 (24) 製成的複數個整流子片磁石以環狀配置在處理室周圍的多 電極狀態的環形磁石，但只要是能在處理空間的周圍形成 磁場而封閉電漿就可以，並不限於本形態。而此種電漿封 閉用的周邊磁場不一定需要。就是可在不存在磁場的狀態 下進行蝕刻。而對處理空間施加水平磁場，並在正交電磁 場中進行電漿蝕刻的電漿蝕刻處理也很適用本發明。 更在上述實施形態中，對下部電極施加電漿形成用的 高頻電力，但並不限於此，也可施加在上部電極。更且被 處理基板的層構造並不限於上述實施形態的第3圖或第4圖 所示者。甚至被處理基板是表示針對使用半導體晶圓的情 形，但並不限於此，也適用於其他被處理基板的多結晶矽 膜的蝕刻。 【圖式簡單說明】 第1圖是表示本發明之一實施形態的電漿蝕刻裝置的 槪略斷面圖。 第2圖是模式表示配置在第1圖的電漿蝕刻裝置的處理 室周圍的環形磁石的水平斷面圖。 第3圖是表示應用本發明的電漿蝕刻的半導體晶圓構 造之一實例的斷面圖。 第4圖是表示應用本發明的電漿蝕刻的半導體晶圓構 造的其他實例的斷面圖。 第5圖是部分表示具備有電漿生成用的高頻電源與離 子引入用的高頻電源的電漿處理裝置的槪略斷面圖。 -30- 1233644 (25) 第6圖是表示於氬氣體的電漿中，高頻電力的頻率爲 4 0MHz與100MHz時的自我偏壓電壓的絕對値| Vdc |與 電漿密度Ne的關係圖。 第7A圖是於高頻電力功率爲5 00W、1 000W、1 5 0 0W 的各個時候表示針對高頻電力爲100MHz時的晶圓位置的 多結晶矽膜的蝕刻速率之値的圖。 第7B圖是於高頻電力功率爲500W、1 000W、1 5 00W 的各個時候表示針對高頻電力爲40MHz時的晶圓位置的 多結晶矽膜的蝕刻速率之値的圖。 第8圖是於高頻電力爲40MHz與100MHz的時候表示 高頻電力功率與多結晶矽膜的鈾刻速率的關係圖。 第9圖是於高頻電力爲40MHz與100MHz的時候表示 高頻電力功率與Si02膜的蝕刻速率的關係圖。 第1〇圖是於高頻電力爲40MHz與100MHz的時候表示 高頻電力功率與多結晶矽膜的蝕刻速率的關係以及相對於 高頻電力功率與蝕刻選擇比的多結晶矽膜的蝕刻速率/ Si〇2膜的蝕刻速率比的關係圖。 第11圖是於高頻電力爲40MHz與100MHz的時候表示 相當於結晶矽膜的蝕刻速率與蝕刻選擇比的多結晶矽膜的 蝕刻速率/ Si02膜的蝕刻速率比的關係圖。 第12A圖是表示蝕刻之際的處理室內壓力與高頻電力 爲100MHz時以及爲40MHz時的多結晶矽膜的蝕刻速率的 關係圖。 第1 2B圖是表示蝕刻之際的處理室內壓力與高頻電力 -31 - 1233644 (26) 爲100MHz的時候以及爲40MHz的時候的Si02膜的蝕刻速 率的關係圖。 第13圖是於高頻電力爲40MHz與100MHz的時候表示 相當於處理室內壓力與蝕刻選擇比的多結晶矽膜的蝕刻速 率/ Si02膜的蝕刻速率比的關係圖。 第14圖是於高頻電力爲40MHz與100MHz的時候表示 處理室內壓力與多結晶矽膜的蝕刻速率的關係以及相當於 高頻電力功率與蝕刻選擇比的多結晶矽膜的蝕刻速率/ Si02膜的蝕刻速率比的關係圖。 第15圖是於高頻電力爲40MHz與100MHz的時候表示 相當於多結晶矽膜的蝕刻速率與蝕刻選擇比的多結晶矽膜 的蝕刻速率/ Si02膜的蝕刻速率比的關係圖。 第16圖是表示於HBr氣體的電漿中，高頻電力的頻 率爲100MHz，第二高頻電力爲13MHz，而各個高頻電力 功率改變的時候（高頻電力：5〇〇W、1 000W、1 5 00W、 2000W、第二高頻電力：0W、200W、600W)，自我偏壓電 壓的絕對値I Vdc |與電漿密度Ne的關係圖。 第1 7圖是表示高頻電力的高頻電力功率與多結晶矽膜 的蝕刻速率的關係以及相當於高頻電力的高頻電力功率與 蝕刻選擇比的多結晶矽膜的蝕刻速率/ Si02膜的蝕刻速率 比的關係圖。 第1 8圖是表示第二高頻電力的高頻電力功率與多結晶 矽膜的蝕刻速率的關係以及相當於第二高頻電力的高頻電 力功率與蝕刻選擇比的多結晶矽膜的鈾刻速率/ Si 02膜的 -32- 1233644 (27) 蝕刻速率比的關係圖。 第19圖表示以電極間間隙爲25mm的時候和爲4 Omm 的時候來比較電漿氣體使用Ar氣體時的Ar氣體流量、晶 圓中心部、周邊部的壓力差△ P的關係圖。 [圖號說明] 1 :處理室 la:上部 1 b :下部 2:支撐台 3:絕緣板 4:支撐台 5 :聚焦環 6 :靜電夾頭 6 a :電極 6 b :絕緣體 7:滾珠螺桿 8 :波紋管 9 :波紋管套 1 〇 :高頻電源 11:匹配箱 1 2 :給電線 1 3 :直流電源 1 4 :擋板 -33- 1233644 (28) 1 5 :處理氣體供給系統 15a:氣體供給配管 16:淋浴噴頭 1 6 a :氣體導入部 1 7 .·空間 1 8 :氣體吐出孔 1 9 :排氣口 2 0 :排氣系統 2 1 :環形磁石 22:整流子片磁石 2 4 :閘閥 25:旋轉機構 26:第二高頻電源 3 1 :矽基板 3 2 :多結晶矽膜 33:無機系材料膜 4 1 :矽基板 42:無機系材料膜 43:多結晶矽膜 44:光阻膜Relation diagram of the ratio of the etching rate of the Si02 film (also referred to as the etching selection ratio in FIG. 14). FIG. 15 is a ratio of the etch rate of the polycrystalline silicon film corresponding to the etching rate of the polycrystalline silicon film and the uranium etch selectivity ratio of the etch rate of the polycrystalline silicon film to the etch rate of the Si 0 2 film (at Fig. 15 is also shown as a relationship diagram of the etching selection ratio). From these figures, it is confirmed that the etching rate of the polycrystalline silicon film at 100 MHz is slightly higher than that at 40 MHz, and the etching selection ratio is also high at the same high-frequency power and processing chamber pressure. For the same high-frequency electric power, it is confirmed that a high etching selectivity can be obtained at a lower pressure at 100 MW Η z than at 40 MW Η z. As shown in FIG. 15, with the same high-frequency power and etching rate, it is also confirmed that the etching selection is higher than that at 100MHz and 40MHz. From these cases, it is confirmed that at 100MHz, it is beneficial to the shape of the etching. A high etching selectivity can be obtained under controlled low pressure conditions, and both high etching selectivity and good etching shape controllability can be achieved. Among the effects of pressure, 40MHz or 100MHz, it is confirmed that the etching rate and etching selection ratio of the polycrystalline silicon film are good at high voltage. However, from the viewpoint of controllability of the etched shape of the polycrystalline silicon film, it is confirmed that the low voltage is more preferably 13.3 Pa or less. Next, the results of using the actual etching gas (HBr) to grasp (measure) the absolute 値 | Vdc I and plasma density of the self-bias voltage when 100MHz high-frequency power is applied will be described. Fig. 16 shows the relationship between the absolute value of self-bias voltage and the density of plasma -26 · 1233644 (21) for the case where plasma is formed with HBr gas at a frequency of 100 MHz for high-frequency power. The horizontal axis is the absolute 値 I Vdc I of the self-bias voltage, and the vertical axis is the plasma density. Plasma density is measured using a microwave perturbator. The pressure in the processing chamber at this time was 2.7 Pa (20 mTorr). And the power of 100MHz high-frequency power will change between 500 ~ 2000W, so that the plasma density and the absolute self-bias voltage 値 | Vdc | will be changed. When the power of 100MHz high-frequency power is 500W, the second high-frequency power of 13MHz will overlap at 0W, 200W, and 600W. It can be seen from Fig. 16 that the higher the high-frequency power applied even at each frequency, the greater the plasma density Ne and the absolute value of self-bias voltage 値 | Vdc I. As shown in Fig. 16, the plasma of the actual etching gas tends to be slightly lower than the plasma of Ar gas (see Fig. 6). On the other hand, the lower-frequency second high-frequency power (13MHz) overlaps. If the power increases, the self-bias voltage tends to increase. It can be understood from Fig. 16 that when the second high-frequency power is not overlapped, even if the plasma density increases, I Vdc | will not rise much and will be suppressed below about 1000V. It was found that high plasma density and low self-bias voltage can be achieved. FIG. 17 is the relationship between the high-frequency power power of the high-frequency power and the etching rate of the polycrystalline silicon film when the second high-frequency power is not overlapped, and the high-frequency power equivalent to the high-frequency power and the etching selection ratio. A graph showing the relationship between the ratio of the etching rate of the polycrystalline silicon film to the etching rate of the Si02 film. When the high-frequency power is increased, the etching rate of the polycrystalline silicon film becomes larger, but the selection ratio becomes smaller. Therefore, it is -27-1233644 at about 15 0 W (about 4 · 7 7 W / c m2) or less. (22) Good. On the one hand, since the etching rate is reduced when the power is reduced, the selection ratio is increased. Therefore, it is preferably about 500 W (about 1.5 W / cm2) or more. From Figs. 16 and 17, it can be confirmed that a high frequency of 100 MHz can be used to obtain a desired polycrystalline silicon etching rate, and the polycrystalline silicon film can be etched with a high etching selectivity ratio to the inorganic material film. From Figures 16 and 17, it can be understood that at low voltages, high plasma density and low self-bias voltage can be used to etch a polycrystalline silicon film using a higher selection ratio and the required etching rate than conventionally, so consider The plasma density is 5 X 1 09 ~ 2xl01 () cnr3, and the self-bias voltage of the electrode is preferably less than 200V. In addition, as the process gas, a gas containing Cl2 gas may be used in addition to the gas containing HBr gas. However, in the latter case, it has been confirmed that the proper plasma density range has the same range as described above. On the one hand, Figure 18 is a case where the high-frequency power of the high-frequency power is fixed at 500W, and the high-frequency power of the second high-frequency power is overlapped. The relationship between the etching rate of the silicon film and the relationship between the etching rate of the polycrystalline silicon film corresponding to the second high-frequency power and the etching selection ratio / etching rate of the Si02 film are shown. As can be understood from FIGS. 16 and 18, the second high-frequency power at 13 MHz overlaps, and as the power increases, the etching rate increases, and the self-bias voltage of the electrode also increases. When the self-bias voltage becomes larger, the etching selection ratio tends to decrease. Until the self-bias voltage is 200V, the second high-frequency power is about 200 W (about 0.64 W / cm2), and the etching selection ratio can be maintained within an allowable range. . -28- 1233644 (23) Therefore, the power (bias power) of the overlapping second high-frequency power is increased, and the etching selection ratio can be maintained above 10 and the etching rate can be increased. In the above test, the gap between the electrodes was 27 mm. However, as described above, if the distance between the electrodes is too small, the surface pressure distribution (the pressure difference between the central portion and the peripheral portion) of the wafer W of the substrate to be processed becomes large, resulting in Problems such as reduced etching uniformity. Therefore, the actual distance between the electrodes is preferably 35 to 50 mm. This situation is explained with reference to FIG. 19. FIG. 19 is a graph comparing the relationship between the Ar gas flow rate when the plasma gas uses Ar gas, and the pressure difference ΔP between the center portion of the wafer and the peripheral portion of the wafer with the gap between the electrodes of 25 mm and 40 mm. . As shown in Fig. 19, when the gap is 40 mm, the pressing difference ΔP is smaller than 25 mm. When the gap is 25 mm, the pressure rises with the Ar gas flow rate, and the pressure difference △ P tends to increase sharply. The gas flow rate is above 0.3 L / min, which will cause problems such as a decrease in etching uniformity. 0.27Pa (2mTorr) of the allowable maximum pressure difference ΔP. For this reason, when the gap is 40mm, the pressure difference does not need to be based on the gas flow rate, and the pressure difference is not less than 0.27Pa (2mT0. Allowable maximum pressure difference for problems such as reduced etching uniformity. Furthermore, the present invention is not limited to the above embodiment, and various changes can be made. For example, in the above embodiment, the silicon film indicates the use of a polycrystalline silicon film, but it is not limited to this. It is also possible to use other silicon films such as a single crystalline silicon film or an amorphous silicon film. In the above embodiment, the magnetic field formation means uses a plurality of commutator plate magnets made of permanent magnet-29-1233644 (24) to A multi-electrode ring magnet arranged in a ring shape around the processing chamber, but it is not limited to this form as long as it can form a magnetic field around the processing space and seal the plasma. Must be required. That is, plasma etching can be performed in the absence of a magnetic field. Plasma etching can be performed by applying a horizontal magnetic field to the processing space and performing plasma etching in an orthogonal electromagnetic field. The present invention is also applicable to the engraving process. In the embodiment described above, high-frequency power for plasma formation is applied to the lower electrode, but it is not limited to this, and may be applied to the upper electrode. Furthermore, the layer structure of the substrate to be processed is not limited. It is not limited to those shown in FIG. 3 or FIG. 4 of the above embodiment. Even the substrate to be processed indicates the case where a semiconductor wafer is used, but it is not limited to this. It is also applicable to polycrystalline silicon films of other substrates to be processed. [Schematic explanation] Figure 1 is a schematic cross-sectional view showing a plasma etching apparatus according to an embodiment of the present invention. Figure 2 is a schematic view showing a processing chamber of the plasma etching apparatus arranged in Figure 1. A horizontal cross-sectional view of a surrounding ring magnet. Fig. 3 is a cross-sectional view showing an example of a structure of a semiconductor wafer to which the plasma etching of the present invention is applied. Fig. 4 is a semiconductor crystal to which the plasma etching of the present invention is applied. Sectional view of another example of a circular structure. Fig. 5 is a schematic cross-sectional view partially showing a plasma processing apparatus provided with a high-frequency power source for plasma generation and a high-frequency power source for ion introduction. -30- 123364 4 (25) Figure 6 is a graph showing the relationship between the absolute self-bias voltage 与 | Vdc | and the plasma density Ne of the high-frequency power in the plasma of argon gas at 40 MHz and 100 MHz. 7A FIG. 7B is a graph showing an increase in etching rate of a polycrystalline silicon film with respect to a wafer position at a high-frequency power of 100 MHz at each time when the high-frequency power is 500 W, 1,000 W, and 15 0 W. FIG. 7B is Graphs showing the difference between the etching rate of the polycrystalline silicon film for the wafer position when the high-frequency power is 500W, 1,000W, and 1500W at each time. Figure 8 shows the high-frequency power. When it is 40MHz and 100MHz, it shows the relationship between high-frequency power and uranium etching rate of polycrystalline silicon film. Fig. 9 is a graph showing the relationship between the high-frequency power power and the etching rate of the Si02 film when the high-frequency power is 40 MHz and 100 MHz. Figure 10 shows the relationship between the high-frequency power power and the etching rate of the polycrystalline silicon film when the high-frequency power is 40MHz and 100MHz, and the etching rate of the polycrystalline silicon film relative to the high-frequency power power and the etching selection ratio / Relation diagram of the etching rate ratio of the Si02 film. Fig. 11 is a graph showing the relationship between the etching rate of the polycrystalline silicon film and the etching rate ratio of the Si02 film corresponding to the etching rate of the crystalline silicon film and the etching selectivity ratio when the high-frequency power is 40 MHz and 100 MHz. Fig. 12A is a graph showing the relationship between the pressure in the processing chamber during etching and the etching rate of the polycrystalline silicon film when the high-frequency power is 100 MHz and 40 MHz. Fig. 12B is a graph showing the relationship between the etching rate of the Si02 film when the pressure in the processing chamber during etching and the high-frequency power -31-1233644 (26) are 100 MHz and 40 MHz. Fig. 13 is a graph showing the relationship between the etching rate of the polycrystalline silicon film corresponding to the pressure in the processing chamber and the etching selection ratio / the etching rate ratio of the Si02 film when the high-frequency power is 40 MHz and 100 MHz. Figure 14 shows the relationship between the pressure in the processing chamber and the etching rate of the polycrystalline silicon film when the high-frequency power is 40MHz and 100MHz, and the etching rate of the polycrystalline silicon film corresponding to the high-frequency power power and the etching selectivity ratio / Si02 film. Diagram of the etch rate ratio. Fig. 15 is a graph showing the relationship between the etching rate of the polycrystalline silicon film corresponding to the etching selectivity ratio of the polycrystalline silicon film and the etching rate ratio of the Si02 film when the high-frequency power is 40 MHz and 100 MHz. Fig. 16 shows when the frequency of high-frequency power is 100 MHz and the second high-frequency power is 13 MHz in the plasma of HBr gas, and each high-frequency power is changed (high-frequency power: 500W, 1,000W , 1 500W, 2000W, second high-frequency power: 0W, 200W, 600W), the relationship between the absolute self-bias voltage 电压 I Vdc | and the plasma density Ne. Figure 17 shows the relationship between the high-frequency power of high-frequency power and the etching rate of a polycrystalline silicon film, and the etching rate of a polycrystalline silicon film corresponding to the high-frequency power of high-frequency power and the etching selection ratio / Si02 film. Diagram of the etch rate ratio. Figure 18 shows the relationship between the high-frequency power of the second high-frequency power and the etching rate of the polycrystalline silicon film, and the uranium of the polycrystalline silicon film corresponding to the high-frequency power of the second high-frequency power and the etching selection ratio. Etching rate / -32-1233644 (27) Etching rate ratio of Si 02 film. Fig. 19 shows the relationship between the Ar gas flow rate when the plasma gas uses Ar gas, and the pressure difference ΔP at the center and peripheral portions of the crystal circle when the gap between the electrodes is 25 mm and when the gap is 40 mm. [Illustration of drawing number] 1: processing chamber la: upper part 1 b: lower part 2: support stand 3: insulating plate 4: support stand 5: focusing ring 6: electrostatic chuck 6 a: electrode 6 b: insulator 7: ball screw 8 : Corrugated tube 9: Corrugated tube cover 1 〇: High-frequency power supply 11: Matching box 1 2: Power supply line 1 3: DC power supply 1 4: Baffle-33-1233644 (28) 1 5: Process gas supply system 15a: Gas Supply piping 16: shower head 16a: gas inlet 17 ... space 1 8: gas discharge hole 19: exhaust port 2 0: exhaust system 2 1: ring magnet 22: commutator plate magnet 2 4: Gate valve 25: Rotating mechanism 26: Second high-frequency power source 3 1: Silicon substrate 3 2: Polycrystalline silicon film 33: Inorganic material film 4 1: Silicon substrate 42: Inorganic material film 43: Polycrystalline silicon film 44: Light Barrier film