TWI233268B - Transceiver for full duplex communication systems - Google Patents

Abstract

A transceiver in a full duplex communication system, the transceiver includes: a hybrid circuit for transmitting a transmit signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmit signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Description

1233268 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a transceiver, and more particularly to a transceiver suitable for a full-duplex communication system. [Previous technology] Due to the advancement of technology, the application of the Internet has become wider and wider. Figure 1 is a simplified schematic diagram of a conventional Transceiver 100 used in a channel of an Ethernet network device. The transceiver 100 includes: a hybrid circuit (Hybird) 115, which is a three-terminal device. The transceiver 100 transmits the signal Tx to be transmitted to the channel 110 through the hybrid circuit 115, and the other end of the channel 110 transmits The signal Rx is mixed with TX to form Rx + Tx. The hybrid circuit 115 includes an echo cancellation circuit 130 for removing the Tx signal from the Rx + Tx signal on the channel 110 to generate a received signal Rx, and An analog front end (AFE) circuit 140 is coupled to the hybrid circuit 115 to receive and process the received signal Rx. The hybrid circuit 115 further includes a digital analog conversion circuit 120. However, in the conventional technology, since the unavoidable parasitic capacitance effect is not taken into consideration, the echo interference effect in the transceiver 100 cannot be minimized. In addition, the open circuit output impedance of the hybrid circuit 115 is a finite resistance Ra, while the input impedance of the analog front-end circuit 140 is a finite resistance Rb, the insertion loss of the signal is Ra / (Ra + Rb), and the analogy The equivalent output impedance of the front stage of the front-end circuit 140 becomes Ra // Rb, thereby reducing the signal-to-noise ratio (SNR) of the received signal Rx. Therefore, the conventional transceiver 100 will set a zero gain buffer (Unit Gain Buffer) 170 before the analog front-end circuit 140 to provide a very large input impedance and a very small output resistance 1233268 to drive the secondary circuit. The analog front-end circuit 140 can prevent signals from being transmitted from the analog front-end circuit 140 to the hybrid circuit 115. Furthermore, the conventional transceiver 100 is also provided between the analog front-end circuit 140 and a sampling and holding circuit 160, and a zero gain buffer 180 is also provided to provide a very small output impedance to further reduce the resistor-capacitor network. Equivalent resistance value, so that the operating frequency of the sample and hold circuit 160 can be increased. The conventional receiver uses a zero-gain buffer to drive the secondary circuit, which will increase the cost and complexity of the circuit, increase the degree of noise and harmonic distortion of the active components in the circuit, and reduce the quality of the signal. [Summary of the Invention] In view of this, one object of the present invention is to provide a transceiver, which uses a proper circuit structure design to simplify the complexity of the circuit to solve the above problems. A tenth embodiment of the present invention provides a transceiver of a communication system. The transceiver includes: a hybrid circuit (Hybird Circuit) connected to a channel handle for outputting a transmission signal or receiving through the channel. A receiving signal, the hybrid circuit includes an echo cancelling device for removing a component of the transmitting signal from the receiving signal; wherein the hybrid circuit outputs a processed receiving signal; and a gain amplifier, It is an amplifier-resistor-capacitor automatic gain amplifier (OP-RC AGC), which is directly coupled to the hybrid circuit to amplify the processed received signal. The gain amplifier provides one of the echo cancellation devices. Terminal is a virtual ground terminal. According to the present invention, the effect of the parasitic capacitance can be minimized by the effect of the echo canceling device, and the echo canceling performance can be optimized. 11 1233268 Benming does not need to mediate any buffer circuit to listen to private a & + 赭 上帝 政 播 上 丄 丄 峪 木 驱动 人人 电路 circuit, which can greatly reduce the time: road = structure, cost and power consumption, reduce active components True, the signal quality can be effectively improved. A wave loss [Embodiment] = Look at the small signal model of the hybrid circuit 115 shown in the figure. ^ In the figure, the digital analog conversion circuit 12G is a circuit such as an id, and the echo cancellation circuit 13 is used. The circuit equivalent is ", and the Hirohara system is the equivalent of the digital analog conversion circuit 120: to :, the purpose of the impedance Zc elimination, then the current source 1 (: and ^; Wen Xi lose = and react. If you want to achieve echo un The original and Id output currents are compared to the analog front-end circuit to the following two programs? ... must be offset each other. From the small signal model in Figure 3, we can get (1)

Vi = ^ [idZo + (z〇 + Rp) lc]

Si formula ⑴ knows that 'To eliminate the echo, that is, to make Vi = 0, then. IdZo + (Zo + Rp) lc = 〇 (2) can be obtained from equation (2): r — Zo (3) / c = 7; -Id

Rp + Zo — two of the anti- ^, the points of echo cancellation (Echo Free) and 1-^ 〖I 'The small signal model of the hybrid circuit 115 of the present invention will be as ra: ^ IS] KVL equation can be obtained: RP ^ ZUz〇 ^^ (4) 12 1233268 At this time, if Vi = 0, then equation (2) must also be satisfied: IdZo + {Zo + Rp) lc = 0, that is, equation (3) must be satisfied:

Ic = Id

Rp + Zo In other words, as long as the equivalent current source Ic satisfies the relationship of the above equation (3), the echo can be completely eliminated, and the impedance Zi can be any value. Therefore, in the circuit design, the realization of the stable ground point with a virtual ground point will not affect the above analysis. % The actual circuit needs to consider the parasitic capacitance effect, so the equivalent output impedance Zo in the above analysis is the load resistance Re (composed of the matching resistance Rm and the channel equivalent resistance Rc) and the parallel connection of the parasitic capacitance Ce (ZozRe / VCe) 'The size is shown in the following equation:

Zo

Re sReCe + 1 (5) Substituting equation (5) into equation (3), the following equation can be obtained:

Ic -Re Rp + Rq + sRt RpCe

Id = H (s) Id (6)

In equation (6), H (s) represents the relationship between Ic and Id, which is actually a low-pass transfer function. Fig. 5 is a schematic diagram showing a first embodiment of a receiver for a full-duplex communication system according to the present invention. In the transceiver 500 of the present invention, the analog front-end circuit 540 includes a gain adjustment circuit 542 for adjusting the amplitude of the received signal to increase the signal gain; and a filter 544 coupled to the gain adjustment circuit 542 for To filter out noise or 13 1233268 harmonics in the signal output by the gain adjustment circuit 542 and drive the next stage. In the preferred embodiment of the present invention, the gain adjustment + 542 can be realized by a programmable gain amplifier (PGA); ^^ 1 = can be used with an operational amplifier-resistor-capacitor (OP-RC) frame σσ filter (OP-RC Filter). The H (s) of the filter 570 in Fig. 6 is a low-pass conversion equation, which can be implemented in a digital or analog circuit manner so that it satisfies the aforementioned equation (6). For example, if it is implemented by a digital circuit, a digital low-pass filter (Digital Low Pass Filter); if it is implemented by an analog circuit, H (s) is a resistor-capacitor network low-pass ^ (Rc Network Low Pass Filter). If the semiconductor process is used, the resistance in the low-pass filter of the resistor-capacitor network can be realized by a MOS transistor. The resistance value is determined by the size of its gate voltage, and the capacitor can be a gold-layer capacitor or It is parasitic capacitance to achieve. In a better implementation, the current source (the circuit is equivalent to the current source Ia in FIG. 6) and the DC level of Η, so that the transistor in the current source Ic can work in the Saturation Region. In order to avoid the situation of signai DWorticm, the transmitter of the present invention has been improved. The echo has just been eliminated: the performance is two: the operation: the boost current source (ie, equivalent current source Η) can be a fixed current source Or an adjustable current source, that is, a boost current source. The signal provided may be a DC signal or an AC signal with a fixed DC component. It may also be a signal whose DC component is adjusted according to the size of the current source Ic. The receiver 500 of the present invention minimizes the phenomenon of echo interference by the action of the low-pass filter 57. In the transceiver 500 of the present invention, the gain adjustment circuit 542 in the analog front-end circuit 54 is implemented using an operational amplifier-resistor-capacitor (〇p_RC) circuit architecture, and the input impedance Zi of the gain adjustment circuit 542 is This can be achieved with a 1233268 resistor. One end of the input impedance Zi is connected to the node A, and the other end is connected to the Echo Free point of the transceiver 500. Due to the high loop gain characteristic of the OP-RC circuit architecture, the node A forms a virtual ground point. It is known from the foregoing analysis of the conditions required to cancel the echo that the magnitude of the input impedance Zi does not affect the function of the low-pass filter, the wave filter 570 and the echo cancel circuit 530 to cancel the echo. Therefore, the degree of freedom of the gain adjustment circuit 542 to adjust the gain can be greatly improved. At the same time, because the gain adjustment circuit 542 is implemented using the circuit structure of 0P-RC, it can obtain a very low output impedance, which is a good driver stage for the voltage signal, and can smoothly drive the next stage. Circuit (eg, wave 544). In this way, the transceiver 500 of the present invention does not need to mediate a zero-gain buffer between the analog front-end circuit 540 and its pre-stage, which reduces the complexity, cost and power consumption of the circuit, and reduces additional noise or resonance. The source of wave distortion. As mentioned earlier, in a multi-channel communication environment, signals between channels are prone to high-frequency interference (Cross Talk), and in a full-duplex communication environment, the components of the residual echo input to the analog front-end circuit 540 are also Mostly at high frequencies, the receiver 500 of the present invention uses a filter 544 to filter out residual echoes of high frequency components. Since the filter 544 of the present invention is a filter of the 0P-RC structure, its output impedance is extremely small, which can smoothly drive the next-stage circuit. If the second-stage circuit is a sampling and holding circuit 560 which is one of the preceding stages of the analog digital conversion circuit 550, the equivalent time constant of an RC network formed by the sampling and holding circuit 560 can be effectively reduced, and the sampling and holding The operating frequency of the reserved circuit 560. In the actual implementation of the circuit, due to the size of the parasitic capacitance Ce, the channel equivalent resistance Rc, and the impedance matching resistance Rm, it will be affected by factors such as the working environment, operating temperature, process differences, and so on. During the process of data transmission / reception China may change at any time. In order to achieve the effect of echo cancellation more accurately, the receiver 500 of the present invention may further be provided with a residual echo detection circuit (not shown), coupled with 15 1233268 to the analog digital conversion circuit 550, for detecting the analog digital conversion circuit 550. Echo Residue received. The residual echo detection circuit outputs a control signal to the low-pass filter 570 according to the detected residual echo to adjust the position of the pole (Pole) of the low-pass conversion equation H (s), so that the residual echo can be adjusted. To the minimum, the simplified equivalent circuit diagram is shown in Figure 7. In the description of the foregoing embodiments, “the hybrid circuit (Hybird) is used as the current mode (current mode) as an example. In fact, the structure and concept of the echo canceller of the present invention can also be applied to this. The hybrid circuit (Hybird) is a voltage mode mode receiver, which can also achieve the echo cancellation effect of the receiver of the present invention and the concept that the active components can be driven smoothly without the need for a zero gain buffer. FIG. 8 is a simplified equivalent circuit diagram of a voltage driving mode. Among them, Vo 'is the output of the line driving transmission circuit, Rk is the matching resistance, Vo is the signal to be transmitted through one of the one-line interface outputs, Re is the equivalent load resistance, and Ce is the parasitic capacitance. In the case of considering the parasitic capacitance effect, the equivalent output impedance Zo of the line driving transmission circuit is the parallel connection of the load resistance Re and the parasitic capacitance Ce (Zo = Re // Ce). The following equation can be obtained from the principle of voltage division:

Vo --- ^-Vo1 ----- Vo ^ h (s) 'Vof (7)

Zo + Rk R / c + Re + s Re RkCe Figure 9 shows a simplified equivalent circuit diagram of the second embodiment of the receiver of the present invention. The hybrid circuit (Hybird) of the transceiver 900 includes a line-driven transmission circuit 920 that outputs a transmission signal to a channel through an impedance matching resistor Rk; an echo cancellation signal generator 930 that couples the line-driven transmission circuit 920 with An echo cancellation signal is generated according to the transmission signal; and a cancellation module 942 is used in the line driving transmission circuit 920 and the echo cancellation signal generator 930 to remove the echo generated by the transmission signal. 16 1233268 The echo cancellation signal generator 930 generates the echo cancellation signal according to the output Vo ′ of the line driving transmission circuit 920, and transmits the echo cancellation signal to the cancellation module 942. The cancellation module 942 is used to remove the echo generated by the transmission signal. FIG. 10 illustrates an embodiment of the receiver 900 of the present invention. In this embodiment, the echo cancellation signal generator 930 is implemented by a resistor-capacitor network low-pass filter, which includes a resistor Ra and a capacitor Ca, and is used to output the signal Vo ′ from the line-driven transmission circuit 920. An echo cancellation signal Va is generated. The echo cancellation signal Va is input to an operational amplifier 950 of one of the cancellation modules 942 through a resistor R1, and the transmission signal Vo of the transmitter 900 is input to the operational amplifier 950 through a resistor R2. In the cancellation module 942, a resistor Rf has two ends, one end is connected to the input terminal of the operational amplifier 950, and the other end is connected to the output terminal of the operational amplifier 950 to control the amplification ratio of the operational amplifier 950. The operational amplifier 950 performs low-pass filtering and subtraction at the same time. After calculation, we can get:

Va ^ -—- Vo1 (8)

Ra + Rl-l · sCaRaRl

Va · sheng + Vo · sheng = -Vr (9) R1 R2 Assuming Vr = 0, combining the above equations (7), (8) and (9), we can get:

Ra + R1 + sCaRaRl (Re + Rk + sCeRtRk) R2 Therefore, as long as the following two relations (11) and (12) are satisfied, the echo can be completely offset:

CaRaRl = CeRkRl (11) 17 = + (12) 1233268 In practice, when the hybrid filter 944 of the receiver 900 is used, it is not necessary to connect the 944-Di and Γ-type circuits to the 944 of the 0P-Rc architecture. Smoothly drive the second-level electric booster and the OP-RC data wave booster to improve the sampling and holding circuit: fetch, and reserve circuit, the same buffer. ’Staff rate without the need for an intermediary for another zero gain

[Brief description of the figure] Brief description of the figure The figure is a simplified schematic diagram of a transceiver in a channel of a conventional Ethernet device. Figure ^ is a schematic diagram of some circuits in Figure 1. Fig. 1 is a small signal model of the previous stage of the analog front-end circuit in Fig. 1. Figure 4 is another small signal model of the pre-stage of the analog front-end circuit in Figure 1. FIG. 5 is a simplified schematic diagram of the first embodiment of the receiver of the present invention. Figure 6 is the equivalent circuit diagram of Figure 5. FIG. 7 is a simplified equivalent circuit diagram of another embodiment of FIG. 5. Figure 8 is a simplified equivalent circuit diagram of the one-line drive transmission circuit. FIG. 9 is a simplified schematic diagram of the second embodiment of the receiver of the present invention. Figure 10 is the equivalent circuit diagram of Figure 9. Symbols of the drawings: Receiver channel 100, 500 110 18 1233268 115, 510 hybrid circuit 120, 520 digital analog conversion circuit 130, 530 echo cancellation circuit 140, 540 analog front-end circuit 150, 550 analog digital conversion circuit 160, 560 Sample and hold circuit 170, 180 Zero gain buffer 212 Switch 214 Capacitor 512 line interface 514 Twisted pair 542 Gain adjustment circuit 544, 570, 944 Wavelet 920 line drive transmission circuit 930 Echo cancellation signal generator 942 Elimination module 950 operation Amplifier 19

Claims (1)

! 233268 Scope of patent application: i · A transceiver of a full-duplex communication system, the transceiver includes:-a hybrid circuit (Hybird Circuit), coupled to a channel, used to output through this channel A transmission signal or a reception signal, the hybrid circuit includes: an echo cancellation device for removing a component of the transmission signal from the reception signal; wherein the hybrid circuit outputs a processed reception signal And gain amplifier, which is an amplifier-resistance-capacitor automatic gain amplifier (〇P-RC AGC), which is directly coupled to the hybrid circuit to amplify the processed receiving afL number, which is a far-increasing lean amplifier One of the echo cancellation devices is connected to a virtual ground (Virtual Ground). 2. The receiver according to item 1 of the patent application range, wherein the gain amplifier has a low output impedance. . … 3. The receiver according to item 1 of the patent application range, wherein the gain amplifier has a high loop gain characteristic. 4. The receiver according to item 1 of the scope of patent application, wherein the gain amplifier comprises:-an operational amplifier coupled to the hybrid circuit;-a resistor having two ends, one end coupled to the input end of the operational amplifier, The other end is coupled to the output end of the operational amplifier; and a capacitor is coupled to the input end and the output end of the operational amplifier. 5. The receiver described in item 1 of the scope of patent application, further includes a filter, which is an amplifier-resistor-capacitive filter (p_RC fi 1 ter), which is directly coupled to the gain amplifier. In order to filter out the gain 20 1233268 to enlarge the noise or harmonics in the output signal. 6. The receiver as described in item 5 of the patent scope, wherein the wave filter has a low output impedance. 7. The transceiver according to item 5 of the scope of patent application, wherein the wave receiver has a high loop gain characteristic. 8. The receiver as described in item 5 of the scope of patent application, which further includes an analog digital conversion circuit, which is connected to the filter and used to digitize the signal after the wave. 9. The receiver described in item 8 of the scope of patent application, further comprising: a clock restorer coupled to the analog digital conversion circuit for generating a sampling clock for the analog digital conversion circuit to operate. 10. The receiver according to item 1 of the scope of patent application, wherein the echo cancellation device further comprises: a filter for outputting a filtered signal according to the transmission signal; and-an echo cancellation circuit, which is incorporated in the A filter for outputting an echo cancellation signal according to the filtered signal; wherein the echo cancellation signal corresponds to the transmission signal. Π. The receiver according to item 10 of the patent application scope, wherein the echo cancellation circuit further comprises: a boost current source for raising the DC level of the echo cancellation circuit. 12. The transmitter as described in item 10 of the scope of the patent application, wherein the receiver further includes: 21 1233268 Residual echo detection circuit, which is integrated with the analog digital conversion circuit, and is used according to a residual echo ( Echo Residue) outputs a control signal to control the filter. The transceiver as described in item 12 of the patent application scope, wherein the filter is a digital filter, and the control signal is used to adjust the finite impulse response (FIR) or infinite impulse response ( nR). 14. The transmitter according to item 1 of the scope of patent application, wherein the echo cancellation device comprises: an echo cancellation signal generator for generating an echo cancellation signal according to the transmission signal; and a cancellation module coupled to The echo cancellation signal generator is used to remove the echo generated by the transmission signal. 15 · = The transceiver as described in item 14 of the scope of patent application, wherein the cancellation module includes: an operational amplifier coupled to the echo cancellation signal generator; and a resistor having two ends and one end coupled to the operational amplifier The other end is consumed by the output end of the operational amplifier. 16. · A transceiver of a full-duplex communication system, including: a hybrid circuit (Hybird) coupled to a channel for transmitting signals or receiving a receiving signal through the channel output, the hybrid circuit includes ·· An echo cancellation device for removing the components of the transmission signal from the received signal; among them, the hybrid circuit outputs a processed received signal; and a filter, which is an amplifier-resistor-capacitor 〇p_RC filter, which is directly coupled to a gain amplifier to filter out noise or harmonics in the signal output by the gain amplifier. The filter is connected to the echo 22 1233268. Terminal is a virtual ground terminal. 17. The receiver described in item 16 of the scope of patent application. Low round-out impedance. 18. The high loop gain characteristic of the receiver as described in item 16 of the scope of patent application. Where the filter has a