TWI257774B - Echo cancellation device for full duplex communication systems - Google Patents

Abstract

An echo cancellation device in a full duplex communication system, the full duplex communication system includes a transmitter for transferring an near-end signal and a receiver for receiving a far-end signal, the echo cancellation device includes a filter for generating a filtered signal according to the near-end signal; a echo canceller coupled to the filter for generating a echo cancellation signal according to the filtered signal; at least one echo cancellation resistor coupled to the transmitter, the receiver, and the echo canceller; wherein the echo canceller further includes a current source for promoting DC level of the echo canceller.

Description

1257774 IX. Description of the Invention: [Technical Field] The present invention relates to an echo canceling apparatus, and more particularly to an echo canceling apparatus for a full duplex (Full Duplex) communication system. [Prior Art] Due to advances in technology, the use of the Internet has become more widespread. In view of the increasing bandwidth requirements for the network, the currently widely used Ethernet (Ethemet) has also increased the transmission speed of its poor-selling packets from the previous 1〇/1〇〇Mbps to more than 1Gbps. As is well known in the art, in an IGbps fast Ethernet device, each port has four channels (Channei) and each channel has a transmitter. Please refer to Figure 1. Figure 1 is a simplified schematic diagram of a conventional transceiver 100 for use in a channel of a fast Ethernet device. In general, the transceiver 100 is coupled to a twisted pair (Twist Lines) 118 via a line interface 116. As shown in Figure 1, the transceiver 1 can be divided into a transmitter (Transmitter)

Section 104 and a receiver (Receiver Section) 106. Among them, the transmitter! 〇4 includes a digital analog conversion circuit 108 (Digital_to_Anal〇gc〇nverter, DAC) for converting a Near-end Signal into an analog form, and transmitting it to the far line through the line interface 116 and the twisted pair 118. Another network device. The receiving 1257774 terminal 106 includes an analog front end (Anaiog Front End, AFE) circuit for performing signal processing on the received signal (Far_endsignal) received by the line interface 116, and then using an analog-to-digital conversion circuit (Anal〇g_toDigital Converter). , ADC) 114, the received signal is converted into a digital form, and then sent to the subsequent circuit. The fast Ethernet device uses four channels simultaneously with the other remote network device, and each channel performs transmission and reception functions at the same time. Therefore, the fast Ethernet network is a full-duplex communication system. As mentioned earlier, each channel in a fast Ethernet device performs both transmit and receive functions. When the channel transmits a signal, it will be caused by the channel received at the same time. This phenomenon is called echo interference (). In order to minimize the effects of echo interference, an echo cancellation circuit (Echo Cancellation) 110 and an echo cancellation resistor Rp are provided in the conventional transceiver 100. The echo cancellation circuit 110 is also generally a digital analog conversion circuit (DAC) 'for generating a cancellation signal corresponding to the transmission signal output by the digital analog conversion circuit 108, and the cancellation signal can offset the transmission signal to receive The effect of the end 1〇6 to achieve the effect of echo cancellation. Please refer to Figure 2. FIG. 2 is an equivalent circuit diagram of the transceiver 1 图 shown in FIG. In FIG. 2, the digital analog conversion circuit 1 8 and the echo cancellation circuit 110, which are touched by the transceiver, are respectively equivalent to the current sources Id and ic. For the receiving terminal 1〇6, if the purpose of echo cancellation is to be achieved, the effects of current source and recorded output current on the receiving terminals 1〇6 must be offset. 1257774 Please refer to Figure 3. Figure 3 is a small signal model of the equivalent circuit diagram shown in Figure 2. Where 'z〇 is the equivalent output impedance of the transmitting end 104, which is the equivalent input impedance of the receiving terminal 1〇6. 〇 is the electrical signal at the output of the transceiver j 00, that is, the Neai^endSignal output just sent by the transmitting end, and the paste is the echo caused by the transmitting signal to the receiving end 106 (4). ). In the conventional echo cancellation circuit 110, the wheel iB_Zg is regarded as the load-bearing power earning, and the load-resistance effect is determined by the matching resistance of the impedance used in the figure, and the receiver should belong to The ants of the channel are made of Re Re. Lai Sanjing's rare touch model can get the following equation:

Rp + Zi + Zo (1) From equation (1), we can see that 'to eliminate the echo, that is, to make v(four) must be satisfied · (2) (3) ^Zo + (z〇^Rp)Icss〇 from equation (2) Can get:

Rp + Z〇 In other words, as long as the relationship of equation (3) is given, the echo (Echo) 1257774 can be completely eliminated. When considering the effective output impedance z〇, as described above, the conventional echo cancel circuit 110 considers the equivalent output impedance z〇 as the load resistance Re of the matching resistor (four) and the channel, etc. However, the parasitic electricity valley effect that cannot be avoided when the actual circuit is implemented is not considered. Obviously, since the conventional technique only considers the equal-output impedance Zo as a simple load resistance Re, the echo interference effect in the receiver 1〇〇 cannot be minimized. In addition, V0>Vi is known from Figure 3. As the operating voltage of the integrated circuit (IC) becomes lower and lower, Vo and Vi also decrease. When the operating voltage of the integrated circuit is reduced to a certain extent, it is possible in the prior art to generate an equivalent current source Ic (that is, the conventional echo canceling circuit 11A). The situation of the saturation region CSaturationRegi〇n), which in turn causes the effects of signal distortion. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide an echo cancellation (Eeh() Caneellati()n) device for a full-duplex communication system, a parasitic capacitance effect in a side-filter cancellation circuit, To minimize echo interference. Another object of the present invention is to enable the MOS transistor in the Echo Cancellation device to be maintained in a saturation region, 1257774, to improve the performance of the echo cancellation device. In an embodiment of the present invention, an Echo Cancellation device for a full-duplex communication system is provided. The full-duplex communication system includes a transmitting end for transmitting a transmitting signal and a receiving end for Receiving a received signal, the echo canceling device includes: a filter for outputting a filtered signal according to the transmitted signal; an echo cancellation circuit (Echo Canceiier) coupled to the filter for outputting a signal according to the filtered signal An echo cancellation signal; at least one echo cancellation resistor coupled to the transmitting end, the receiving end, and the echo cancellation circuit; wherein the echo cancellation circuit further includes a boost current source for boosting the DC level of the echo level circuit. Implementation method] Please refer to Figure 3 again. The present invention takes into account the parasitic capacitance effect that is difficult to avoid when the actual circuit is implemented, so that the equivalent output impedance is 2. Corrected by the parallel connection of the load resistor (composed of the matching resistor Rm and the equivalent resistance Rc of the channel) and the parasitic capacitance ^ (5). In this flip, the equivalent output size is as shown in the following equation:

Zo

Re sReCe + 1 (4) Substituting equation (4) into equation (3), we can get the following equation 1257774 = H^'Id (5) From equation (5), the relationship between Ic and Id represented by H(8) is actually one. Low Pass Transfer Function. Please refer to FIG. 4, which is a simplified schematic diagram of a first embodiment 400 of a transceiver for use in a channel of a full duplex communication system. In the transceiver 400, the echo canceling apparatus proposed by the present invention includes an Echo Canceller 410 for generating an offset corresponding to one of the signals output by the digital analog converting circuit 4〇8. An echo cancellation resistor Qiu is coupled between the transmitting end 404 of the transceiver 400 and a receiving end 4〇6; a low pass filter 420' is connected to the echo canceling circuit 41 as its preamplifier The circuit; wherein the echo cancellation circuit 410 further includes a boost current source for boosting the vertical level of the echo circuit 41A. In practice, the echo cancellation circuit 41 can be a digital analog conversion circuit (DAC), and the boost current source can be implemented by one or more transistors. The function and setting purpose of the low pass filter state 420 can be used to reduce the parasitic capacitance effect of the actual circuit. Please refer to FIG. 5 for an equivalent circuit diagram of the transceiver 4 of the present invention. In Fig. 5, the circuit of the H400 is equal to the current source I_c, and the circuit of the boost current source is equivalent to the current source la. The analog analog conversion circuit still generates a transmission signal based on a digital signal. 1257774 The H in Figure 5 (the side as before (10) is a low-pass conversion equation, which can be implemented by a renewed or analog circuit to satisfy equation (5). For example, if it is a number 4 circuit Now, H(8) is a digital low-pass chopper (10) coffee]

Pass Filter), the right-hand side is implemented as an analog circuit, then H(s) is a resistor valley low-wave n (RCNet kLQwPassFil(10)), as shown in the equivalent circuit diagram in Figure 6. If the _ casting system is implemented, the resistance in the resistor-capacitor network low-pass filter 420 of the thin six can be realized by the Congdian crystal, and the resistance value is determined by the magnitude of the gate voltage Vd, and the capacitance can be utilized. Metal sandwich capacitors or parasitic capacitors are used. The echo canceling device of the present invention can make the echo canceling circuit 41G by means of low-pass filtering pure 0 side (the circuit is equivalent to the current source 1 (the output signal of the annihilation output is locked by the digital class _ circuit) (on the circuit Equivalent to the effect caused by the transmission signal (3) outputted by the money source (4), the phenomenon of interference will be minimized. As can be seen from the foregoing, the filter 420 and the echo cancellation circuit 41 can be simultaneously eliminated. Echo interference and overcoming the parasitic capacitance effect. In addition, the present invention utilizes the boost current source (ie, the equivalent current source la in Gang 5 and Figure 6) to improve the DC level of Vi' so that the electric (four) financial touch The crystal can be maintained in the saturation region (SaturationRegion) to avoid signal distortion (& 31 Distortion), thereby improving the performance of the echo cancellation circuit 41 of the present invention to eliminate echo. In practice, the boost current of Figure 4 The source (ie, the equivalent current source 13) may be a fixed current source or an adjustable current source, that is, the signal provided by the boost current source Ia 1257774 may be a DC signal with a fixed DC component. The alternating signal may also be a signal whose DC component is adjusted according to the magnitude of the current source Ic. Referring to FIG. 7 , which is a second embodiment of the present invention for the transmission state in the full duplex communication system. 7〇〇 Simplified schematic diagram. In the actual implementation of the circuit, due to the size of the parasitic capacitance Ce, the channel equivalent resistance rc and the impedance matching resistance ^, it will be affected by the working environment, operating temperature, process variation, etc. In the process of transmitting/receiving data, it may change at any time. In order to achieve the effect of echo cancellation more accurately, in the second embodiment of the present invention, a residual echo detecting circuit is additionally provided at the receiving end 7〇6. 722, used to detect the residual echo (Echo Residue) received by the receiving end 706. The residual echo detecting circuit 722 outputs a control signal to a low pass filter 72A according to the detected residual echo to adjust The position of the low-pass conversion equation H(s) pole (P〇le) is such that the residual echo energy can be adjusted to a minimum. Please refer to Fig. 8. Fig. 8 is an equivalent circuit diagram of the receiver 7〇〇 of the present invention.The low pass filter 720 to a digital-based low-pass filter is implemented, the residual echo sensing circuit 722 may detect Calls adjusted digital finite impulse response low pass filter based on the residual echo 72〇

I should be a factor of (Finite Impulse Response, FIR) or Infmite Impulse Response (IIR). If the low pass filter 720 is implemented with a _resistive capacitor network low pass filter, the residual echo detection circuit 722 can adjust the capacitance or resistance value of the resistor-capacitor network low pass filter 720 based on the residual echo. For example, if the resistance in the resistor-capacitor network low-pass filter 720 is implemented by a MOS transistor, the residual echo detection circuit 722 can adjust 12 1257774 by controlling the gate voltage vd of the MOS transistor: The resistance and capacitance (RC) value of the SG network i-pass filter 720 is dynamically dependent on the circuit of the 转=============================================================== The system and implementation of the upgrade mia are substantially the same as those of the boost current source Ia of FIG. 4, and therefore will not be described again. The above description is only the preferred embodiment of the present invention, and all the special modifications made according to the scope of the patent application of the present invention should be covered by the patent of the present invention. [Simple description of the diagram] Figure 2 is the equivalent circuit diagram of the conventional transceiver after the transmission and reception in the channel of the fast Ethernet device. Figure 2 is a small signal model of the equivalent circuit diagram of Figure 1. First implementation of the transceiver

Figure 4 is a simplified schematic view of a channel for a full duplex communication system of the present invention. Figure 5 and Figure 6 are equivalent circuit diagrams of the first embodiment of the transceiver of the present invention. Figure 7 is a simplified schematic diagram of the first example of the transceiver in the channel of the full dual 1 communication system. & Figure 8 is an equivalent circuit diagram of a second embodiment of the transceiver of the present invention. 13 1257774 [Description of Symbols] 100, 400, 700 Transmitter 104, 404, 704 Transmitter 106, 406, 706 Receiver 108, 408, 708 Digital analog conversion circuit 110, 410, 710 Echo cancellation circuit 112, 412, 712 analog front end circuit 114, 414, 714 analog digital conversion circuit 116, 416, 716 line interface 118, 418, 718 twisted pair 420, 720 low pass filter 722 residual echo detection circuit

Claims (1)

1257774 X. Patent application scope: 1·- for the full double guard rail, the echo of the system; the Xiao (touch) Canedlati (10) device, wherein the full duplex communication system includes a transmitting end for transmitting one Transmitting a signal, and receiving-receiving a receiving signal, the echo canceling device includes: a filter for outputting a filtered signal according to the transmitted signal; - an echo cancellation circuit coupled to the filter, the rib is based on the filtering The signal output an echo cancellation signal; and at least one echo cancellation resistor coupled to the transmitting end, the receiving end, and the echo cancellation circuit; wherein the time consuming circuit further includes: boosting the current source, and removing the echo by bribing The DC level of the circuit. 2. The device as claimed in the application of the patent phantom, the echo cancellation signal corresponding to the transmission signal. The device of claim 1, wherein the echo cancellation circuit is a digital analog conversion circuit. The device according to the first aspect of the invention is the apparatus of the invention, wherein the filter is a digital liquid. The device of claim 5, wherein the filter is a resistance electric 15 1257774. Network filter. 7 Applying for the device described in the patent specification, the _ is _ wave state. 7. The device of the application of the smear item, the towel axis device further comprises a residual returning yaw circuit for controlling the signal according to the residual echo (touch Residue) of the receiving end to control The chopper. 8·-Echo echo cancellation for full-duplex communication systems (4). The brain (10) device, wherein the king duplex communication system includes a transmitting end for transmitting and transmitting signals, and a receiving end for receiving a receiving signal, the echo canceling device comprising: a device for transmitting signals according to the signal Output-ship signal; 曰/xiao division circuit, and the chopper device, for outputting an echo cancellation signal according to the filtered signal; and removing the resistor, and the transmitting end, the receiving end, and the echo cancellation a circuit coupling; and a residual back-to-day bias circuit for outputting a control signal according to the residual echo (Residue) of the receiving end to control the filter; wherein the phase sound; the Xiao divide circuit further includes: boosting current Source to boost the DC level of the echo cancellation circuit. 9. The device of claim 8, wherein the echo cancellation signal corresponds to the 16 1257774 transmission signal. 10. The device of claim 8, wherein the echo cancellation circuit is a digital analog conversion circuit. 11. The skirt of claim 8, wherein the waver is a digital filter. 12. The device of claim U, wherein the control signal is used to adjust a finite pulse of the digital filter and the filter (Finite Impulse Resp_, _ a plurality of coefficients. 13. If applying for a full-time The apparatus of item n, wherein the (four) signal is used to adjust a plurality of coefficients of an infinite impulse response (Infinite Impulse Resp〇nse, IIR) of the digital filter. The wave filter is a resistor-capacitor network filter. 15. For the device described in claim 14, the resistor-capacitor network chopper includes a resistor. In the device, the 憎 resistor residual network filter includes a -MOS transistor, and the circuit is equivalent to a resistor. 17 1257774 17. The splicing according to claim 16 of the patent application, wherein the control signal is used To control the gate current of the MOS transistor. The device of claim 1, wherein the resistor-capacitor network filter comprises a capacitor. 19 as described in claim 18 Device, where the electricity It is a parasitic capacitor '20' - a transceiver for a full-duplex communication system, comprising: a receiving end for receiving a receiving signal, and a transmitting end coupled to the receiving end For transmitting a transmission signal, the transmission end includes a filter for outputting a filtered signal according to the transmission signal; an echo cancellation circuit (Echo Canceller) coupled to the filter for relieving The filter signal outputs an echo cancellation signal; and at least one echo cancellation resistor is coupled to the transmitting end, the receiving end, and the echo cancellation circuit; wherein the echo cancellation circuit further includes a boost current source for boosting the echo Eliminate the DC level of the circuit. XI. Schema: 18