TW200533092A - Transceiver for full duplex communication systems - Google Patents

Abstract

A transceiver in a full duplex communication system, the transceiver includes: a hybrid circuit for transmitting a transmit signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmit signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Description

200533092 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a transceiver, especially a transceiver suitable for a full-duplex communication system. [Previous technology] Due to the advancement of technology, the application of the Internet has become wider and wider. Figure 1 is a simplified schematic diagram of a conventional Transceiver 100 used in a channel of an Ethernet network device. The transceiver 100 includes: a hybrid circuit (Hybird) 115, which is a three-terminal device. The transceiver 100 transmits the signal Tx to be transmitted to the channel 110 through the hybrid circuit 115, and the other end of the channel 110 transmits The signal Rx is mixed with TX to form Rx + Tx. The hybrid circuit 115 includes an echo cancellation circuit 130 to remove the Tx signal from the Rx + Tx signal on the channel 110 to generate a received signal Rx, and An analog front end (AFE) circuit 140 is coupled to the hybrid circuit 115 to receive and process the received signal Rx. The hybrid circuit 115 further includes a digital analog conversion circuit 120. However, in the conventional technology, since the unavoidable parasitic capacitance effect is not taken into consideration, the echo interference effect in the transceiver cannot be minimized. In addition, the open circuit output impedance of the hybrid circuit 115 is a finite resistance Ra, while the input impedance of the analog front-end circuit 140 is a finite resistance Rb, the insertion loss of the signal is Ra / (Ra + Rb), and the analogy The equivalent output impedance of the front stage of the front-end circuit 140 becomes Ra // Rb, thereby reducing the signal-to-noise ratio (SNR) of the received signal Rx. Therefore, the conventional transceiver 100 will be provided with a zero gain buffer (Unit Gain Buffer) 170 before the analog front-end circuit 140, which is used to provide a maximum input impedance and a minimum output resistance 200533092. Drive the secondary analog front-end circuit 140 and prevent signals from being transmitted back from the analog front-end circuit 140 to the hybrid circuit 115. Moreover, the conventional transceiver 100 is also provided between the analog front-end circuit 140 and a sampling and holding circuit 160, and a zero gain buffer 180 is also provided to provide a very small output impedance to further reduce the resistor-capacitor network. Equivalent resistance value of the circuit, so that the working frequency of the sample and hold circuit 160 can be increased. The conventional receiver uses a zero-gain buffer to drive the secondary circuit, which will increase the cost and complexity of the circuit, increase the degree of noise and harmonic distortion of the active components in the circuit, and reduce the quality of the signal. [Summary of the Invention] In view of this, one object of the present invention is to provide a transceiver, which uses a proper circuit structure design to simplify the complexity of the circuit to solve the above problems. An embodiment of the present invention provides a transmitter of a communication system. The transmitter includes a hybrid circuit (Hybird Circuit) connected to a channel for outputting a transmission signal through the channel. Or receiving a reception signal, the hybrid circuit includes: an echo cancelling device for removing a component of the transmission signal from the reception signal; wherein the hybrid circuit outputs a processed reception signal; and a gain amplifier Is an amplifier-resistor-capacitor automatic gain amplifier (OP-RC AGC), which is directly coupled to the hybrid circuit to amplify the processed received signal. The gain amplifier provides one of the echo cancellation devices. One end is a virtual ground terminal. According to the present invention, the effect of the parasitic capacitance can be minimized by the effect of the echo canceling device, and the echo canceling performance can be optimized. 11 200533092 The present invention does not need to interpose any buffer circuit to drive the secondary circuit, which can greatly simplify the circuit structure, cost and power consumption, reduce noise and harmonic distortion of active components, and effectively improve the signal quality. [Embodiment] FIG. 3 illustrates a small signal model of the hybrid circuit 115 in FIG. In FIG. 3, the digital analog conversion circuit 120 of FIG. 1 is equivalent to a current source Id, while the echo cancellation circuit 130 is equivalent to a current source Ic, and the impedance Zo is equivalent to the digital analog conversion circuit 120. Output impedance. If the purpose of echo cancellation is to be achieved, the effects of the output currents of the current sources Ic and Id on the analog front-end circuit 140 must offset each other. From the small signal model in Figure 3, the following equations can be obtained:

Vi =-[idZo + (Zo + Rp) lc] (1) As can be seen from equation (1), if you want to eliminate the echo, that is, to make Vi = 0, you must satisfy:

IdZo + (Zo + Rp) lc = 0 (2) From equation (2) we can get: ic = ^ -id (3)

Rp + Zo When the two ends of the impedance Zi are respectively the point of echo cancellation (Echo Free) and a stable ground point, the small signal model of the hybrid circuit 115 of the present invention will be shown in Figure 4. At this point, solving the KCL and KVL equations gives:

Vi _ ~ ziildz ° + (z ° + ⑷ " Rp + Zi + Zo 12 200533092 'At this time, if Vi = 0, then equation (2) must also be satisfied: IdZo + (Zo + Rp) lc = 0 That is, equation (3) must be satisfied: J-Z〇 ^ Ic = -Id Rp + Zo. In other words, as long as the equivalent current source Ic satisfies the relationship of equation (3) above, the echo can be completely eliminated, and the impedance Zi can be any value. So in circuit design, the realization of the stable ground point with a virtual ground point (Virtual Ground) will not affect the above analysis. The actual circuit needs to consider the parasitic capacitance effect, so the equivalent in the above analysis The output impedance Zo is the parallel connection (ZozRe / ZCe) of the load resistance Re (consisting of the matching resistance Rm and the equivalent resistance Rc of the channel) and the parasitic capacitance Ce. Its size is as shown in the following equation Re

Zo sR ^ Ce + l (5) Substituting equation (5) into equation (3), the following equation can be obtained: -Re

Ic

Rp + Re + s R ^ RpCe

Id = H (s) Id (6) In equation (6), H (s) represents the relationship between Ic and Id, which is actually a low-pass transfer function. Fig. 5 is a schematic diagram showing a first embodiment of a receiver for a full-duplex communication system according to the present invention. In the transceiver 500 of the present invention, the analog front-end circuit 540 includes a gain adjustment circuit 542 for adjusting the amplitude of the received signal to increase the signal gain; and a filter 544 coupled to the gain adjustment circuit 542 for To filter out noise or 13 200533092 harmonics in the signal output by the gain adjustment circuit 542 and drive the next stage. In the preferred embodiment of the present invention, the gain adjustment circuit 542 can be implemented by using a privately-available display amplifier, and the filter 544 can be implemented by using an operational amplifier-resistor-capacitor (0P-RC). The structure is implemented by the OP-RC Filter. The H (s) of the filtered state 570 in Fig. 6 is a low-pass conversion equation, which can be implemented digitally or by analog circuits, so that it satisfies the aforementioned equation (6). For example, if implemented in a digital circuit, H (s) is a digital low pass filter; if implemented in an analog circuit, H (s) is a resistor and capacitor Rc Network Low Pass Filter. If the semiconductor process is used for implementation, the resistance in the low-pass filter of the resistor-capacitor network can be realized by a M0S transistor. Its resistance value is determined by the size of its gate voltage, and the capacitor can be a metal sandwich capacitor or It is parasitic capacitance to achieve. In a preferred embodiment, the present invention further includes a boost current source (the circuit is equivalent to the current source la in FIG. 6), which is used to improve the DC level of Vi, so that the MOS transistor in the current source Ic can be maintained at The saturation region (Saturation Region) works to avoid the situation of signal distortion (Signal Distortion), thereby improving the echo cancellation performance of the transceiver 500 of the present invention. In practice, the boosted current source (ie, the equivalent current source la) can be a fixed current source or an adjustable current source, that is, the signal provided by the boosted current source la can be a DC with a fixed DC component. The signal or the AC signal may also be a signal whose DC component is adjusted according to the size of the current source Ic. The receiver 500 of the present invention minimizes the phenomenon of echo interference by the action of the low-pass filter 570. In the transceiver 500 of the present invention, the gain adjustment circuit 542 in the analog front-end circuit 540 is implemented using an operational amplifier-resistor-capacitor (OP-RC) circuit architecture, and the input impedance Zi of the gain adjustment circuit 542 is Can be implemented with a 14 200533092 resistor. One end of the input impedance Zι is connected to the node a, and the other end is connected to the echo free point of the transceiver 500. Because of the high loop gain (High Looop Gain) characteristic of this circuit architecture, the node A forms a virtual ground point. It is known from the foregoing analysis of the conditions required for echo cancellation that the magnitude of the input impedance zi does not affect the function of echo cancellation by the low-pass filter 57 and the echo cancellation circuit 530. Therefore, the degree of freedom of the gain adjustment circuit 542 to adjust the gain can be greatly improved. At the same time, because the gain adjustment circuit 542 is implemented by using the circuit structure of yP-RC, it can obtain a very low output impedance. For the voltage δίΐ, Lu is a good drive stage (丨 ver stage), which can be driven smoothly. One stage circuit (eg filter 544). In this way, the transceiver 500 of the present invention does not need to mediate a zero gain buffer between the analog front-end circuit 54 and its pre-stage, which reduces the complexity, cost and power consumption of the circuit, and reduces additional noise or Source of harmonic distortion. As mentioned earlier, in a multi-channel communication environment, signals between channels are prone to high-frequency interference (Cross Talk), and in a full-duplex communication environment, the components of the residual echo input to the analog front-end circuit 540 are also Mostly at high frequencies, the receiver 500 of the present invention uses a filter 544 to filter out residual echoes of high frequency components. Since the filter 544 of the present invention is a filter of the 0P-RC structure, its output impedance is extremely small, and it can smoothly drive the next-stage circuit. If the second-stage circuit is a sampling and holding circuit 56 ^ which is set before the analog-to-digital conversion circuit 550, the equivalent time of the RC network formed by the sampling and holding circuit 560 can be effectively reduced, and the sampling can be improved. The operating frequency of the AND circuit 560. When the circuit is operating continuously, the parasitic capacitance Ce, the channel equivalent resistance rc 卩, and the size of the anti-matching resistance Rm will be affected by factors such as the working environment, operating temperature, location = difference, and so on. / Receiving process may change from time to time. In order to achieve the effect of echo cancellation more accurately, the receiver 500 of the present invention may also be provided with a residual echo detection circuit (not shown), coupled with 15 200533092 to the analog-to-digital conversion circuit 550, for detecting the analog-to-digital conversion circuit 550. Echo Residue. The residual echo detection circuit outputs a control signal to the low-pass filter 570 according to the detected residual echo to adjust the position of the pole (Pole) of the low-pass conversion equation H (s), so that the residual echo can be adjusted. To the minimum, the simplified equivalent circuit diagram is shown in Figure 7. In the description of the foregoing embodiment, the hybrid circuit (Hybird) is used as the current drive mode (Cur rent Mode) as an example. In fact, the architecture and concept of the echo cancellation of the receiver of the present invention can also be applied to the The hybrid circuit (Hybird) is a voltage mode mode receiver, which can also achieve the echo cancellation effect of the receiver of the present invention and the concept that the active components can be driven smoothly without the need for a zero gain buffer. FIG. 8 is a simplified equivalent circuit diagram of a voltage driving mode. Among them, Vo 'is the output of the line driving transmission circuit, Rk is the matching resistance, Vo is the signal to be transmitted through one of the one-line interface outputs, Re is the equivalent load resistance, and Ce is the parasitic capacitance. In the case of considering the parasitic capacitance effect, the equivalent output impedance Zo of the line driving transmission circuit is the parallel connection of the load resistance Re and the parasitic capacitance Ce (Zo = Re // Ce). From the principle of partial pressure, the following equation can be obtained: v〇-^-v〇y ----- v〇 ^ h (s) -v〇} (7)

Zo + Rk Rk + Rt + sRtRkCe Figure 9 shows a simplified equivalent circuit diagram of the second embodiment of the receiver of the present invention. The hybrid circuit (Hybird) of the transceiver 900 includes a line driving transmission circuit 920, which outputs a transmission signal to a channel through an impedance matching resistor Rk; an echo cancellation signal generator 930, which couples the line driving transmission circuit 920, An echo cancellation signal is generated according to the transmission signal; and a cancellation module 942 is coupled to the line driving transmission circuit 920 and the echo cancellation signal generator 930 to remove the echo generated by the transmission signal. 16 200533092 The echo cancellation signal generator 930 generates the echo cancellation signal according to the output Vo ′ of the line driving transmission circuit 920, and transmits the echo cancellation signal to the cancellation module 942. The cancellation module 942 is used to remove the echo generated by the transmission signal. FIG. 10 illustrates an embodiment of the receiver 900 of the present invention. In this embodiment, the echo cancellation signal generator 930 is implemented by a resistor-capacitor network low-pass filter, which includes a resistor Ra and a capacitor Ca, and is used to output the signal Vo ′ from the line-driven transmission circuit 920. An echo cancellation signal Va is generated. The echo cancellation signal Va is input to an operational amplifier 950 of one of the cancellation modules 942 through a resistor R1, and the transmission signal Vo of the transmitter 900 is input to the operational amplifier 950 through a resistor R2. In the cancellation module 942, a resistor Rf has two ends, one end is connected to the input terminal of the operational amplifier 950, and the other end is connected to the output terminal of the operational amplifier 950 to control the amplification ratio of the operational amplifier 950. The operational amplifier 950 performs low-pass filtering and subtraction at the same time. After calculation, it can be obtained: Va R1

Ra + R1 + sCaRaRl ~ Vo}

Va + Vo cover (8) (9) Assuming Vr = 0, combining the above equations (7), (8), and (9), we get: (10) _1 ___- Re_

Ra + R1 + sCaRaRl (Re + Rk + sCeRtRk) R2 Therefore, as long as the following two relations (11) and (12) are satisfied, the echo can be completely offset:

CaRaRl = CeRkR2 (11) 17 + = ^ + (12) 200533092 In the case of a hybrid pppp wave filter 944 with upload and receive status g〇〇, there is no need to set a zero gain = then 0P-944 of the RC architecture It can also smoothly drive the second-stage fetching and 0P-RC filter. It takes the working buffer from A y, for example, a sampling and holding circuit, which is the same as A up to 4 sampling and holding circuit. "A and A, and another zero increase in profit. ^ The above is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the patent application for the present invention should be covered by the present invention patent. [Brief description of the diagram] Brief description of the diagram Figure 1 is a simplified schematic diagram of a transceiver in a channel of a conventional Ethernet device. FIG. 2 is a schematic diagram of some circuits in FIG. 1. Figure 3 is a small signal model of the pre-stage of the analog front-end circuit in Figure 1. Figure 4 is another small signal model of the pre-stage of the analog front-end circuit in Figure 1. FIG. 5 is a simplified schematic diagram of the first embodiment of the receiver of the present invention. Figure 6 is the equivalent circuit diagram of Figure 5. FIG. 7 is a simplified equivalent circuit diagram of another embodiment of FIG. 5. Figure 8 is a simplified equivalent circuit diagram of the one-line drive transmission circuit. FIG. 9 is a simplified schematic diagram of the second embodiment of the receiver of the present invention. Figure 10 is the equivalent circuit diagram of Figure 9. Symbols of the drawings 100, 500 Transceiver 110 Channel 18 200533092 115, 510 Hybrid circuit 120, 520 Digital analog conversion circuit 130, 530 Echo cancellation circuit 140, 540 Analog front-end circuit 150, 550 Analog digital conversion circuit 160, 560 Sample and hold circuit 170, 180 Zero gain buffer 212 Switch 214 Capacitor 512 line interface 514 Twisted pair 542 Gain adjustment circuit 544, 570, 944 Filter 920 line drive transmission circuit 930 Echo cancellation signal generator 942 Elimination module 950 Operation Amplifier 19

Claims (1)

200533092 The scope of patent application: 1. A transceiver of a full-duplex communication system, the transceiver includes: a hybrid circuit (Hybird Circuit), coupled to a channel, used to output through the channel A transmitting signal or receiving a receiving signal, the hybrid circuit includes: an echo cancelling device for removing a component of the transmitting signal from the receiving signal; wherein the hybrid circuit outputs a processed receiving signal; and A gain amplifier is an amplifier-resistance-capacitor automatic gain amplifier (〇P-RC AGC), which is directly coupled to the hybrid circuit to amplify the processed received signal. The gain amplifier is connected to the echo. A first end of one of the elimination devices is a virtual ground (Virtual Ground). 2. The transceiver as described in item 1 of the Shen Qing patent range, wherein the gain amplifier has a low output impedance. 3. The receiver according to item 1 of the patent application range, wherein the gain amplifier has a high loop gain characteristic. 4. The receiver according to item 1 of the scope of the patent application, wherein the gain amplifier comprises: an operational amplifier 'faced to the hybrid circuit;-a resistor having two ends, one end coupled to the input end of the operational amplifier , The other end is coupled to the output end of the operational amplifier; and-a capacitor is coupled to the input end and the output end of the operational amplifier. 5. The receiver according to item 1 of the scope of patent application, further comprising:-a filter, which is an amplifier-a resistor-capacitive filter (〇p_RC filter), which is directly coupled to the gain amplifier, and is used for Filter out the noise or harmonics in the signal output by the gain 20 200533092 amplifier. 6. The transceiver according to item 5 of the patent application, wherein the filter has a low output impedance. 7. The transceiver according to item 5 of the patent application, wherein the filter has a high loop gain characteristic. 8. The transceiver as described in item 5 of the patent application scope, further comprising: an analog digital conversion circuit coupled to the filter for digitizing the filtered signal. 9. The transceiver as described in item 8 of the scope of patent application, further comprising: a clock restorer coupled to the analog digital conversion circuit for generating a sampling clock for the analog digital conversion circuit to operate. 10. The transmitter according to item 1 of the scope of patent application, wherein the echo cancellation device further comprises: a filter for outputting a filtered signal according to the transmission signal; and an echo cancellation circuit coupled to the filter A device for outputting an echo cancellation signal according to the filtered signal; wherein the echo cancellation signal corresponds to the transmission signal. 11. The receiver according to item 10 of the patent application scope, wherein the echo cancellation circuit further comprises: a boost current source for raising the DC level of the echo cancellation circuit. 12. The transmitter as described in item 10 of the scope of patent application, wherein the transmitter further includes a 21 echo echo circuit, which is incorporated in the analog conversion circuit, and is used for the basis of-residual echo (Echo Residue) output-control signal, filter. 13. The receiver described in item 12 of the patent, wherein the money device is a digital wave filter, and the control signal is used to adjust the finite impulse response (FIR) or infinite impulse response of the digital filter. ⑴R). H. The receiver described in item i of the patent scope, wherein the echo cancellation device includes an echo cancellation signal generator for generating an echo cancellation signal according to the transmission signal; and "a cancellation module, The echo cancellation signal generator is coupled to remove the echo generated by the transmission signal. 15 .: The transceiver described in item 14 of the patent scope of claim 5, wherein the cancellation module includes: an operational amplifier, coupled An echo cancellation signal generator; and a resistor having two ends, one end coupled to the input end of the operational amplifier and the other end connected to the output end of the operational amplifier. 16.-Transmission of a full-duplex communication system The device includes a hybrid circuit (Hybird) coupled to a channel for outputting a transmission signal or receiving a reception signal through the channel. The hybrid circuit includes a cancelling device for moving In addition to the components of the transmitted signal in the received signal; wherein the hybrid circuit outputs a processed received signal; and the filter is an amplifier-resistor-capacitive type The wave filter (〇P-Rc filter) is directly coupled to a gain amplifier to filter out noise or harmonics in the signal output by the gain amplifier. The filter is connected to the echo. 22 200533092 One end is a virtual ground terminal. 17. The transmitter according to item 16 of the patent application, wherein the filter has a low output impedance. 18. The receiver according to item 16 of the patent application, wherein the The filter has a high loop gain characteristic.