KR100842775B1 - Two-stage equalizer, method of two-stage equalization, receiver, and communication system for high speed communication - Google Patents

Abstract

A two-stage equalizer, a two-stage equalization method, a receiver, and a high speed communication system are provided to decrease a power consumption of the communication system by effectively compensating for a high speed data signal. A two-stage equalizer includes an emphasis circuit(4100) and a de-emphasis circuit(4200). The emphasis circuit divides an input signal into N pieces. A divided signal passes through cascaded transconductance filters, such that a high frequency component is extracted. The signal from the transconductance filters passes through cascaded flat band amplifiers, such that delay times are equalized. The signal from the flat band amplifiers is amplified by a variable gain amplifier, such that a signal gain is adjusted. N amplified signals are added in a linear mixer.

Description

TWO-STAGE EQUALIZER, METHOD OF TWO-STAGE EQUALIZATION, RECEIVER, AND COMMUNICATION SYSTEM FOR HIGH SPEED COMMUNICATION}

1 is a block diagram showing a conventional communication system.

2 is a block diagram illustrating a communication system according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an amplifier circuit included in the two-stage equalizer of FIG. 2.

4 is a block diagram illustrating a de-emphasis circuit included in the two-stage equalizer of FIG. 2.

FIG. 5 is a circuit diagram illustrating a transconductance filter included in the amplifier circuit of FIG. 3.

FIG. 6 is a circuit diagram illustrating a flat band amplifier included in the amplifier circuit of FIG. 3.

FIG. 7 is a circuit diagram illustrating a variable gain amplifier included in the amplifier circuit of FIG. 3.

FIG. 8 is a circuit diagram illustrating a linear coupler included in the ampere circuit of FIG. 3.

FIG. 9 is a circuit diagram illustrating a main tap included in the de-emphasis circuit of FIG. 4.

FIG. 10 is a circuit diagram illustrating a delay cell included in the de-emphasis circuit of FIG. 4.

11 is a block diagram illustrating a receiver according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100, 1000: transmitter 200, 2000: channel

300, 3000: receiver 4000: two-stage equalizer

310, 4100: Amphasis circuit 110, 4200: De-emphasis circuit

4111,4112,4113: Transconductance Filter

4121,4122,4123: Flat Band Amplifier

4131,4132,4133: Variable Gain Amplifier

4210: main tab

4240: delay line

4241,4242,4243,4244: delay cells

The present invention relates to an equalizer, and more particularly, to a two-stage equalizer for high-speed signal transmission, a receiver and a communication system including the same, and a two-stage equalization method.

Data transfer rates are getting higher. This trend is widespread, from in-chip data communications to near-field and remote data communications. The frequency dependent loss resistance of the channel having the width W is expressed by Equation 1.

Where σ represents the conductivity of the channel (5.8 * 10 ■ ohm / m for copper). The resistance value is expressed as a function of frequency, and it can be seen that as the frequency increases, the value increases. As such, the higher the frequency component, the higher the frequency-dependent loss, which causes higher loss. The higher data rate includes more high-frequency signals, so the higher the data rate, the higher the data rate. Becomes even worse.

In order to solve this problem, an equalization method is used, in which the frequency dependent loss characteristic is reversed to flatten the frequency characteristic of the channel. A signal that suffers frequency dependent loss suffers more at higher frequency components, and at higher frequencies, the signal becomes smaller. Therefore, attenuating low frequency signals and amplifying high frequency signals have the same magnitude regardless of frequency. A state in which all frequency components of a signal have an output of the same magnitude is ideally equalized, and a circuit for this is called an equalizer.

1 is a block diagram showing a conventional communication system.

Referring to FIG. 1, a communication system includes a transmitter 100, a channel 200, and a receiver 300. The transmitter 100 of a conventional communication system includes a de-emphasis circuit 110, and the receiver 300 includes a de-emphasis circuit 310.

When using the method of amplifying a signal in the transmitter 100, noise may be amplified together or cross talk or electromagnetic interference may occur. Therefore, the transmitter 100 de-emphasizes attenuation of low frequencies. The loss is compensated by a de-emphasis method, and the receiver 300 compensates for the loss by an emphasis method of amplifying a high frequency wave. In the case where a high loss occurs in the channel 200, both methods may be used.

However, when the channel loss is large due to the high transmission rate, the conventional equalizer has some problems. The gain is insufficient to compensate for this loss with a conventional equalizer structure in the receiver, and increasing the gain dramatically increases chip area or power consumption. When the transmitter compensates for a large loss, the signal attenuation increases, resulting in a smaller output signal. If a largely attenuated signal passes through the channel, a problem arises in that the size of the transmitted signal becomes small enough that the receiver cannot detect it.

Therefore, an equalizer capable of efficiently compensating for loss in a communication environment having a high channel loss due to a high transmission rate is required.

In order to solve the above problems, an object of the present invention is to provide a two-stage equalizer that occupies a small chip area and consumes little power.

Another object of the present invention is to provide a two-stage equalization method that occupies a small chip area and consumes little power.

Another object of the present invention is to provide a receiver including the two-stage equalizer.

Another object of the present invention is to provide a communication system including the two-stage equalizer.

To achieve the above object, a two-stage equalizer according to an embodiment of the present invention includes an amplifier circuit and a de-emphasis circuit.

The amplifier circuit receives an input signal and outputs a first equalized signal obtained by amplifying a high frequency component of the input signal. The de-emphasis circuit receives the first equalized signal and outputs a second equalized signal obtained by attenuating low frequency components of the first equalized signal.

The amplifier circuit may be configured to branch the input signal into N (N is a natural number of 2 or more), and each of the branched signals passes through transconductance filters of different orders.

In one embodiment, the amplification circuit branches the input signal into N (N is a natural number of 2 or more), and the I-th branched signal (I is a natural number from 1 to N) for extracting high frequency components. Pass through cascaded I-1 transconductance filters, pass signal through transconductance filters, pass through cascaded N-I + 1 flat band amplifiers to equalize delay time, then pass through flat band amplifiers One signal is amplified by a variable gain amplifier that adjusts the gain of the signal in accordance with a weighted control signal, and the amplified N signals can be configured to be summed by a linear combiner.

The transconductance filters may be implemented as differential amplifiers each having a degeneration capacitor. The flat band amplifiers may be implemented as differential amplifiers each having a degeneration resistor. Each of the variable gain amplifiers may be implemented as a differential amplifier having a variable current source connected between a source and a ground in accordance with a weighted control signal. The linear coupler may be implemented with N differential amplifiers sharing an output resistance.

The de-emphasis circuit may be implemented with an analog finite-duration impulse response filter.

The de-emphasis circuit may include: a main tap configured to receive the first equalized signal and output the second equalized signal without changing the waveform; and receive the first equalized signal and sequentially receive the first equalized signal. A delay line for outputting M delay signals through delay cells of a delay M order (M is one or more natural numbers), and connected to each of the delay cells, respectively, by the respective delay signals. M side taps that are driven and serve as a sub current driver to attenuate the second equalized signal according to the weighted control signal.

The de-emphasis circuit may further include a buffer connected between each side tap connected to the delay cells to compensate for a temporal error due to a long delay time.

The main tap may be implemented as a differential amplifier with a current source connected between the source and ground, wherein the delay cells are in parallel with a diode-connected PMOS device such that the delay time is controlled by voltage, respectively. It can be implemented as an RC delay circuit consisting of connected equally sized biased PMOS devices, and the side taps are implemented as differential amplifiers, each of which is connected to a variable current source whose current magnitude is controlled according to a weighted control signal between the source and ground. Can be.

The delay line may further include dummy delay cells between the delay cells to maintain a driving time interval between the main tab and the side taps.

The two-stage equalization method according to the embodiment of the present invention includes an amperiss step and a de-emphasis step.

The emphasis step receives an input signal from a channel having a high transmission rate and outputs a first equalized signal that amplifies a high frequency component of the input signal. The de-emphasis step receives the first equalized signal and outputs a second equalized signal obtained by attenuating low frequency components of the first equalized signal.

The step of amplifying may include branching an input signal for each frequency band, amplifying the branched signal for each frequency band according to a weighted control signal, and linearly combining each amplified signal.

The de-emphasis step may include receiving the first equalized signal and outputting the first equalized signal as the second equalized signal without changing the waveform by a main tap, and receiving the first equalized signal to obtain a M order (M is a natural number of 1 or more). A delay step of sequentially delaying by delay lines having delay cells to output M delay signals, and attenuating the second equalized signal according to a weighted control signal by side taps driven by each of the M delay signals It may include a step.

A receiver according to an embodiment of the present invention includes an input terminal, a two-stage equalizer, and an on die termination circuit.

The input terminal receives an input signal from a channel having a high transmission rate. The two-stage equalizer is connected to the input terminal and outputs a first equalized signal amplifying a high frequency component of the input signal and an amplifier circuit for receiving the first equalized signal and attenuating the low frequency component of the first equalized signal. It has a de-emphasis circuit which outputs a two equalization signal. The on die termination circuit is coupled to the output of the two-stage equalizer for impedance matching to minimize power consumption.

The ampere circuit may branch the input signal into N (N is a natural number of two or more), and each branched signal may be configured to pass a transconductance filter of a different order, wherein the de-emphasis circuit is analogue. It may be implemented as an analog finite-duration impulse response filter.

A communication system according to an embodiment of the present invention includes a transmitter, a channel, and a receiver.

The transmitter transmits data at high transmission rates. The channel is a transmission path of the data. The receiver is connected to the channel and outputs a first equalized signal that amplifies a high frequency component of an input signal transmitted on the channel and an attenuation circuit and receives the first equalized signal to attenuate the low frequency component of the first equalized signal. And a two-stage equalizer having a de-emphasis circuit for outputting the second equalized signal.

The ampere circuit may branch the input signal into N (N is a natural number of two or more), and each branched signal may be configured to pass a transconductance filter of a different order, wherein the de-emphasis circuit is analogue. It may be implemented as an analog finite-duration impulse response filter.

Therefore, the two-stage equalizer uses a small area and can efficiently compensate for the loss in the channel when transmitting a high speed data signal with low power consumption.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same components in the drawings, and duplicate descriptions of the components are omitted.

2 is a block diagram illustrating a communication system according to an embodiment of the present invention.

2, a communication system includes a transmitter 1000, a channel 2000, and a receiver 3000. The receiver 3000 includes a two-stage equalizer 4000, and the two-stage equalizer 4000 includes an amplifier circuit 4100 and a de-emphasis circuit 4200.

The transmitter 1000 transmits data through the channel 2000 at a high transmission rate. The channel 2000 is a transmission path for transmitting the data from the transmitter to the receiver. In this case, the data loss is large because the data transmission speed is high, and more loss is caused in the high frequency band due to the frequency dependent loss. The receiver 3000 receives a signal transmitted through the channel 2000 and includes a two-stage equalizer 4000 to compensate for the loss of the input signal. An emphasis circuit 4100 included in the two-stage equalizer 4000 amplifies the high frequency component of the input signal, and the de-emphasis circuit 4200 attenuates the low frequency component of the input signal. This enables communication of equalized signals having the same magnitude over the entire band of frequencies. In this case, when the two-stage equalizer is installed in the receiver, the equalizer can be utilized even if the design range is limited to the receiver, and it is easy to design an equalizer suitable for the receiver since the loss is compensated for after the loss in the channel.

Since the two-stage equalizer 4000 receives a low level signal from which a loss occurs in the channel 2000, the second equalizer 4000 amplifies the input signal and then compensates the input signal through attenuation of the input signal. An emphasis circuit 4100 amplifies the high frequency component of the input signal, and the de-emphasis circuit 4200 attenuates the low frequency component of the input signal. At this time, the emphasis circuit 4100 and the de-emphasis circuit 4200 share one output driver.

Unlike the conventional equalizer, the two-stage equalizer 4000 occupies less chip area and consumes less power than the conventional equalizer, because the emphasis circuit 4100 and the de-emphasis circuit 4200 share one output driver. At the same time, high losses can be effectively compensated. In addition, since the signal is attenuated in the de-emphasis circuit 4200, cross talk or electromagnetic interference may be reduced.

Hereinafter, with reference to FIG. 3 and FIG. 4, the impulse circuit 4100 and the de-emphasis circuit 4200 will be described.

FIG. 3 is a block diagram illustrating an amplifier circuit included in the two-stage equalizer of FIG. 2.

Referring to FIG. 3, the ampere circuit 4100 includes a transconductance filter 4111, 4112, 4113, flat band amplifiers 4121, 4122, 4123, variable gain amplifiers 4131, 4132, 4133, and a linear combiner 4140. ).

The emphasis circuit 4100 receives the input signal IS with data loss from the channel. The input signal IS maintains the same waveform and branches into N signals. The number of branched signals may vary depending on the embodiment. The branched signal passes through transconductance filters of different orders. Since the transconductance filter serves as a kind of high pass filter, each signal passing through the transconductance filter becomes a signal having a different size for each frequency band. On the other hand, each signal should have the same delay time, even if the respective signals are combined, only the size of each frequency band is different, it is possible to sum the signals without distortion. Therefore, there is a need for a configuration in which the delay time of each signal is the same. Since the flat band amplifier amplifies the same in all frequency bands, the signal passing through the flat band amplifier does not vary in size for each frequency band. However, since the flat band amplifier delays the signal like the transconductance filter, the flat band amplifier is mainly used to have the same delay time as the transconductance filter. Therefore, it is preferable that the flat band amplifier have a transistor of the same size as the transistor of the transconductance filter. In addition, since the delay time of each signal is equal when the sum of the number of transconductance filters and the flat band amplifiers that each signal passes through is the same, the number of transconductance filters that pass through each signal is different. The sum of the number of and the flat band amplifiers is preferably the same. In this configuration, each signal passing through the transconductance filters and the flat band amplifiers has different frequency bands but the same delay time. The signals having different magnitudes for each frequency band are amplified by the variable gain amplifiers, respectively. Since the input signal IS of the ampere circuit 4100 has a loss in the high frequency band greater than that in the low frequency band, the ampere circuit 4100 amplifies the signal past a large number of transconductance filters more than the signal that is not. . Each of the amplified signals is summed by a linear combiner, thereby obtaining a first equalized signal EQ1 obtained by amplifying high frequencies.

Referring again to FIG. 3, the emphasis circuit 4100 divides the input signal IS into three. The branched signal passes through two, one, and zero transconductance filters, respectively. The signal S12 passing through the two transconductance filters 4111 and 4112 mainly includes a high frequency signal among the input signals. The signal S21 passed through one transconductance filter 4113 mainly includes signals of high frequency and middle band. The signal that has not passed through the transconductance filter has the same waveform as the input signal IS. The signal S21 passing through one transconductance filter 4113 passes through one flat band amplifier 4121 so that the delay time of each signal is equal, and the signal not passing through the transconductance filter passes through two flat signals. Passes through band amplifiers 4122 and 4123. The signals S12, S22, and S32 passing through the transconductance filters and the flat band amplifiers have different magnitudes for each frequency band and have the same delay time. The signals S12, S22, and S32 having different magnitudes for each frequency band pass through the variable gain amplifiers 4131, 4132, and 4133, whose gains are varied by the weighted control signal, respectively. According to the purpose of the ampere circuit for amplifying the high frequency band of the input signal IS, the signal S12 which has passed through two transconductance filters is amplified most, and the signal S32 which has not passed through the transconductance filter is most amplified. Amplify less. The signals S13, S23, S33 amplified by the variable gain amplifier are summed by the linear combiner 4140. The combined signal is a signal in which the high frequency band of the input signal is amplified as the first equalization signal EQ1 and provided to the input of the de-emphasis circuit 4200.

4 is a block diagram illustrating a de-emphasis circuit included in the two-stage equalizer of FIG. 2.

Referring to FIG. 4, the de-emphasis circuit 4200 includes a main tap 4210, side taps 4221, 4222, 4223, 4224, buffers 4231, 4232, 4233, and delay cells 4241, 4242, 4243, 4244. Delay line 4240 having

The de-emphasis circuit 4200 receives a first equalized signal EQ1 of which the high frequency band is amplified from the emphasis circuit 4100. The first equalized signal EQ1 is input to the main tap 4210 and is output as the second equalized signal EQ2 without changing the waveform. The main tap 4210 acts as an output driver, and the power consumption can be minimized because the emphasis circuit 4100 and the de-emphasis circuit 4200 of FIG. 3 use one output driver. The first equalizing signal EQ1 is an input of the main tap 4210 and an input of a delay line 4240. The delay line 4240 has M delay cells, and the number of delay cells may vary according to embodiments. Each delay cell has the same configuration and sequentially delays the first equalized signal at equal intervals and outputs a delayed signal, respectively. The delay signal is input to the side taps to drive the side taps. The side tap acts as a sub current driver and works the opposite of the main tap as an output driver. For example, when there is a step input, the main tap maintains the waveform of the input and outputs the input signal. Therefore, when the input signal changes from 'low' to 'high', the output signal of the main tap also changes from 'low' to 'high'. In addition, the step input is sequentially delayed by the delay cells, and the side taps are sequentially driven by the output values of the respective delay cells having the 'high' value sequentially. In this case, since the side tap operates in the opposite direction of the main tap, the output of the main tap is gradually lowered. Accordingly, the output of the main tap is sequentially reduced by the output of the side taps which are sequentially driven, and the interval is increased from the moment when it is changed to 'high' until all the side taps are driven. That is, it attenuates the signal swing when the output is in a transient state, which is attenuated by low frequencies when interpreted in the frequency domain. The de-emphasis circuit outputs the second equalized signal EQ2 in which the low frequency component of the first equalized signal is attenuated by the side taps sequentially driven.

Referring back to FIG. 4, the de-emphasis circuit 4200 according to an embodiment includes a fifth finite section having a main tap 4210 and five taps of four side taps 4221, 4222, 4223, and 4224. Implemented as a finite-duration impulse response filter. The order of the finite interval impulse response filter may vary depending on the embodiment. The conventional equalizer is composed of an analog to digital converter (ADC) and a digital finite-range impulse response filter. However, high-speed ADCs are required in systems that transmit high data rates, and high-speed ADCs are difficult to implement in CMOS technology. Therefore, the finite-range impulse response filter according to an embodiment of the present invention is implemented in analog for fast operation and simple implementation. Therefore, the finite-period impulse response filter according to an embodiment does not require a clock and a data recovery circuit (CDR circuit) or a phase locked loop (PLL). The first equalized signal EQ1, which is an input signal of the de-emphasis circuit 4200, is input to the main tap 4210 and the second equalized signal EQ2 without changing the waveform by the main tap 4210 serving as an output driver. Is output. The first equalized signal EQ1 is input to the first delay cell 4241 of the delay line 4240 and delayed for a predetermined time, and then output to the first side tap 4221 and the second delay cell 4242. The first side tap 4221 is driven by the signal delayed by the first delay cell 4241. The output of the side tab 4221 attenuates the output swing of the main tab. Also, the second delay cell 4242 also outputs a delay signal after delaying a predetermined time signal, and the output delay signal drives the second side tap 4422. Similarly, after a certain time delay, the third side tab 4223 and the fourth side tab 4224 are driven. The sequentially driven side taps act as sub-output drivers and attenuate low frequency components of the second equalized signal by sequentially attenuating the swing of the signal when the second equalized signal is in a transient state. In addition, the de-emphasis circuit is connected between the delay cells 4241, 4242, 4243, and 4244 to the respective side taps 4221, 4222, 4223, and 4224 to compensate for the temporal error due to the long delay time 4231. , 4232, 4233, and 4234 may be further included.

5, 6, 7, and 8, the components of the impulse circuit 4100 of FIG. 3 will be described.

FIG. 5 is a circuit diagram illustrating a transconductance filter included in the amplifier circuit of FIG. 3.

Referring to FIG. 5, the transconductance filter 4111 according to an embodiment may be implemented as a differential amplifier having a degeneration capacitor. Other transconductance filters 4112 and 4113 of FIG. 3 also have the same configuration. However, this is an embodiment, and the transconductance filter may be implemented as a common source amplifier having a subtractive capacitor implemented as one transistor rather than a differential amplifier. In a common source amplifier having a subtractive capacitor, since the capacitor has a high impedance at high frequencies and the capacitor has a low impedance at low frequencies, the high frequency component of the input signal passes and the low frequency component is removed. The transconductance of the common source amplifier with the derating capacitor can be obtained from Equation 2.

은 트랜지스터의 트랜스컨덕턴스이고, C는 감생 캐패시터의 캐패시턴스이며, s는 복소 주파수 변수이다. 이 때,

이 sC보다 충분히 크면, 수학식 3과 같은 이득을 얻을 수 있다.here

Is the transconductance of the transistor, C is the capacitance of the damping capacitor, and s is the complex frequency variable. At this time,

If it is larger than this sC, the gain as in Equation 3 can be obtained.

는 전원 전압과 드레인 사이의 저항이다. 수학식 3에 따라 감생 캐패시터를 가지는 공통 소스 증폭기의 이득은 주파수에 선형적으로 의존한다. 그러므로 감생 캐패시터를 가지는 공통 소스 증폭기는 일차 미분기로 알려져 있고, 고주파 통과 필터의 역할 때문에 트랜스컨덕턴스 필터로 불리기도 한다.here

Is the resistance between the supply voltage and the drain. According to Equation 3, the gain of a common source amplifier having a subtractive capacitor is linearly dependent on frequency. Therefore, a common source amplifier with a derating capacitor is known as a first order differentiator and is sometimes called a transconductance filter because of its role as a high pass filter.

In addition, the transconductance filter may be implemented as a MOS differential amplifier as shown in FIG. When implemented as a MOS differential amplifier, it can be implemented as a capacitor (Cs / 2) having half the capacitance than when implemented as a single transistor, which has the advantage of implementing a transconductance filter in a smaller area.

FIG. 6 is a circuit diagram illustrating a flat band amplifier included in the amplifier circuit of FIG. 3.

Referring to FIG. 6, the flat band amplifier 4121 according to an embodiment is implemented as a MOS differential amplifier having a degeneration resistor. The other flat band amplifiers 4122 and 4123 of FIG. 3 also have the same configuration. However, this is one embodiment, and the flat band amplifier may be implemented as a common source amplifier having a damping resistor implemented by one transistor instead of the MOS differential amplifier. The transconductance of the common source amplifier with the damping resistance can be obtained from Equation 4.

는 감생 저항이다. 이 때,

가 충분히 큰 경우, 이득인

는

가 되어 입력에 무관하게 되고, 증폭기는 선형화 된다. 다만, 선형성이 향상되면 이득이 줄어들게 되고, 이득을 높이면 선형성이 줄어들게 된다. 따라서 플랫 밴드 증폭기는 주파수에 무관하게 동일한 신호를 출력하는 데에 사용되고, 선형성을 유지하기 위해 신호의 이득은 뒷단의 가변 이득 증폭기(variable gain amplifier)를 통해 얻는다. here

Is a reduction resistance. At this time,

Is large enough,

Is

Becomes independent of the input, and the amplifier is linearized. However, if the linearity is improved, the gain is reduced, and if the gain is increased, the linearity is reduced. Therefore, a flat band amplifier is used to output the same signal regardless of frequency, and in order to maintain linearity, the gain of the signal is obtained through a variable gain amplifier at the rear stage.

FIG. 7 is a circuit diagram illustrating a variable gain amplifier included in the amplifier circuit of FIG. 3.

Referring to FIG. 7, the variable gain amplifier 4131 according to an embodiment is implemented as a MOS differential amplifier in which a variable current source having a magnitude of current controlled according to a weighted control signal is connected between a source and a ground. The other variable gain amplifiers 4132 and 4133 of FIG. 3 also have the same configuration. However, this is one embodiment, and the variable gain amplifier may be implemented as one transistor instead of the MOS differential amplifier. In addition, the variable gain amplifier of FIG. 7 has a configuration in which the gain is adjusted by controlling the magnitude of the current by three control signals S1, S2, and S4. For example, when all three control signals S1, S2, and S4 are 'low', all of the gate voltages Vb1, Vb2, and Vb4 of the transistors MN73, MN74, and MN75 serving as current sources are all. The bias voltage Vbias is provided so that the gate voltages Vb1, Vb2, and Vb4 become 'high', and the transistors MN73, MN74, and MN75 are all turned on to obtain maximum gain. At this time, if the first transistor MN73 has twice the size of the second transistor MN74 and the second transistor MN74 has twice the size of the third transistor MN75, eight steps with relative sizes ranging from 0 to 7 are obtained. Gain control. Depending on the purpose of the ampiculation circuit, a signal containing a lot of high frequency components may have a large gain, and a signal containing a lot of low frequency components may have a small gain. Will be. Summing up each signal is by linear combiner 4140 of FIG.

FIG. 8 is a circuit diagram illustrating a linear coupler included in the ampere circuit of FIG. 3.

Referring to FIG. 8, the linear coupler 4140 according to an embodiment is implemented with three differential amplifiers sharing output resistors R1 and R2. The number of common source amplifiers depends on the number of branched signals. The signals S13, S23, S33 amplified by the variable gain amplifiers 4131, 4132, 4133 of Fig. 3 become inputs to the differential amplifiers included in the linear combiner 4140, respectively, each differential amplifier being all from a current source. Since a bias current of the same magnitude is supplied and the same output resistors R1 and R2 are shared, an output EQ1 in which the respective signals S13, S23, and S33 are linearly coupled is provided. The output of the linear combiner 4140 becomes the output signal EQ1 of the emulation circuit 4100 of FIG. 3, and the output signal is the first equalization signal EQ1 of which the input of the de-emphasis circuit 4200 of FIG. do.

Hereinafter, the components of the de-emphasis circuit 4200 of FIG. 4 will be described with reference to FIGS. 9 and 10.

FIG. 9 is a circuit diagram illustrating a main tap included in the de-emphasis circuit of FIG. 4.

Referring to FIG. 9, the main tap 4210 according to an embodiment is implemented as one differential amplifier. At this time, since the output of the main tap 4210 should be the same as the input, the main tap 4210 may have the same configuration as the linear coupler 4140 of FIG. 3. Therefore, when the linear coupler 4140 of FIG. 3 is implemented with three differential amplifiers, the main tap 4210 may include three times as large transistors as each transistor of one linear amplifier of the linear coupler 4140 of FIG. 3. In addition, it is preferable to receive from the current source Is9 three times the bias current of the bias current supplied by the current source Iss8 of one of the linear amplifiers 4140 of FIG. 8. In such a configuration, the main tap 4210 may output the same second equalized signal EQ2 as the first equalized signal EQ1 that is an input signal. On the other hand, the first equalized signal EQ1 is an input of the main tap 4210 and a delay line.

FIG. 10 is a circuit diagram illustrating a delay cell included in the de-emphasis circuit of FIG. 4.

Referring to FIG. 10, the delay cell 4241 is implemented with an RC delay circuit. The other delay cells 4142, 4143, and 4244 of FIG. 4 also have the same configuration. Delay line 4240 of FIG. 4 is composed of delay cells of series M connected in series, where the number of delay cells may vary according to embodiments. Delay line 4240 according to one embodiment does not require an internal clock or ADC since each of the delay cells 4221, 4142, 4143, 4244 is implemented in an RC delay circuit and implemented in analog. The variable resistor R and the capacitor C according to the exemplary embodiment of FIG. 10 may be the output resistance of the delay cell and the gate of the next cell, respectively. Since the capacitance of the gate is difficult to control, it is preferable to adjust the output resistance R of the delay cell to adjust the delay time. The variable resistor may also consist of a diode-connected PMOS device and a biased PMOS device of the same size connected in parallel thereto. This variable resistor is also called a symmetric load because it has a symmetrical current versus voltage characteristic from the center of the voltage swing. In this case, the resistance may be changed by adjusting the gate voltage of the PMOS device connected in parallel to the diode-connected PMOS device, and the delay time of the delay cell may be adjusted by changing the resistance. These delay cells may be connected in series to form a voltage controlled delay line whose delay time is controlled by voltage.

Referring back to FIG. 4, the delay cells 4241, 4242, 4243, and 4244 of the delay line 4240 have the same configuration and have the same delay time. However, even though the delay time between the side taps 4221, 4222, 4223, and 4224 driven by the delay cells 4241, 4242, 4243, and 4244 is the same, between the main tap 4210 and the first side tap 4221. Since the delay time may be different from the delay time between the side taps, dummy delay cells may be added between the delay cells 4241, 4242, 4243, and 4244.

In addition, when each of the delay cells 4241, 4242, 4243, and 4244 is implemented as an RC current circuit, a rise time of an output may increase as a delay increases. As a result, the side taps 4221, 4222, 4223, and 4224 may malfunction in the long rise time. Accordingly, buffers 4231, 4232, 4233, and 4234 may be added between the delay cells 4241, 4242, 4243, and 4244 and the side taps 4221, 4222, 4223, and 4224 to reduce the malfunction. The buffer should have a rise time short enough for the side taps to operate normally. The signal delayed by the delay cells is input to the side taps to drive the side taps.

According to an embodiment, the side taps 4221, 4222, 4223, and 4224 of FIG. 4 may be implemented as differential amplifiers having a variable current source having a magnitude of current controlled according to a weighted control signal between a source and a ground, respectively. . In addition, since the side taps output a signal opposite to the main tap 4210 of FIG. 4 to attenuate the swing of the signal, the sum of the size of the side taps must be smaller than the size of the main tap. The ratio of the size of the main tab to the size of the side tab may be determined as in Equation 5.

는 메인 탭의 출력의 최대 스윙 범위(full swing range)이고,

는 최악의 스윙 범위(worst swing range)이며, n은 사이드 탭의 개수를 나타낸다. 이 식에 따라 사이드 탭의 크기, 즉 감쇄되는 출력의 정도는 메인 탭의 출력의 크기를 넘어서지 않게 된다.here

Is the full swing range of the output of the main tap,

Is the worst swing range, and n is the number of side taps. According to this equation, the size of the side tap, i.e. the amount of attenuated output, does not exceed the size of the output of the main tap.

11 is a block diagram illustrating a receiver according to an embodiment of the present invention.

Referring to FIG. 11, the receiver 3000 includes an input terminal 4400, a two-stage equalizer 4000, and an on die termination circuit 4300. The two-stage equalizer 4000 includes an amplifier circuit 4100 that amplifies the high frequency components of the signal and a deemphasis circuit 4200 that attenuates the low frequency components of the signal.

The receiver 3000 according to an embodiment of the present invention receives a lost signal through the channel 2000 through the input terminal 4400, compensates for the loss through the two-stage equalizer 4000, and on die Impedance matching may be performed through the termination circuit 4300 to minimize power consumption. The on die termination circuit may be directly connected to the input terminal 4400, or may be connected to an output terminal of the two-stage equalizer 4000 as an output resistance of the main tap 4210 of the de-emphasis circuit 4200.

As described above, the two-stage equalizer, the two-stage equalization method, the receiver, and the communication system according to the embodiments of the present invention can reduce the area of the equalizer and reduce the loss in the channel when transmitting a high speed data signal. Efficiently compensate for low power consumption.

In addition, in the two-stage equalizer, the two-stage equalization method, the receiver, and the communication system according to the embodiments of the present invention, the de-emphasis circuit may be implemented in analog to have a high operating speed.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (19)

delete delete An amplifier circuit for receiving an input signal and outputting a first equalized signal obtained by amplifying a high frequency component of the input signal; And And a de-emphasis circuit for receiving the first equalized signal and outputting a second equalized signal obtained by attenuating low frequency components of the first equalized signal. Split the input signal into N (N is a natural number of 2 or more), The I-th branched signal (I is a natural number from 1 to N) passes through cascaded I-1 transconductance filters for extracting high frequency components, The signal passing through the transconductance filters passes through cascaded N-I + 1 flat band amplifiers to equalize the delay time, The signal passing through the flat band amplifiers is amplified by a variable gain amplifier that adjusts the gain of the signal according to the weighted control signal, Wherein the amplified N signals are configured to be summed by a linear combiner. The method of claim 3, wherein the transconductance filters, A two-stage equalizer characterized by being implemented as differential amplifiers each having a degeneration capacitor. The method of claim 3, wherein the flat band amplifiers, A two-stage equalizer characterized by being implemented as differential amplifiers each having a degeneration resistor. The method of claim 3, wherein the variable gain amplifiers, A two-stage equalizer, each of which is implemented by a differential amplifier having a variable current source connected between a source and ground, the magnitude of the current being controlled according to a weighted control signal. The method of claim 3, wherein the linear coupler, A two-stage equalizer characterized by being implemented with N differential amplifiers sharing an output resistance. The method of claim 3, wherein the de-emphasis circuit, A two-stage equalizer characterized in that it is implemented by an analog finite-duration impulse response filter. An amplifier circuit for receiving an input signal and outputting a first equalized signal obtained by amplifying a high frequency component of the input signal; And And a de-emphasis circuit for receiving the first equalized signal and outputting a second equalized signal obtained by attenuating low frequency components of the first equalized signal. A main tap for receiving the first equalized signal and outputting the second equalized signal without changing a waveform; A delay line configured to receive the first equalized signal and output M delay signals through delay cells of an M order (M is a natural number of 1 or more) for sequentially delaying the first equalized signal; And And M side taps connected to each of the delay cells and driven by the respective delay signals and serve as a sub current driver to attenuate a second equalization signal according to a weighted control signal. Featured two-stage equalizer. The method of claim 9, wherein the de-emphasis circuit, And a buffer coupled between each side tap connected to the delay cells to compensate for a temporal error due to a long delay time. The method of claim 9, The main tap is implemented as a differential amplifier having a current source connected between the source and the ground, Each of the delay cells is implemented as a delay circuit composed of diode-connected PMOS transistors having the same size and biased PMOS transistors connected in parallel thereto so that a delay time is controlled by a voltage. And the side taps are implemented as differential amplifiers each having a variable current source connected between a source and a ground, the magnitude of the current being controlled according to a weighted control signal. The method of claim 9, wherein the delay line, Further comprising dummy delay cells between the delay cells to maintain a constant driving time interval between the main tab and the side taps. Receiving an input signal from a channel and outputting a first equalized signal obtained by amplifying a high frequency component of the input signal; And And a de-emphasis step of receiving the first equalized signal and outputting a second equalized signal obtained by attenuating low frequency components of the first equalized signal. Receiving the first equalized signal and outputting the first equalized signal as the second equalized signal without changing the waveform by a main tap; A delay step of receiving the first equalized signal and sequentially delaying the delay signal by delay lines having delay cells of order M (M is a natural number of 1 or more) to output M delay signals; And And attenuating the second equalized signal according to a weighted control signal by a side tap driven by each of the M delay signals. The method of claim 13, wherein the emphasis step, Dividing the input signal by frequency band; Amplifying the branched signal according to the weighted control signal for each frequency band; And And linearly combining each amplified signal. delete An input terminal receiving an input signal from a channel; An amplifier circuit connected to the input terminal to output a first equalized signal that amplifies a high frequency component of the input signal, and a second equalized signal that receives the first equalized signal and attenuates a low frequency component of the first equalized signal; A two-stage equalizer having a de-emphasis circuit to output; And The receiver circuit comprising: an on-die termination circuit connected to an output of the two-stage equalizer and performing impedance matching for minimizing power consumption. Split the input signal into N (N is a natural number of 2 or more), The I-th branched signal (I is a natural number from 1 to N) passes through cascaded I-1 transconductance filters for extracting high frequency components, The signal passing through the transconductance filters passes through cascaded N-I + 1 flat band amplifiers to equalize the delay time, The signal passing through the flat band amplifiers is amplified by a variable gain amplifier that adjusts the gain of the signal according to the weighted control signal, The amplified N signals are configured to be summed by a linear combiner. The method of claim 16, The de-emphasis circuit is a receiver, characterized in that implemented by an analog finite-duration impulse response filter. A transmitter for transmitting data; A channel which is a transmission path of the data; And An amplifier circuit connected to the channel to output a first equalized signal amplifying a high frequency component of an input signal transmitted from the channel and a second received attenuated low frequency component of the first equalized signal by receiving the first equalized signal A communication system comprising: a receiver including a two-stage equalizer having a de-emphasis circuit for outputting an equalization signal, wherein the ampiculation circuit comprises: Split the input signal into N (N is a natural number of 2 or more), The I-th branched signal (I is a natural number from 1 to N) passes through cascaded I-1 transconductance filters for extracting high frequency components, The signal passing through the transconductance filters passes through cascaded N-I + 1 flat band amplifiers to equalize the delay time, The signal passing through the flat band amplifiers is amplified by a variable gain amplifier that adjusts the gain of the signal according to the weighted control signal, The amplified N signals are configured to be summed by a linear combiner. The method of claim 18, The de-emphasis circuit is a communication system, characterized in that implemented by an analog finite-duration impulse response filter.

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