JP7187804B2 - radar receiver - Google Patents

Description

The present invention relates to radar receivers.

In recent years, many technologies such as collision prevention and automatic driving have been proposed, and technology that uses sonar and millimeter-wave radar technology to measure the distance from a mobile device to a target has attracted attention. Conventionally, sonar is used to measure the distance to a relatively nearby target of 1 m or less, and millimeter-wave radar is used to measure a longer distance, for example, 1 m to several hundred meters.

In recent years, there has been an increasing demand for monitoring within 1 m using millimeter wave radar. However, the reflected signal from the target within 1 m has a large voltage amplitude, and the signal is distorted when the signal is amplified using the receiving circuit.

Saturation cannot be avoided by lowering the gain of the receiver when the received signal is greater than a predetermined value, as is the case with popular mobile phones. Therefore, the radar receiver is required to receive both weak reflected signals from distant targets and large reflected signals from nearby targets at the same time and not to saturate the internal signals. Various techniques have been proposed to improve the linearity of input/output power over a wide frequency range (see, for example, Patent Document 1).

According to the technique described in Patent Document 1, a signal is amplified while improving linearity by using a transimpedance amplifier in the subsequent stage of the frequency converter. However, even if the received signal is amplified, if the power supply voltage is exceeded, the signal is clamped and distorted. In order to avoid this clamping, the gain of the frequency converter or transimpedance amplifier must be lowered. It becomes a factor that increases the probability. Therefore, it is desirable to increase the power supply voltage in order to improve the linearity of the input/output power over a wide frequency range. However, since power consumption increases when the power supply voltage is increased, it is desired to be able to operate stably even with a low power supply voltage.

JP 2010-147988 A

SUMMARY OF THE INVENTION It is an object of the present invention to provide a radar receiver capable of amplifying a received voltage without saturating the voltage even when operated using a low power supply voltage.

The invention according to claim 1 comprises a transmitter that converts a modulated signal using a frequency modulation method that gradually increases or decreases in frequency and outputs it to a target as a radar transmission wave, and a receiver that receives the signal reflected by the target. The target is a radar receiver that constitutes a receiver in a radar device equipped with the present invention. According to the first aspect of the invention, the n branch amplifiers have the characteristic of amplifying in a band including at least the same frequency. Since the voltage of the received signal is amplified as it is, the current can be amplified while being shunted. As a result, the synthesizing unit synthesizes the voltages of the signals amplified by the n branch amplifying units, so that the voltage can be amplified without saturating the voltage even when operating using a low power supply voltage. become.

1 is an electrical configuration diagram of a radar device according to a first embodiment; FIG. Explanatory diagram of frequency modulation method Part 1 Explanatory diagram of frequency modulation method, part 2 Explanatory diagram of the relationship between the time from when the transmitter outputs the radar transmission wave until the receiver receives the signal, the transmission frequency, and the reception frequency Characteristic diagram schematically showing the relationship between the distance to the object, the intermediate frequency, and the voltage amplitude Electrical configuration diagram of the amplifier Electrical configuration diagram of the amplifier in the second embodiment Electrical configuration diagram of the amplifier in the third embodiment Electrical configuration diagram of the amplifier in the fourth embodiment Explanatory diagram showing the time change of the output voltage of the comparator Timing chart explaining operation

Several embodiments of the radar receiver will be described below with reference to the drawings. In each of the embodiments described below, the same or similar reference numerals are assigned to configurations that perform the same or similar operations, and description thereof will be omitted as necessary. In the following embodiments, the same or similar configurations are described by attaching the same reference numerals to the tens digit and the ones digit of the reference numerals.

(First embodiment)
1 to 5 show explanatory diagrams of the first embodiment. FIG. 1 schematically shows an electrical configuration of a radar device 1 that constitutes a millimeter wave radar system.
This radar device 1 is configured by connecting a MCU (Micro Control Unit: or MPU (Micro Processing Unit)) 2 and a semiconductor integrated circuit device 3 by MMIC (Monolithic Microwave Integrated Circuit), , vehicles). The MCU 2 includes a memory 4 such as a non-volatile memory and a volatile memory, and is connected to the semiconductor integrated circuit device 3 so as to be capable of serial communication.

The semiconductor integrated circuit device 3 mainly includes a transmitter 5, a receiver (corresponding to a radar receiver) 6, and a digital control unit 7, and is constructed by a miniaturized CMOS process. 1.8V is a low power supply voltage.

The digital control unit 7 includes a logic circuit 8, a register bank 9, a register bank interface 10, an SRAM controller 11, an SRAM 12, a nonvolatile memory controller 13, a nonvolatile memory 14, and a serial interface 9s. This digital control unit 7 stores various set values in the control registers of the register bank 9 by communicating with the external MCU 2 through the serial interface 9s, and the MCU 2 uses the logic circuit 8 of the digital control unit 7 configured to control.

A serial interface 9 s is arranged between the MCU 2 and an internal register bank 9 , and is capable of transferring data such as various setting values between the MCU 2 and the register bank 9 . The controllers 11 and 13 control the SRAM 12 and nonvolatile memory 14 respectively, and are configured to transfer data between the SRAM 12 and nonvolatile memory 14 and the register bank 9 through the register bank interface 10 . The logic circuit 8 refers to the data transferred to the register bank 9 and controls the transmitter 5 and receiver 6 based on this data.

The transmitter 5 has an amplifier 16 that amplifies the modulated signal output from the PLL 15 under the control of the digital controller 7 . The PLL 15 gradually increases/decreases the frequency over time according to the frequency command stored in the register bank 9 of the digital control unit 7 under the control of the MCU 2, for example, by frequency modulation using FCM (Fast-Chirp Modulation) modulation. A local signal (corresponding to a modulated signal) LO is generated, and the generated local signal LO is output to the amplifier 16 of the transmitter 5 and the frequency converter 19 of the receiver 6 . The amplifier 16 amplifies this local signal LO and outputs it to the outside as a radar transmission wave through the transmission antenna 17 .

2A and 2B show descriptions of modulated signals according to the FCM modulation scheme. As shown in FIG. 2A, the PLL 15 linearly decreases (that is, gradually decreases) the frequency from the initial frequency fsta at a certain timing ts1 and outputs a frequency that reaches the final frequency fsto at a timing ts2, and then returns to the initial frequency fsta. It outputs a local signal LO that returns step by step. The PLL 15 may also be configured to output a local signal LO as shown in FIG. 2B. That is, the PLL 15 may linearly increase (that is, gradually increase) the frequency from a certain initial frequency fsta, reach the final frequency fsto, and then modulate the frequency to return to the initial frequency fsta. In the following, as shown in FIG. 2A, an example using a frequency modulation method that gradually decreases the frequency with time will be described.

As shown in FIG. 1, radar transmissions reflect off target 18 . The receiver 6 is a direct conversion receiver mainly including a frequency converter 19 and an amplifier section 20 with a high-pass filter. The receiver 6 further includes an A/D converter 22 and receives radar waves reflected by the target 18 from a receiving antenna 23 . The receiving antenna 23, the frequency converter 19, the amplifier 20, and the A/D converter 22 are cascaded in this order.

Frequency converter 19 mixes the signal received through receiving antenna 23 with the local signal LO output from PLL 15 and outputs this signal to amplifying section 20 . The amplifier 20 filters and amplifies the output of the frequency converter 19 and outputs the amplified output to the A/D converter 22 . The A/D converter 22 A/D converts the output of the amplifying section 20 and stores it in the register bank 9 after performing digital filter processing as necessary. This data is output to the MCU 2 through serial communication through the serial interface 9s. The MCU 2 measures the distance between itself and a target 18 that exists in front of the vehicle, for example, based on the data received through serial communication.

FIG. 3 shows the relationship between the time from when the transmitter 5 outputs the radar transmission wave to when the receiver 6 receives the signal, and the transmission frequency fTX and reception frequencies fRXn and fRXf. The characteristics shown in FIG. 3 show temporal changes in the transmission frequency fTX and the reception frequencies fRXn and fRXf when a frequency modulation method is used in which the frequency of the radar transmission wave gradually decreases with time.
In FIG. 3, the reception frequency fRXn indicates the reception frequency when the target 18 is located near the radar device 1, and the reception frequency fRXf indicates the reception frequency when the target 18 is located far from the radar device 1. shows the reception frequency in the case of

After the PLL 15 outputs a signal of a certain first frequency f1 to the amplifier 16 and the frequency converter 19 at a certain timing t1 and the transmitter 5 outputs a radar transmission wave toward the target 18, the receiver 6 outputs this target 18 are received through the receiving antenna 23 at timings t2n and t2f.

The second frequencies f2n and f2f that the PLL 15 outputs to the amplifier 16 and the frequency converter 19 at the timings t2n and t2f are different from the first frequency f1 that is transmitted at the timing t1, and the second frequencies f2n and f2f are , is lower than the first frequency f1 at timing t1. When the target 18 exists near the radar device 1, the time from when the transmitter 5 outputs the radar transmission wave to when the receiver 6 receives it becomes short, and conversely, the target 18 exists far from the radar device 1. As a result, the time from transmission to reception of the radar transmission wave becomes long. Therefore, the frequency differences fIF1 and fIF2 depend on the distance between the radar device 1 and the target 18. FIG.

A frequency converter 19 converts the received signal with a local signal LO. Therefore, the frequency of the signal converted by this frequency converter 19 is fIF1=(first frequency f1 of received signal)-(second frequency f2n of local signal LO) when target 18 is located nearby, and fIF2 =(first frequency f1 of received signal)-(second frequency f2f of local signal LO). The frequency differences fIF1 and fIF2 change depending on the distance.

For example, when the target 18 is positioned in the vicinity of the radar device 1 (for example, about 1 m), the frequency of the signal after conversion by the frequency converter 19 is about fIF1=100 [kHz], and the target 18 is located near the radar device 1. When located far away (for example, about 200 m), the frequency of the signal after conversion by the frequency converter 19 is about fIF2=20 [MHz]. Therefore, the input signal to the amplifier 20 is a signal with a frequency that varies depending on the distance from the target 18 .

FIG. 4 also schematically shows the relationship between the distance to the target 18 and the voltage amplitude Vp-p at the intermediate frequency fIF. As shown in FIG. 4, when the target 18 is located in the vicinity of the radar device 1, the voltage amplitude Vp-p of the signal after conversion by the frequency converter 19 increases. Conversely, when the target 18 is located far from the radar device 1, the voltage amplitude Vp-p of the signal after conversion by the frequency converter 19 becomes small. This indicates that the voltage amplitude Vp-p changes depending on the distance between the radar device 1 and the target 18. FIG.

<Description of Configuration of Amplifier 20>
FIG. 5 shows the electrical configuration of the amplifier section 20. As shown in FIG. The amplifying section 20 includes a plurality (eg, n=4) of branch amplifiers 31a to 31d, n high-pass filters 32a to 32d, and a post-stage amplifier 33 as a synthesizing section. Each of the plurality of branch amplifiers 31a to 31d is a current-voltage converter configured by, for example, a trans-impedance amplifier (TIA), and is positioned downstream of the frequency converter 19 and connected in parallel. It is a configuration corresponding to

The plurality of branch amplifiers 31a to 31d have, for example, the same characteristics of amplifying in the same frequency band, and divide the signal received by the receiver 6, which is the signal after conversion by the frequency converter 19 in this embodiment, into n branches. Amplify in the state. The high-pass filters 32a-32d are connected after the branch amplifiers 31a-31d, respectively. These high-pass filters 32a to 32d are configured by connecting, for example, capacitors and resistors (unsigned) in series, and pass the high frequency side of the output voltage of the branch amplifiers 31a to 31d and reduce the low frequency side. is configured as

These high-pass filters 32a to 32d are set so that the cutoff frequency fc of the frequency component corresponding to a distance closer than a predetermined distance in the middle of the distance range for measuring the distance to the target 18 is gradually reduced. It is desirable that For example, when the distance range from the radar device 1 (self) to the target 18 is set to a measurable range of 50 cm to 200 m, a frequency corresponding to a predetermined intermediate distance (for example, 10 m) is set as the cutoff frequency fc. It is desirable to set the frequency components corresponding to distances closer than a predetermined distance so as to gradually decrease.

Then, the frequency component of the reflected signal from the nearby target 18 can be further reduced. The signal is no longer amplified and the amplitude can be adjusted appropriately. These cutoff frequencies fc are desirably the same among the plurality of high-pass filters 32a to 32d, but they do not necessarily have to be the same.

The outputs of these multiple high-pass filters 32a to 32d are combined at their output nodes and then input to the post-stage amplifier 33. FIG. That is, the post-stage amplifier 33 synthesizes the output voltages of the plurality of high-pass filters 32a-32d. The post-stage amplifier 33 is, for example, a voltage amplifier configured by combining operational amplifiers and resistors. Although the post-amplifier 33 is shown as an example of amplifying in one stage, it is not limited to one stage, and a plurality of stages may be connected in cascade for amplification.

The A/D converter 22 A/D-converts the output of the post-stage amplifier 33 and, if necessary, stores the data in the register bank 9 after digital filtering. The data stored in the register bank 9 are output to the MCU 2 through the serial interface 9s.

For example, the receiver 6 receives a reflected signal from a target 18 1 m away in the vicinity of itself with an amplitude of 63 mVp-p (=-20 dBm) at the high-frequency input terminal, and the reflected signal of the target 18 50 cm away is It will be received at 200mVp-p. On the other hand, the receiver 6 receives a reflected signal with an amplitude of 630 nVp-p (=-120 dBm) from a distant target 18 200 m away.

The receiver 6 is required to simultaneously receive both the reflected signal from the target 18 1 m away and the reflected signal from the target 18 200 m away. Therefore, if the power supply voltage VDD is 1.8 V, then 63 mVp-p×28≈1.8 V, so by multiplying the received signal by about 28, it will be saturated at the power supply voltage VDD and clipped. .

Therefore, in this embodiment, the receiver 6 is configured as described above. In this embodiment, the frequency converter 19 is configured to branch its output into n=4 and output, thereby branching the signal of the intermediate frequency fIF into four and branching amplifiers 31a to 31d respectively. is input to Since the frequency converter 19 divides the converted current, each of the plurality of branch amplifiers 31a to 31d can convert and amplify the current into a voltage.

Since only 1/n current flows into each of the plurality of branch amplifiers 31a to 31d, the amplitude of the output voltage of the plurality of branch amplifiers 31a to 31d also becomes 1/n. Therefore, even if the input voltage of the high-frequency input signal to the receiving antenna 23 increases to 200 mVp-p, the output voltage amplitudes of the plurality of branch amplifiers 31a to 31d are not saturated and clipped.

Further, when the receiver 6 receives a reflected signal with a large amplitude from the nearby target 18, the frequency difference fIF1 between the reception frequency fRXn of the radar reception wave and the local signal LO output from the PLL 15 is small. Transducer 19 outputs a signal of relatively low frequency fIF1.
At this time, although the plurality of branch amplifiers 31a to 31d divert the converted current and amplify the voltage, the high-pass filters 32a to 32d reduce the low frequency, so that the signal can be attenuated and the amplitude can be reduced. It can be held reasonably. Therefore, even if the next post-amplifier 33 combines and amplifies the output voltages of the plurality of high-pass filters 32a to 32d, the amplitude of the amplified signal of the post-amplifier 33 will not be saturated.

When the receiver 6 receives a reflected signal from a distant target 18 with a minute amplitude, the frequency difference fIF2 between the reception frequency fRXf of the radar reception wave and the local signal LO output from the PLL 15 is large. 19 will output a signal of relatively high frequency fIF2. A plurality of branch amplifiers 31a to 31d voltage-amplify the converted current, but the high-pass filters 32a to 32d pass the high-frequency side as it is without attenuating the signal. Sufficient amplification can be achieved by synthesizing and amplifying the output voltages of ~32d. In this case, the amplitude of the amplified signal will not saturate.

Therefore, it is possible to moderately amplify the signal of the low frequency fIF1 converted corresponding to the target 18 in the vicinity while reducing the degree of amplification of the signal, and the signal of the high frequency fIF2 converted corresponding to the target 18 in the distance. It can be amplified moderately by increasing the degree of amplification.

The receiver 6 using such a frequency modulation method is required to have high linearity in its input/output power characteristics. Therefore, it is not preferable to install the high-pass filters 32a to 32d immediately after the frequency converter 19. FIG. When the high-pass filters 32a to 32d are used as the load of the frequency converter 19, the high-pass filters 32a to 32d have high input impedance in the low frequency region. In such a case, the input voltages of the high-pass filters 32a to 32d become large, and as a result, the output voltage amplitude of the frequency converter 19 becomes large and the output voltage is distorted.

As shown in this embodiment, by directly connecting the branch amplifiers 31a to 31d immediately after the frequency converter 19, the input impedance on the low-frequency side of the branch amplifiers 31a to 31d can be kept low, and the output of the frequency converter 19 Voltage amplitude can be suppressed and output voltage distortion of the frequency converter 19 can be prevented. In addition, since the output current of the frequency converter 19 is not suppressed, the current-voltage conversion gain after shunting can be obtained.

In this embodiment, the output of the frequency converter 19 is branched into n=4, but n is not limited to 4, and may be 2, 3, or 5 or more. The number n may be adjusted so that the voltage amplitude level is not saturated. If n=2 or more, the effect of effectively multiplying the power supply voltage VDD by n can be obtained.

As described above, according to this embodiment, the n branch amplifiers 31a to 31d amplify the received signals in n-branched state, and the post-stage amplifier 33 synthesizes these amplified signals. there is Therefore, even when operating with a low power supply voltage VDD, the received signal can be amplified without saturating the signal.

Further, the n high-pass filters 32a-32d pass the high-pass side of the signals amplified by the n branch amplifiers 31a-31d and step down the low-pass side, and the post-stage amplifier 33 filters the n high-pass The output signals of the filters 32a-32d are synthesized. Since the received signal on the low frequency side, which tends to have a large voltage amplitude, is stepped down, saturation of the output voltage can be prevented.

Moreover, the plurality of high-pass filters 32a to 32d are set so that the cutoff frequency fc of the frequency component corresponding to a distance closer than a predetermined distance in the middle of the distance range for measuring the distance to the target 18 is gradually reduced. With this arrangement, the operation can be performed without saturating the voltage on the low-frequency side, and even if a signal having a reception frequency fRXn corresponding to a distance closer than a predetermined distance is input, the voltage will not saturate.

(Second embodiment)
FIG. 6 shows an additional explanatory diagram of the second embodiment. FIG. 6 also shows the configuration of the low noise amplifier 21 . A receiver 206 that replaces the receiver 6 includes a plurality of frequency converters 19a and 19c (where n2≦n: n2=n/k; for example, two) as branch frequency converters. The frequency converters 19a and 19c are connected in parallel. This receiver 206 has a low noise amplifier (LNA) 21 between the receiving antenna 23 and the frequency converters 19a, 19c. After the low-noise amplifier 21 amplifies the signal received from the receiving antenna 23 with a gain of, for example, several dB, this amplified signal is split into n2 and output to the frequency converters 19a and 19c. These n2 frequency converters 19a and 19c each receive the output of the low noise amplifier 21, mix it with the local signal LO, and convert and output the frequency.

The outputs of these n2 frequency converters 19a and 19c are also input to n branch amplifiers 31a to 31d by, for example, k-branching and outputting. The configuration after the plurality of branch amplifiers 31a to 31d is the same as the configuration of the above-described embodiment, so the description is omitted. In this embodiment, n2 frequency converters 19a and 19c are provided, and k branches are made from each of the n2 frequency converters 19a and 19c and input to n branch amplifiers 31a to 31d.

When two (=n2) frequency converters 19a and 19c are provided as in this embodiment, the input voltage amplitude of the frequency converters 19a and 19c can be halved, and the input/output power of the receiver 206 The linearity of characteristics can be improved. For this reason, even if the target 18 is positioned near its own device and the output of the low-noise amplifier 21, that is, the input signal to the frequency converters 19a and 19c is large, the input amplitude of the frequency converters 19a and 19c is Even if the intermediate frequency (frequency difference) fIF is small, it can be amplified without saturation.

That is, the distortion caused by the frequency converters 19a and 19c is greatly related to the overall distortion of the signal received and processed by the receiver 206, and when the output of the configuration preceding the plurality of high-pass filters 32a to 32d is distorted, It is desirable to shunt and process the signal of , and to resynthesize the signal.

In this embodiment, n2=n/3, n/4, . The ratio k of the number n of is not limited to the ratio described above. Also, after the output of the low noise amplifier 21 is branched to n2 frequency converters 19a and 19c, it is further branched into k pieces, and finally branched into n pieces to be input to the branch amplifiers 31a to 31d. Although the form is shown, the way of branching is not limited to this. Note that n2=n, that is, k=1 may be satisfied, but this corresponds to the configuration of the first embodiment.

As described above, according to the present embodiment, the n2 frequency converters 19a and 19c convert the n2 branched signals with the local signal LO before being amplified by the n branch amplifiers 31a to 31d. ing. These frequency converters 19a and 19c are adapted to convert into converted currents of frequency components that change depending on the distance from the target 18, and the branch amplifiers 31a to 31d are finally divided into n. It is designed to be amplified in a branched state. Therefore, the input voltage amplitude of the frequency converters 19a and 19c can be reduced to 1/n2, and the linearity of the input/output power characteristics of the receiver 206 can be improved. For this reason, even if the target 18 is located near its own device, the input voltage amplitude of the frequency converters 19a and 19c can be reduced, the voltage can be amplified without being saturated, and the distance can be accurately measured. become.

(Third Embodiment)
FIG. 7 shows an additional explanatory diagram of the third embodiment. The same reference numerals are given to the same parts as in the second embodiment, the description is omitted, and the different parts will be described. As shown in the receiver 306 of FIG. 7, the amplification function of the low noise amplifier 21 may be divided into a front stage and a rear stage. That is, receiver 306 may be provided with multiple (n2) voltage buffers 34a and 34c located between low noise amplifier 21 and multiple (n2) frequency converters 19a and 19c. good.

By setting the gain of the low-noise amplifier 21 to, for example, 10 to 20 dB and setting the gains of the plurality of voltage buffers 34a and 34c to, for example, about 10 dB, the gains can be divided between the front and rear stages. For example, as in the above embodiment, when it is assumed that the output voltage is distorted in the amplification processing stage of the low noise amplifier 21 in the front stage of the plurality of branch amplifiers 31a to 31d, the circuit after the low noise amplifier 21 It is desirable to connect a plurality of voltage buffers 34a, 34c in parallel and resynthesize the processed signals of the voltage buffers 34a, 34c.

Although a plurality of voltage buffers 34a and 34c are connected in parallel to suppress distortion of the output voltage of the low noise amplifier 21, a plurality of voltage buffers 34a and 34c may be connected in parallel for other requirements. That is, these low-noise amplifier 21, voltage buffers 34a and 34c, and frequency converters 19a and 19c are configured using transistor elements, respectively. In order to meet the conditions of the endurance test, etc., a plurality of devices may be connected in parallel.

(Fourth embodiment)
8 to 10 show additional explanatory diagrams of the fourth embodiment. As shown in FIG. 8, the receiver 406 includes n (eg, 4) branch amplifiers 31a-31d, n (eg, 4) high-pass filters 32a-32d, and these branch amplifiers 31a-31d. 31d and high-pass filters 32a to 32d are set as a set, and switches SW1 and SW2 are provided as switching units for enabling/disabling at least one or more of these sets.

Other configurations of the radar device 1 (for example, the digital control unit 7 and the transmitter 5) are the same as those in the above-described embodiment (for example, the first embodiment), so description thereof will be omitted. In this embodiment, the logic circuit 8 of the digital control section 7 functions as a switching control section. In this embodiment, as shown in FIG. 8, the switches SW1 and SW2 are connected to enable/disable the functions of the parallel-connected branch amplifiers 31c to 31d and the high-pass filters 32c to 32d.

At this time, it is desirable to configure the switching control circuit 35 of these switches SW1 and SW2 as shown in FIG. A switching control circuit 35 for the switches SW1 and SW2 includes a comparator 36 and D latches 37 and 38 . The comparator 36 compares the signal voltage of the intermediate frequency fIF with a predetermined saturation voltage threshold Vth_Sat, and outputs the comparison result to the D latch 37 as an output CMP_OUT.

The D latch 37 is a so-called D flip-flop, and is configured by inputting the power supply voltage VDD to the D terminal and inputting the output of the comparator 36 to the clock terminal. configured by connecting to

The D-latch 38 is also a so-called D flip-flop, and is configured to input a chirp end output ChirpEnd to a clock terminal and receive the input of this clock terminal to switch the switches SW1 and SW2 on and off.
Here, the chirp end output ChirpEnd indicates a signal that the logic circuit 8 outputs "H" in an impulse form at timing ts2 in FIG. The post-amplifier 433 inputs its output to the A/D converter 22, and the A/D converter 22 inputs its output to the register bank 9 through a digital filter (not shown). The MCU 2 processes the data stored in the register bank 9 and measures the distance.

FIG. 9 is an explanatory diagram showing temporal changes in the output of the comparator 36, and FIG. 10 is a flowchart explaining the operation.
As shown in FIG. 10, the transmitter 5 starts outputting a chirp signal modulated by the FCM modulation method at timing ts1 in FIG. 2A (S1 in FIG. 10), and outputs a radar transmission wave to the outside. This radar wave is input to the receiver 406 by being reflected by the target 18 . When a high-frequency signal is input to the receiver 406, the frequency is converted by the frequency converter 19, then the branch amplifiers 31a to 31d amplify each by a predetermined amplification degree, and the high-pass filters 32a to 32d each amplify the high-frequency signal. and cuts the low frequencies for output.

The post-stage amplifier 433 synthesizes the outputs of the plurality of high-pass filters 32 a to 32 d, amplifies the signal of the intermediate frequency fIF, and inputs it to the A/D converter 22 . Further, the comparator 36 receives the signal output of the intermediate frequency fIF of the post-stage amplifier 433 from the terminal IF#OUT, detects saturation, and determines whether or not the saturation has occurred (S2 in FIG. 10).

If the voltage value of the output terminal IF_OUT of the post-amplifier 433 is not saturated, the result in S2 is NO, and the process waits until the chirp signal ends at timing ts2 in FIG. 2A (S3 in FIG. 10). Then, when the chirp signal ends at timing ts2, the MCU 2 uses the data stored in the register bank 9 to perform, for example, fast Fourier transform (FFT) processing to process the data (S4 in FIG. 10). , the intermediate frequency fIF of the terminal IF#OUT is calculated, and the distance corresponding to this intermediate frequency fIF is measured.

On the other hand, when the chirp signal ends at timing ts2 in FIG. 2A, the logic circuit 8 outputs a chirp end output ChirpEnd of "H". At this time, if the Q output of the D latch 37 remains "L", the switches SW1 and SW2 continue to be off.

For example, after that, when the voltage value of the terminal IF#OUT reaches the saturation voltage threshold Vth_Sat at timing ta in FIG. power supply voltage VDD=1.8V), and the Q output of the D latch 37 also becomes "H" (see timing ta in FIG. 9). At this timing ta, the switches SW1 and SW2 are kept off. At this timing ta, the saturation is detected. After that, the logic circuit 8 waits until the end timing of the chirp signal (ts2 in FIG. 2A) (S5 in FIG. 10).

At timing ts2 in FIG. 2, when the logic circuit 8 outputs the chirp end output Chirp_End of "H", the "H" output of the chirp end output Chirp_End is input to the clock terminal of the D latch 38. Then, the Q output of the D latch 38 becomes "H", thereby turning on the switches SW1 and SW2 (S6 in FIG. 10). In this embodiment, the parallel number is increased from two to four by turning on the switches SW1 and SW2. At this time, the output current doubles, but it is desirable to keep the voltage amplitude constant by halving the load resistance of the transimpedance amplifiers (TIAs) of the branch amplifiers 31a to 31d (S7 in FIG. 10). . Then the voltage gain can be kept constant and saturation can be prevented.

In this embodiment, the branching amplifiers 31a to 31d are switched between 2 parallels (ie, 2 branches) and 4 parallels (ie, 4 branches). It is not limited to the contents of the description of this embodiment. Although the outputs of the branch amplifiers 31a to 31d may be directly input to the comparator 36, it is desirable to input the output of the post-stage amplifier 433 to the comparator 36 in order to detect voltage saturation.

As described above, according to the present embodiment, the switches SW1 and SW2 enable/disable at least one or more of the plurality of branch amplifiers 31a to 31d and the plurality of high-pass filters 32a to 32d. is configured as Further, the switching control circuit 35 detects that the synthesized voltage obtained by synthesizing the output signals of the n high-pass filters 32a to 32d by the post-stage amplifier 433 reaches a predetermined saturation threshold voltage Vth_sat. By controlling SW1 and SW2, the synthetic voltage is controlled so as not to be saturated. Therefore, the amplitude of the composite voltage of the post-stage amplifier 433 can be adjusted and controlled, and the convenience of adjusting the signal amplitude can be improved.

(Other embodiments)
The present disclosure is not limited to the embodiments described above, and can be implemented in various modifications, and can be applied to various embodiments without departing from the scope of the present disclosure. For example, the following modifications or extensions are possible.
Although a form applied to a vehicle-mounted millimeter-wave radar has been shown, the present invention can be applied not only to vehicle-mounted systems, but also to radar systems and radar receivers in general.

Although the plurality of branch amplifiers 31a to 31d have the same amplification characteristics for amplifying in the same frequency band, the present invention is not limited to this, and the characteristics for amplifying in a band including at least the same frequency are shown. If so, it is not necessary to use amplifiers with the same frequency characteristics.

The configurations and functions of the multiple embodiments described above may be combined. A mode in which part of the above embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, all conceivable aspects can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the language in the claims.

Although the present disclosure has been described in accordance with the embodiments described above, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of this disclosure.

In the drawing, 1 is a radar device, 5 is a transmitter, 6 is a receiver (radar receiver), 31a to 31d are branch amplifiers (branch amplifiers), 32a to 32d are high-pass filters, 33 and 433 are post-amplifiers (combining section), and 35 denotes a switching control circuit (switching control section).

Claims (6)

A transmitter (5) that converts a modulated signal using a frequency modulation method that gradually increases or decreases in frequency and outputs it as a radar transmission wave to a target, and a receiver (6) that receives the signal reflected by the target. A radar receiver (6) constituting the receiver in the radar device (1),
n branch amplification units (31a) having characteristics of amplifying in a band including at least the same frequency, and amplifying the voltage of the received signal as it is in a state where the received signal is branched into n (where n≧2) ~ 31d) and
a synthesizing unit (33; 433) for synthesizing the analog voltages amplified by the n branch amplifiers;
radar receiver with further comprising n high-pass filters (32a to 32d) that pass the high frequency side of the signal amplified by the n branch amplifier units and reduce the low frequency side,
2. The radar receiver according to claim 1, wherein said synthesizing section synthesizes the output signals amplified by said n branching amplifiers and then processed by said n high-pass filters. 2. The n high-pass filters have cutoff frequencies set to gradually reduce frequency components corresponding to distances closer than a predetermined distance in the middle of a distance range for measuring the distance to the target. Radar receiver as described. switching units (SW1, SW2) for enabling/disabling at least one or more of the n branch amplifiers (31a to 31d) and the n high-pass filters (32a to 32d);
When it is detected that the combined voltage obtained by combining the output signals of the n high-pass filters by the combining section reaches a predetermined saturation threshold voltage, the switching section is controlled so that the combined voltage is not saturated. 3. The radar receiver according to claim 2, further comprising a switching control section (35) for controlling A converted current of a frequency component that changes depending on the distance from the target by converting the signal branched by n2 (where n2≦n) before being amplified by the n branch amplification units by the modulation signal. further comprising n2 branch frequency converters (19; 19a, 19c) that convert to
5. The n branch amplifiers amplify the n2 converted currents converted by the n2 branch frequency converters in a state of being finally branched into the n. radar receiver as described in . 6. The radar receiver according to any one of claims 1 to 5, wherein transimpedance amplifiers are used in said n branch amplifiers.

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