JP2019184339A - Radar receiver - Google Patents

Abstract

To provide a radar receiver which is made to be able to perform amplification without saturating a voltage even when operated using a low power supply voltage.SOLUTION: A radar receiver 6 receives signals reflected from a target. The n branch amplifiers 31a to 31d are equipped with characters to amplify at least each other in a band including the same frequency. The received signal is amplified in a state where n branches (where n≥2) are performed. For this reason, the signal can be amplified in a state where current is divided. A post-stage amplifier 33 synthesizes the signals amplified by the n branch amplifiers 31a to 31d.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a radar receiver.

  In recent years, many techniques such as collision prevention and automatic driving have been proposed, and a technique for measuring the distance from a mobile device to a target using sonar or millimeter wave radar technology has attracted attention. Conventionally, sonar measures a distance to a relatively close target of 1 m or less, and millimeter wave radar is used to measure a distance of, for example, 1 m to several hundreds m farther than this distance.

  In recent years, there has been a growing demand for monitoring near 1 m or less using millimeter wave radar. However, the reflected signal of the target within 1 m has a large voltage amplitude, and when the signal is amplified using the receiving circuit, the signal is distorted.

  As in the case of a mobile phone that is widely used, saturation cannot be avoided by reducing the gain of the receiver when the received signal is larger than a predetermined value. For this reason, the radar receiver is required to receive both a weak reflected signal from a distant target and a large reflected signal from a nearby target at the same time, and the internal signal is not saturated. Various techniques are provided to improve the linearity of input / output power in a wide frequency range (see, for example, Patent Document 1).

  According to the technique described in Patent Document 1, a signal is amplified while improving linearity by using a transimpedance amplifier in the subsequent stage of the frequency converter. However, even if the received signal is amplified, if the power supply voltage is exceeded, the signal is clamped and the signal is distorted. In order to avoid this clamping, the gain of the frequency converter and transimpedance amplifier must be lowered. However, if the gain is lowered, the weak reflected signal of the far target cannot be sufficiently amplified, and the far target is falsely detected. This is a factor that increases the probability. For this reason, it is desirable to increase the power supply voltage in order to improve the linearity of input / output power over a wide frequency range. However, since the power consumption increases when the power supply voltage is increased, it is desired to enable stable operation even when a low power supply voltage is used.

JP 2010-147988 A

  An object of the present invention is to provide a radar receiver capable of amplifying a received signal without saturating the voltage even when operated using a low power supply voltage.

  According to the first aspect of the present invention, there is provided a transmitter that converts a modulation signal using a frequency modulation method that gradually increases or decreases a frequency and outputs the signal as a radar transmission wave to a target, and a receiver that receives a signal reflected by the target. The radar receiver constituting the receiver in the provided radar apparatus is intended. According to the first aspect of the present invention, the n branch amplification units have a characteristic of amplifying at least in a band including the same frequency, and in a state where the received signal is divided into n branches (where n ≧ 2). Since it is amplified, it can be amplified in a state where current is shunted. As a result, the synthesis unit synthesizes the signals amplified by the n branch amplification units, so that even if the operation is performed using a low power supply voltage, it can be amplified without saturating the voltage.

Electrical configuration diagram of a radar apparatus according to the first embodiment Part 1 of an explanatory diagram of a frequency modulation system Part 2 of an explanatory diagram of the frequency modulation method Explanatory diagram of the relationship between the time from when the transmitter outputs a radar transmission wave until the receiver receives a signal, the transmission frequency, and the reception frequency Characteristic diagram schematically showing the relationship between the distance to the object and the intermediate frequency and voltage amplitude Amplifier electrical configuration diagram Electrical configuration diagram of amplifier in the second embodiment Electrical configuration diagram of amplifier in the third embodiment Electrical configuration diagram of amplifier in the fourth embodiment Explanatory drawing showing the time change of the output voltage of the comparator Timing chart explaining operation

  Hereinafter, several embodiments of the radar receiver will be described with reference to the drawings. In each embodiment described below, configurations that perform the same or similar operations are denoted by the same or similar reference numerals, and description thereof is omitted as necessary. In the following embodiments, the same or similar components are described by adding the same reference numerals to the tenth place and the first place.

(First embodiment)
1 to 5 are explanatory diagrams of the first embodiment. FIG. 1 schematically shows an electrical configuration of a radar apparatus 1 constituting a millimeter wave radar system.
The radar apparatus 1 is configured by connecting an MCU (Micro Control Unit: or MPU (Micro Processing Unit)) 2 and a semiconductor integrated circuit apparatus 3 using an MMIC (Monolithic Microwave Integrated Circuit). Mounted on the vehicle). The MCU 2 includes a memory 4 such as a nonvolatile memory and a volatile memory, and is connected to the semiconductor integrated circuit device 3 so that serial communication is possible.

  The semiconductor integrated circuit device 3 mainly includes a transmitter 5, a receiver (equivalent to a radar receiver) 6, and a digital control unit 7, and is configured by a miniaturized CMOS process. The power supply voltage VDD is, for example, The power supply voltage is as low as 1.8V.

  The digital control unit 7 includes a logic circuit 8, a register bank 9, a register bank interface 10, an SRAM controller 11, an SRAM 12, a nonvolatile memory controller 13, a nonvolatile memory 14, and a serial interface 9s. The digital control unit 7 communicates with the external MCU 2 through the serial interface 9 s to store various setting values in the control register of the register bank 9. The MCU 2 uses the logic circuit 8 of the digital control unit 7. Configured to control.

  The serial interface 9 s is configured between the MCU 2 and the internal register bank 9, and data such as various setting values can be transferred between the MCU 2 and the register bank 9. The controllers 11 and 13 are configured to control the SRAM 12 and the nonvolatile memory 14, respectively, and to be able to transfer data between the SRAM 12 and the nonvolatile memory 14 and the register bank 9 through the register bank interface 10. The logic circuit 8 refers to the data transferred to the register bank 9 and controls the transmitter 5 and the receiver 6 based on this data.

  The transmitter 5 includes an amplifier 16 that amplifies the modulation signal output from the PLL 15 in accordance with control by the digital control unit 7. The PLL 15 gradually increases / decreases the frequency in time according to a frequency modulation method using, for example, an FCM (Fast-Chirp Modulation) modulation method in accordance with a frequency command stored in the register bank 9 of the digital control unit 7 under the control of the MCU 2. A local signal (corresponding to a modulation signal) LO is generated, and the generated local signal LO is output to the amplifier 16 of the transmitter 5 and the frequency converter 19 of the receiver 6. The amplifier 16 amplifies the local signal LO and outputs it as a radar transmission wave to the outside through the transmission antenna 17.

  2A and 2B show the explanation of the modulation signal by the FCM modulation method. As shown in FIG. 2A, the PLL 15 linearly decreases (that is, gradually decreases) the frequency from the initial frequency fsta at a certain timing ts1 and outputs a frequency that reaches the final frequency fsto at the timing ts2, and then outputs the frequency to the initial frequency fsta. A local signal LO that returns stepwise is output. Further, the PLL 15 may be configured to output a local signal LO as shown in FIG. 2B. In other words, the PLL 15 may modulate the frequency so as to return to the initial frequency fsta after linearly increasing (that is, gradually increasing) the frequency from a certain initial frequency fsta to reach the final frequency fsto. In the following, as shown in FIG. 2A, an example using a frequency modulation system that gradually decreases the frequency with time change will be described.

  As shown in FIG. 1, the radar transmission wave is reflected by the target 18. The receiver 6 is a direct conversion receiver mainly including a frequency converter 19 and an amplifying unit 20 with a high-pass filter. The receiver 6 further includes an A / D converter 22 and inputs a radar reception wave reflected by the target 18 from the reception antenna 23. The receiving antenna 23, the frequency converter 19, the amplifying unit 20, and the A / D converter 22 are configured in cascade connection in this order.

  The frequency converter 19 mixes the signal received through the receiving antenna 23 with the local signal LO output from the PLL 15 and outputs this signal to the amplifying unit 20. The amplifying unit 20 amplifies the output of the frequency converter 19 while filtering it, and outputs it to the A / D converter 22. The A / D converter 22 performs A / D conversion processing on the output of the amplification unit 20, performs digital filter processing as necessary, and stores the digital filter processing in the register bank 9. This data is output to the MCU 2 by serial communication through the serial interface 9s. The MCU 2 measures, for example, the distance between the target 18 existing in front of the vehicle and the own device based on the received data received by serial communication.

FIG. 3 shows the relationship between the time from when the transmitter 5 outputs a radar transmission wave until the receiver 6 receives a signal, and the transmission frequency fTX and the reception frequencies fRXn and fRXf. The characteristics shown in FIG. 3 show temporal changes in the transmission frequency fTX and the reception frequencies fRXn and fRXf when a frequency modulation method that gradually decreases the frequency of the radar transmission wave is used.
In FIG. 3, the reception frequency fRXn indicates the reception frequency when the target 18 is located in the vicinity of the radar apparatus 1, and the reception frequency fRXf is the position where the target 18 is located far from the radar apparatus 1. In this case, the reception frequency is shown.

  After the PLL 15 outputs the signal of the first frequency f1 at a certain timing t1 to the amplifier 16 and the frequency converter 19 and the transmitter 5 outputs the radar transmission wave toward the target 18, the receiver 6 It is assumed that the reflected signal reflected from 18 is received through the receiving antenna 23 at timings t2n and t2f.

  At timings t2n and t2f, the second frequencies f2n and f2f output from the PLL 15 to the amplifier 16 and the frequency converter 19 are different from the first frequencies f1 transmitted at the timing t1, and the second frequencies f2n and f2f are It is lower than the first frequency f1 at the timing t1. When the target 18 exists in the vicinity of the radar apparatus 1, the time from when the transmitter 5 outputs the radar transmission wave to when the receiver 6 receives it is short. Conversely, the target 18 exists far from the radar apparatus 1. Then, the time from when the radar transmission wave is transmitted until it is received becomes longer. For this reason, the frequency differences fIF1 and fIF2 depend on the distance between the radar apparatus 1 and the target 18.

  The frequency converter 19 converts the received signal with the local signal LO. Therefore, the frequency of the converted signal by the frequency converter 19 is fIF1 = (first frequency f1 of the received signal) − (second frequency f2n of the local signal LO) when the target 18 is located nearby, and fIF2 = (First frequency f1 of received signal)-(second frequency f2f of local signal LO). The frequency differences fIF1 and fIF2 change depending on the distance.

  For example, when the target 18 is located in the vicinity (for example, about 1 m) of the radar apparatus 1, the frequency of the signal after the conversion by the frequency converter 19 is about fIF1 = 100 [kHz]. When located far away (for example, about 200 m), the frequency of the signal after the conversion by the frequency converter 19 is about fIF2 = 20 [MHz]. Therefore, the input signal of the amplification unit 20 is a signal having a frequency that varies depending on the distance to the target 18.

  FIG. 4 schematically shows the relationship between the distance to the target 18 and the voltage amplitude Vp-p at the intermediate frequency fIF. As shown in FIG. 4, when the target 18 is located in the vicinity of the radar apparatus 1, the voltage amplitude Vp-p of the signal converted by the frequency converter 19 becomes large. Conversely, when the target 18 is located far from the radar apparatus 1, the voltage amplitude Vp-p of the signal converted by the frequency converter 19 becomes small. This indicates that the voltage amplitude Vp-p changes depending on the distance between the radar apparatus 1 and the target 18.

<Description of Configuration of Amplifier 20>
FIG. 5 shows an electrical configuration of the amplifying unit 20. The amplifying unit 20 includes a plurality of (for example, n = 4) branching amplifiers 31a to 31d, n high-pass filters 32a to 32d, and a post-stage amplifier 33 as a combining unit. Each of the plurality of branch amplifiers 31a to 31d is a current-voltage converter configured by, for example, a trans-impedance amplifier (TIA), and is located in the subsequent stage of the frequency converter 19 and connected in parallel. It is the structure equivalent to.

  The plurality of branching amplifiers 31a to 31d have the same characteristics that are amplified in the same frequency band, for example, and branch the signal received by the receiver 6, that is, the signal converted by the frequency converter 19 in this embodiment into n branches. Amplify in state. The high pass filters 32a to 32d are connected to the subsequent stages of the branching amplifiers 31a to 31d, respectively. These high-pass filters 32a to 32d are each configured by connecting, for example, a capacitor and a resistor (unsigned) in series. The high-pass filters 32a to 32d pass through the high frequency side of the output voltages of the branch amplifiers 31a to 31d and gradually decrease the low frequency side. It is configured as follows.

  The plurality of high-pass filters 32a to 32d are set so that the cut-off frequency fc gradually decreases a frequency component corresponding to a distance closer to a predetermined distance in the middle of the distance range in which the distance to the target 18 is measured. It is desirable that For example, when the distance range from the radar apparatus 1 (own apparatus) to the target 18 is a measurable range of 50 cm to 200 m, the frequency corresponding to a predetermined intermediate distance (for example, 10 m) is set as the cut-off frequency fc. It is desirable to set so that the frequency component corresponding to the distance closer than the predetermined distance is gradually decreased.

  Then, the frequency component of the reflected signal from the nearby target 18 can be further reduced, and even if the amplitude of the reflected signal increases and the branch amplifiers 31a to 31d and the post-stage amplifier 33 amplify the signal, it is more than necessary. The signal is not amplified and the amplitude can be adjusted appropriately. These cutoff frequencies fc are desirably the same among the plurality of high-pass filters 32a to 32d, but are not necessarily the same.

  The outputs of the plurality of high-pass filters 32 a to 32 d are combined at the output node and then input to the post-stage amplifier 33. That is, the post-stage amplifier 33 synthesizes the output voltages of the plurality of high-pass filters 32a to 32d. The post-stage amplifier 33 is a voltage amplifier configured by combining an operational amplifier and a resistor, for example, and amplifies the combined output voltage of the plurality of high-pass filters 32 a to 32 d and outputs the resultant voltage to the A / D converter 22. Although the post-amplifier 33 shows an example in which one stage is amplified, the stage amplifier 33 is not limited to one stage, and may be configured to amplify by connecting a plurality of cascades.

  The A / D converter 22 performs A / D conversion processing on the output of the post-stage amplifier 33, performs digital filter processing as necessary, and stores the data in the register bank 9. The data stored in the register bank 9 is output to the MCU 2 through the serial interface 9s.

  For example, the receiver 6 receives a reflected signal from the target 18 of 1 m ahead in the vicinity of the own device at an amplitude of 63 mVp-p (= −20 dBm) at the high frequency input terminal, and receives the reflected signal of the target 18 50 cm ahead. Reception is performed at 200 mVp-p. On the other hand, the receiver 6 receives the reflected signal from the distant target 18 200 m ahead with an amplitude of 630 nVp-p (= -120 dBm).

  The receiver 6 is required to simultaneously receive the reflected signal from the target 18 1 m ahead and the reflected signal from the target 18 200 m ahead. For this reason, when the power supply voltage VDD is 1.8 V, 63 mVp−p × 28≈1.8 V, and therefore, when the received signal is multiplied by about 28, the power supply voltage VDD is saturated and clipped. .

  Therefore, in the present embodiment, the receiver 6 is configured as described above. In the present embodiment, the frequency converter 19 is configured to branch and output the output to n = 4, thereby dividing the signal of the intermediate frequency fIF into four, and the respective branch amplifiers 31a to 31d. To input. The frequency converter 19 divides the conversion current, so that the plurality of branch amplifiers 31a to 31d can convert and amplify the current into voltage.

  Since only a 1 / n current flows into each of the plurality of branch amplifiers 31a to 31d, the amplitude of the output voltage of the plurality of branch amplifiers 31a to 31d is also 1 / n. Therefore, even if the input voltage of the high-frequency input signal of the receiving antenna 23 increases to 200 mVp-p, the output voltage amplitudes of the plurality of branch amplifiers 31a to 31d are not saturated and are not clipped.

Further, when the receiver 6 receives a reflected signal with a large amplitude from the target 18 in the vicinity, the frequency difference fIF1 between the received frequency fRXn of the radar received wave and the local signal LO output by the PLL 15 is small. The converter 19 outputs a signal having a relatively low frequency fIF1.
At this time, although the plurality of branching amplifiers 31a to 31d shunt the conversion current and amplify the voltage, the high pass filters 32a to 32d thereafter reduce the low frequency, so that the signal can be attenuated and the amplitude can be reduced. It can be held moderately. Therefore, even if the subsequent post-stage amplifier 33 synthesizes and amplifies the output voltages of the plurality of high-pass filters 32a to 32d, the amplitude of the amplified signal of the post-stage amplifier 33 does not saturate.

  When the receiver 6 receives the reflected signal from the distant target 18 with a small amplitude, the frequency difference fIF2 between the received frequency fRXf of the radar received wave and the local signal LO output from the PLL 15 is large, so that the frequency converter 19 outputs a signal having a relatively high frequency fIF2. The plurality of branch amplifiers 31a to 31d amplify the conversion current, but the high-pass filters 32a to 32d pass through the high-pass side as they are without attenuating the signal, so that the succeeding-stage amplifier 33 in the next stage includes the plurality of high-pass filters 32a. It is possible to sufficiently amplify by synthesizing and amplifying the output voltage of ˜32d. In this case, the amplitude of the amplified signal does not saturate.

  Therefore, the signal of the low frequency fIF1 converted corresponding to the nearby target 18 can be appropriately amplified while reducing the signal amplification degree, and the signal of the high frequency fIF2 converted corresponding to the far target 18 is obtained. Amplification can be increased by increasing the degree of amplification.

  The receiver 6 using such a frequency modulation method is required to have high linearity in its input / output power characteristics. For this reason, it is not preferable to install the high-pass filters 32a to 32d immediately after the frequency converter 19. When the load of the frequency converter 19 is the high-pass filters 32a to 32d, the high-pass filters 32a to 32d have a high input impedance in the low frequency region. In such a case, the input voltage of the high-pass filters 32a to 32d increases, and as a result, the output voltage amplitude of the frequency converter 19 increases and the output voltage is distorted.

  As shown in the present embodiment, by directly connecting the branch amplifiers 31a to 31d immediately after the frequency converter 19, the low-frequency side input impedance of the branch amplifiers 31a to 31d can be kept low, and the output of the frequency converter 19 can be kept low. The voltage amplitude can be suppressed, and the output voltage distortion of the frequency converter 19 can be prevented. In addition, since the output current of the frequency converter 19 is not suppressed, the current-voltage conversion gain after the shunt can be obtained.

  In this embodiment, although the form which branched the output of the frequency converter 19 into n = 4 was shown, n is not limited to 4, It may be 2, 3, or 5 or more. The number n may be adjusted so that the amplitude level of the voltage is not saturated. If n = 2 or more, an effect of effectively multiplying the power supply voltage VDD by n can be obtained.

  As described above, according to the present embodiment, the n branch amplifiers 31a to 31d amplify the received signal in the n-branch state, and the post-stage amplifier 33 combines these amplified signals. Yes. For this reason, even when operating with a low power supply voltage VDD, the received signal can be amplified without saturating the signal.

  Further, n high-pass filters 32a to 32d pass the high-frequency side of the signal amplified by the n branch amplifiers 31a to 31d and gradually reduce the low-frequency side, and the rear-stage amplifier 33 includes n high-pass filters. The output signals of the filters 32a to 32d are synthesized. Since the low-frequency received signal, which tends to have a large voltage amplitude, is stepped down, saturation of the output voltage can be prevented.

  The plurality of high-pass filters 32a to 32d are set so that the cutoff frequency fc gradually decreases a frequency component corresponding to a distance closer to a predetermined distance in the middle of the distance range in which the distance to the target 18 is measured. Therefore, the operation can be performed without saturating the voltage on the low frequency side, and the voltage is not saturated even if a signal having the reception frequency fRXn corresponding to a distance closer to the predetermined distance is input.

(Second Embodiment)
FIG. 6 shows an additional explanatory diagram of the second embodiment. FIG. 6 also shows the configuration of the low noise amplifier 21. A receiver 206 in place of the receiver 6 includes a plurality (but n2 ≦ n: n2 = n / k: for example, two) of frequency converters 19a and 19c as branch frequency converters. The frequency converters 19a and 19c are connected in parallel. The receiver 206 includes a low noise amplifier (LNA) 21 between the receiving antenna 23 and the frequency converters 19a and 19c. The low noise amplifier 21 amplifies the signal received from the receiving antenna 23 with a gain of, for example, several dB, and then branches the amplified signal into n2 and outputs it to the frequency converters 19a and 19c. Each of these n2 frequency converters 19a and 19c branches and inputs the output of the low noise amplifier 21, mixes it with the local signal LO, and converts and outputs the frequency.

  The outputs of the n2 frequency converters 19a and 19c are also input to the n branch amplifiers 31a to 31d by, for example, k-branching and outputting. Since the configuration after the plurality of branch amplifiers 31a to 31d is the same as the configuration of the above-described embodiment, the description thereof is omitted. In this embodiment, n2 frequency converters 19a and 19c are provided, and k branches from the n2 frequency converters 19a and 19c, respectively, and input to n branch amplifiers 31a to 31d.

  When two frequency converters 19a and 19c (= n2) are provided as in this embodiment, the input voltage amplitude of the frequency converters 19a and 19c can be halved, and the input / output power of the receiver 206 can be reduced. The linearity of the characteristics can be improved. For this reason, even if the target 18 is located in the vicinity of the own device and the output of the low noise amplifier 21, that is, the input signal of the frequency converters 19 a and 19 c increases, the input amplitude of the frequency converters 19 a and 19 c is increased. Even if the intermediate frequency (frequency difference) fIF is small, it can be amplified without being saturated.

  That is, when the distortion of the frequency converters 19a and 19c is greatly related to the overall distortion of the reception processing signal of the receiver 206, and the output of the configuration of the preceding stage of the plurality of high-pass filters 32a to 32d is distorted, the preceding stage Are preferably shunted and processed, and it is desirable to re-synthesize the signal.

  In this embodiment, n2 = n / 3, n / 4..., That is, k may be any of 3, 4,..., The number n2 of these frequency converters 19a, 19c, and branch amplifiers 31a to 31d. The ratio k of the number n is not limited to the ratio described above. Further, after the output of the low noise amplifier 21 is branched to n2 frequency converters 19a and 19c, it is further branched into k and finally branched into n and input to the branching amplifiers 31a to 31d. Although a form is shown, the way of branching is not limited to this. Note that n2 = n, that is, k = 1 may be used, which corresponds to the configuration of the first embodiment.

  As described above, according to the present embodiment, the n2 frequency converters 19a and 19c convert the signal branched into n2 before being amplified by the n branch amplifiers 31a to 31d by the local signal LO. ing. These frequency converters 19a and 19c convert frequency component conversion currents that change depending on the distance between the target 18 and the branch amplifiers 31a to 31d finally become n. It amplifies in a branched state. For this reason, the input voltage amplitude of the frequency converters 19a and 19c can be reduced to 1 / n2, and the linearity of the input / output power characteristics of the receiver 206 can be improved. For this reason, even if the target 18 is located in the vicinity of the own device, the input voltage amplitude of the frequency converters 19a and 19c can be reduced, the voltage can be amplified without being saturated, and the distance can be accurately measured. It becomes like this.

(Third embodiment)
FIG. 7 shows an additional explanatory diagram of the third embodiment. The same parts as those of the second embodiment are denoted by the same reference numerals, and the description thereof is omitted. As shown in the receiver 306 in FIG. 7, the amplification function of the low noise amplifier 21 may be divided into a front stage and a rear stage. That is, the receiver 306 may be provided between the low noise amplifier 21 and a plurality (n2) of frequency converters 19a and 19c, and may include a plurality (n2) of voltage buffers 34a and 34c. good.

  By setting the gain of the low noise amplifier 21 to, for example, 10 to 20 dB and setting the gains of the plurality of voltage buffers 34a and 34c to, for example, about 10 dB, the gain can be divided at the front and rear stages. For example, as in the above-described embodiment, when it is assumed that the output voltage is distorted in the amplification processing stage of the low noise amplifier 21 in the previous stage of the plurality of branch amplifiers 31a to 31d, it is a subsequent circuit of the low noise amplifier 21. It is desirable to connect a plurality of voltage buffers 34a and 34c in parallel and re-synthesize the processing signals of the voltage buffers 34a and 34c.

  In order to suppress distortion of the output voltage of the low noise amplifier 21, a plurality of voltage buffers 34a and 34c are connected in parallel. However, a plurality of voltage buffers 34a and 34c may be connected in parallel for other requirements. That is, the low noise amplifier 21, the voltage buffers 34a and 34c, and the frequency converters 19a and 19c are each configured by using transistor elements. However, the rated conditions of the breakdown voltage of these transistor elements, various specifications, In order to satisfy the conditions of the durability test, etc., a plurality of them may be connected in parallel.

(Fourth embodiment)
8 to 10 show additional explanatory diagrams of the fourth embodiment. As shown in FIG. 8, the receiver 406 includes n (for example, four) branch amplifiers 31a to 31d and n (for example, four) high-pass filters 32a to 32d, and these branch amplifiers 31a to 31d. 31d and high-pass filters 32a to 32d are provided as switches, and switches SW1 and SW2 that switch at least one of these sets to valid / invalid are provided as a switching unit.

  Other configurations of the radar apparatus 1 (for example, the digital control unit 7 and the transmitter 5) are the same as those in the above-described embodiment (for example, the first embodiment), and thus the description thereof is omitted. In the present embodiment, the logic circuit 8 of the digital control unit 7 functions as a switching control unit. In the present embodiment, as shown in FIG. 8, the switches SW1 and SW2 are connected so that the functions of the branch amplifiers 31c to 31d and the high-pass filters 32c to 32d connected in parallel can be switched between valid and invalid.

  At this time, it is desirable to configure the switching control circuit 35 of these switches SW1 and SW2 as shown in FIG. The switch control circuit 35 for the switches SW1 and SW2 includes a comparator 36 and D latches 37 and 38. The comparator 36 compares the signal voltage of the intermediate frequency fIF with a predetermined saturation voltage threshold value Vth # Sat, and outputs the comparison result to the D latch 37 as an output CMP # OUT.

  The D latch 37 is a so-called D flip-flop, and is configured by inputting the power supply voltage VDD to the D terminal and inputting the output of the comparator 36 to the clock terminal. The Q terminal is the D terminal of the D latch 38 of the next stage. Connected to and configured.

The D latch 38 is also a so-called D flip-flop, and is configured to input a chirp end output ChirpEnd to a clock terminal and switch the switches SW1 and SW2 on and off in response to the input of the clock terminal.
Here, the chirp end output ChirpEnd indicates a signal that the logic circuit 8 outputs “H” in an impulse shape at the timing ts2 of FIG. Then, the post-stage amplifier 433 inputs the output to the A / D converter 22, and the A / D converter 22 inputs the output to the register bank 9 through a digital filter (not shown). The MCU 2 processes data based on the data stored in the register bank 9 and measures the distance.

FIG. 9 is an explanatory diagram showing a change in the output of the comparator 36 over time, and FIG. 10 is a flowchart for explaining the operation.
As shown in FIG. 10, the transmitter 5 starts the output of the chirp signal of the modulated signal by the FCM modulation method at the timing ts1 in FIG. 2A (S1 in FIG. 10), and outputs the radar transmission wave to the outside. The radar wave is input to the receiver 406 by being reflected by the target 18. When a high frequency signal is input to the receiver 406, after the frequency converter 19 converts the frequency, the branching amplifiers 31a to 31d amplify each with a predetermined amplification degree, and the plurality of high pass filters 32a to 32d respectively Pass through and cut the low range and output.

  The post-stage amplifier 433 combines the outputs of the plurality of high-pass filters 32 a to 32 d, amplifies the signal of the intermediate frequency fIF, and inputs the amplified signal to the A / D converter 22. Further, the comparator 36 inputs the signal output of the intermediate frequency fIF of the post-stage amplifier 433 from the terminal IF # OUT, detects saturation, and determines whether or not it is saturated (S2 in FIG. 10).

  If the voltage value of the output terminal IF # OUT of the post-stage amplifier 433 is not saturated, NO is determined in S2, and the process waits until the chirp signal ends at the timing ts2 in FIG. 2A (S3 in FIG. 10). If the chirp signal ends at timing ts2, the MCU 2 performs, for example, fast Fourier transform (FFT) processing using the data stored in the register bank 9 to perform data processing (S4 in FIG. 10). The intermediate frequency fIF of the terminal IF # OUT is calculated, and the distance corresponding to the intermediate frequency fIF is measured.

  On the other hand, when the chirp signal ends at the timing ts2 in FIG. 2A, the logic circuit 8 outputs the chirp end output ChirpEnd “H”. At this time, if the Q output of the D latch 37 remains “L”, the switches SW1 and SW2 are kept off.

  For example, when the voltage value of the terminal IF # OUT subsequently reaches the saturation voltage threshold Vth # Sat at the timing ta in FIG. 9, the comparator 36 detects this state, and the output CMP # OUT of the comparator 36 is “H” (= (The power supply voltage VDD = 1.8V), and the Q output of the D latch 37 also becomes “H” (see timing ta in FIG. 9). At this timing ta, the switches SW1 and SW2 are held off. At this timing ta, saturation is detected. Thereafter, the logic circuit 8 waits until the end timing of the chirp signal (ts2 in FIG. 2A) (S5 in FIG. 10).

  When the logic circuit 8 outputs the chirp end output Chirp # End to “H” at the timing ts <b> 2 in FIG. 2, the “H” output of the chirp end output Chirp # End is input to the clock terminal of the D latch 38. Then, the Q output of the D latch 38 becomes “H”, thereby turning on the switches SW1 and SW2 (S6 in FIG. 10). In the present embodiment, the number of parallels is increased from 2 to 4 by turning on the switches SW1 and SW2. At this time, the output current is doubled, but it is desirable to make the voltage amplitude constant by halving the load resistance of the transimpedance amplifier (TIA) of the branch amplifiers 31a to 31d (S7 in FIG. 10). . Then, the voltage gain can be kept constant and saturation can be prevented.

  In the present embodiment, the branch amplifiers 31a to 31d are switched between two parallel (ie, two branches) and four parallel (ie, four branches). The number of branches and the positions where the switches SW1 and SW2 are inserted are as follows. The description is not limited to the contents of the present embodiment. The outputs of the branch amplifiers 31a to 31d may be directly input to the comparator 36. However, in order to detect voltage saturation, it is desirable to input the output of the post-stage amplifier 433 to the comparator 36.

  As described above, according to the present embodiment, the switches SW1 and SW2 switch at least one of the plurality of branch amplifiers 31a to 31d and the plurality of high-pass filters 32a to 32d to valid / invalid. It is configured as follows. Further, the switching control circuit 35 switches when it detects that the combined voltage obtained by combining the output signals of the n high-pass filters 32a to 32d by the post-stage amplifier 433 has reached a predetermined saturation threshold voltage Vth # sat. Control is performed so that the combined voltage is not saturated by controlling SW1 and SW2. Therefore, the amplitude of the combined voltage of the post-stage amplifier 433 can be adjusted and controlled, and convenience related to signal amplitude adjustment can be improved.

(Other embodiments)
The present disclosure is not limited to the above-described embodiment, can be implemented with various modifications, and can be applied to various embodiments without departing from the gist thereof. For example, the following modifications or expansions are possible.
Although the form applied to the in-vehicle millimeter-wave radar has been shown, the present invention is not limited to the in-vehicle, but can be applied to all radar systems and radar receivers.

  The plurality of branch amplifiers 31a to 31d are shown to have the same amplification characteristic that amplifies each other in the same frequency band. However, the present invention is not limited to this. If provided, it is not necessary to use amplifiers having the same frequency characteristics.

  You may combine the structure and function of several embodiment mentioned above. An aspect in which a part of the above-described embodiment is omitted as long as the problem can be solved can be regarded as the embodiment. Moreover, all the aspects which can be considered in the limit which does not deviate from the essence of the invention specified by the wording described in the claims can be regarded as the embodiment.

  Although the present disclosure has been described based on the above-described embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including one element, more or less, are within the scope and spirit of the present disclosure.

  In the drawings, 1 is a radar device, 5 is a transmitter, 6 is a receiver (radar receiver), 31a to 31d are branch amplifiers (branch amplifiers), 32a to 32d are high-pass filters, and 33 and 433 are post-stage amplifiers (synthesizers). Part), 35 shows a switching control circuit (switching control part).

Claims (6)

A transmitter (5) that converts a modulated signal using a frequency modulation system that gradually increases or decreases a frequency and outputs the modulated signal to a target as a radar transmission wave, and a receiver (6) that receives a signal reflected by the target. A radar receiver (6) constituting the receiver in the radar device (1),
N branch amplifying units (31a to 31d) each having a characteristic of amplifying in a band including at least the same frequency and amplifying the received signal in n branches (where n ≧ 2);
A synthesis unit (33; 433) for synthesizing signals amplified by the n branch amplification units;
A radar receiver comprising: N high-pass filters (32a to 32d) that pass through the high frequency side of the signal amplified by the n branch amplification units and gradually decrease the low frequency side,
2. The radar receiver according to claim 1, wherein the synthesis unit synthesizes output signals processed by the n high-pass filters after being amplified by the n branch amplification units.   3. The n high-pass filters are set so that a cutoff frequency gradually decreases a frequency component corresponding to a distance closer to a predetermined distance in the middle of a distance range in which the distance to the target is measured. The described radar receiver. A switching unit (SW1, SW2) that switches at least one of the n branch amplifiers (31a to 31d) and the n high pass filters (32a to 32d) to valid / invalid;
The combined voltage is not saturated by controlling the switching unit when it is detected that the combined voltage obtained by combining the output signals of the n high-pass filters by the combining unit has reached a predetermined saturation threshold voltage. The radar receiver according to claim 2, further comprising: a switching control unit (35) that controls the radar receiver. A signal that has been branched by n2 (where n2 ≦ n) before being amplified by the n branch amplifiers is converted by the modulation signal, and a frequency component conversion current that varies depending on the distance to the target N2 branch frequency converters (19; 19a, 19c) for converting into
5. The n branch amplification units amplify the n2 conversion currents converted by the n2 branch frequency conversion units in a state where they are finally branched into the n pieces. The radar receiver described in 1.   The radar receiver according to claim 1, wherein a transimpedance amplifier is used for the n branch amplification units.

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