TWI228693B - Angle wave generating circuit of plane display and angle wave generating method - Google Patents

Abstract

An angle wave generating circuit of plane display and angle wave generating method, the angle wave generating circuit receives an input voltage and a trigger voltage. The angle wave generating circuit comprises a first switch, a Zener diode, a second switch and a control circuit. A terminal of the first switch receives the input voltage and another terminal of the first switch couples to the output of the angle wave generating circuit. The input of the Zener diode is coupled to the output of the angle wave generating circuit. The second switch determines that whether the Zener diode is grounded. The control circuit receives and accords the trigger voltage to decide to open or close the first switch and the second switch. The control circuit further decides that the output of the angle wave generating circuit outputs the output voltage that transmitted by the first switch or the output voltage that clamped by the Zener diode.

Description

1228693 Case No. 92131751 V. Description of the invention (1) [Technical field to which the invention belongs The present invention relates to a device for displaying on a plane. [Prior art] Domain Zheng # change the page 'year 9a to amend a device to change the chamfered waveform, and in particular to change the chamfered waveform in the display to eliminate 4 frequencies in Transi, whose liquid crystals are crossed, as Connect the poles, and move the front image like a signal. The waveform is changed from the front end to the system definition. Thin Film Crystal Display (TFT-LCD) system includes a pair of electrode substrates, and the electrodes are filled with electrons. In a liquid crystal display, the signal lines and the scanning lines are perpendicular to each other and the matrix forms a matrix. Among them, each thin film transistor (TFT) in the scan line turns on these thin film transistors to control whether to write to a stor-liquid on the market and to control whether it is electrically connected to the liquid crystal display. Refer to FIG. 5A and The waveform of the driving voltage at the terminal to the RC constant on the scanning line (such as the wave in Figure 5 A and Figure 5 B is: Figure 5 B, which shows the conventional gate drive and the end of the gate drive line respectively. The parasitic resistance and parasitic capacitance of the waveform of the driving voltage have a delay change as shown in Figure 5A, so the waveform drawn in the scan line graph) will be shaped at the end of the scan line. The coupling voltage of the gate of the thin film transistor is V. sub.C0UPLED = V. Sub.GCsub.gs/(C. Sub.gs + C. Sub.L C + C. Sub.ST) where V.sub .G is the voltage supplied to the gate, C.sub.gs is the gate

12026twf1.ptc Page 10 1228693 Case No. 92131751 I Correction of the month Η V. Description of the invention (2) Capacitance between the source and the electrode, C. sub. ST is a kind of storable capacitor. In the conventional technique, the voltage supplied to the gate of the thin film transistor at the front end of the scan line is V · s u b. G 1, and the voltage supplied to the gate of the thin film transistor at the end of the scan line is V.sub.G2. Because V.sub.Gl is larger than V. sub. G2, the coupling voltage V.sub.COUPLED1 will be greater than V. sub. COUPLED2, which causes the daytime display of the LCD to flicker. In order to solve the problem of flicker, the conventional technique is to reduce the gate voltage. Please refer to FIG. 6 for a circuit diagram of a conventional flicker reduction device. In FIG. 6, the conventional flicker reduction device 6 0 0 includes an RC circuit composed of a resistor and a capacitor, a first switch 6 2 0, and a second Switch 6 3 0 and reverse brake 6 4 0. The trigger voltage is used to control the opening and closing of the first switch 6 2 0 and the second switch 6 3 0. When the first switch 6 2 0 is turned off and the second switch 6 30 is turned on, the RC circuit can receive the input voltage and charge it; otherwise, when the first switch 6 2 0 is turned on and the second switch 6 3 0 is turned off, The RC circuit will discharge. Therefore, it can be seen from the above that V.sub.G G during charging will be larger than V.sub.GH during discharging. Next, please refer to FIG. 7A and FIG. 7B, which respectively show waveform diagrams of the driving voltages of FIGS. 5A and 5B after being chamfered. Since the driving voltage at the front end of the scanning line is chamfered, the input voltage V. S u b. G 1 of the gate will be almost equal to the voltage V. S u b. 2 transmitted to the end of the scanning line. Therefore, since the coupling voltage V.sub.COUPLED1 is almost equal to V.sub.COUPLED2, the situation of daytime flicker can be avoided. However, although this flicker reducing device can avoid the capacitance of the sub cell,

12026twf1.ptc Page 11 Case No. 92131751 1228693 Amendment

V. Description of the invention (3) There are four frequency bands to avoid the situation of day and night, but the problem. Please continue to refer to Figure 6, whose output voltage is output to the four gate integrated circuits of the flat panel display. On the COG (Chip On Glass) architecture, because the WOA (WireON A r a y) line resistance is relatively large, it will cause the waveforms of the drive voltages on the scan lines of the four gate integrated circuits to be inconsistent. Please refer to FIG. 8A, FIG. 8B, and FIG. 8C, which respectively show the driving voltages of the first-stage gate-integrated circuit and the second-, third-, and fourth-stage gate-integrated circuits. Waveform diagram of time. After amplifying the waveform, it can be clearly seen that the difference between the driving voltage of the gate integrated circuit of the first stage (curve 80 2) and the second stage (curve 80 4) can reach 375mV, and the first stage (curve 802) ) And the third stage (curve 8 0) the gate voltage of the gate integrated circuit is 7 7 2 m V, the first stage (curve 8 0 2) and the fourth stage (curve 8 0 8) gate product The difference between the driving voltages of the body circuits is 1069 mV. Because the cut-off waveforms of the four gate integrated circuits will be inconsistent, it will cause the feed-through effects of the four gate integrated circuits to be different, so that there will be four frequency bands on the day surface of the LCD. [Summary of the Invention] The object of the present invention is to provide a chopper wave generating circuit for a flat panel display, which replaces the conventional resistor with a Zener Diode to change the driving of the gate integrated circuit output. Voltage, and reduce the difference in the angle waveforms of the gate integrated circuits, so that the feedthrough effect of the gate integrated circuits is more consistent. Another object of the present invention is to provide a method for generating a chamfered wave, which reduces the input voltage when the output voltage is at a chamfering time of 1/5.

12026twf1.pt c Page 12 1228693 _ Case No. 92131751_ Annual net exchange rate 丨 Amendment _ V. Description of the invention ⑷ Factory > 93 · The width of the poem is cut at 3/7 and the scale of f / Ύ is widened again between. The present invention provides a clipped wave generating circuit for a flat panel display. The clipped wave generating circuit receives an input voltage and a trigger voltage, and includes a first switch, a Zener diode, a second switch, and a control circuit. One terminal of the first switch receives the input voltage, and the other terminal is electrically coupled to the output terminal of the clipped wave generating circuit. The input of the Zener diode is electrically connected to the output of the clipped wave generating circuit, and the second switch is selectively coupled to the output of the Zener diode to determine whether the Zener diode is grounded. The control circuit receives and determines whether the first switch and the second switch are closed according to the trigger voltage. Among them, when the first switch is turned off and the second switch is turned on, the output terminal of the clipped wave generating circuit outputs the output voltage from the first switch; otherwise, when the first switch is turned on and the second switch is turned off, the clipped wave is output. The output terminal of the generating circuit outputs the output voltage clamped by the Zener diode. According to a preferred embodiment of the present invention, the time from when the second switch is turned off to when it is turned on again is the chamfering time, and during the chamfering time, the waveform of the input voltage is trimmed by a chamfering amplitude. The invention provides a method for generating a clipped wave. The method for generating a clipped wave is suitable for a flat display. This method firstly provides a trigger voltage and an input voltage, and then the control circuit of the clipped wave generating circuit determines whether to close the first switch and the second switch of the clipped wave generating circuit according to the triggering voltage. When the first switch is turned off and the second switch is turned on, the waveform of the input voltage is not clipped; otherwise, when the first switch is turned on and the second switch is turned off, the waveform of the input voltage is clipped within the chamfering time A clipped amplitude is cut to obtain a clipped wave. Finally, when the first switch is turned off and the second switch is hit

12026twf1.ptc Page 13 text #W 1L-8 years a Case No. 92131751 1228693 Amendment V. Description of the invention (5) When it is on, it will output the waveform of the original input αΓ voltage, and when the first switch is turned on and the second When the switch is turned off, this clipped wave is output. Among them, when the chamfering time is 1/5, the input voltage is cut off between 3/7 and 6/7. Because the present invention uses a Zener diode, the difference between the driving voltages of the output circuits of the first to fourth-level gate integrated circuits can be reduced, so that the feedback between the first-level to fourth-level gate integrated circuits is reduced. The pass effect is more consistent to eliminate the problem that the flat display has 4 frequency bands caused by the large difference in feed-through effect. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with reference to the accompanying drawings. [Embodiment] Please refer to FIG. 1A, which illustrates a circuit diagram for generating a clipped wave of a flat panel display according to a preferred embodiment of the present invention. The clipped wave generating circuit 1 0 0 receives an input voltage and a trigger voltage, and the clipped wave generating circuit 1 0 includes a Zener diode 1 1 0, a first switch 1 2 0, a second switch 1 3 0 and Control circuit 1 4 0. Among them, if those skilled in the art can easily know, the first switch 120 and the second switch 130 may include transistors, but they are not limited thereto. In this embodiment, one end of the first switch 120 receives an input voltage from, for example, a power supply (not shown), and the other end is electrically connected to the clipped wave generating circuit 100 Output 1 0 2. The Zener diode 1 10 has an input terminal 112 and an output terminal 114. The input terminal 112 of the Zener diode 110 is electrically coupled to the output terminal 102 of the clipped wave generating circuit 100. Second switch 1 3 0

12026twf1.ptc Page 14 1228693 Case No. 92131751 Replacement Army. Amendment V. Description of Invention (6) Year 93 · Ling ·-8 f) is selectively coupled to the Zener diode 1 1 0 ~ output terminal 1 14 to determine whether the Zener diode 1 1 0 is grounded. The control circuit 140 receives and determines whether the first switch 120 and the second switch 130 are closed according to the trigger voltage. In this embodiment, the operation mode of the clipped wave generating circuit 1 0 0 is that when the first switch 12 0 is turned off and the second switch 1 30 is turned on, the output terminal 1 0 2 of the clipped wave generating circuit 1 0 0 It directly outputs the output voltage from the first switch 120. Conversely, when the first switch 120 is turned on and the second switch 130 is turned off, the output terminal 100 of the clipped wave generating circuit 100 is output voltage clamped by the Zener diode 110. . The output voltage clamped by the Zener diode 110 is the output voltage of the clipped wave after the clipped angle. In this embodiment, the time from when the second switch is turned off to when it is turned on again is the chamfering time, and during this chamfering time, the waveform of the input voltage will be trimmed by a chamfering amplitude. Please refer to FIG. 1B, which illustrates a detailed circuit diagram of a clipped wave generating circuit of a flat panel display according to a preferred embodiment of the present invention. In Fig. 1B, it is only one detailed circuit for realizing the clipped wave generating circuit 100. In actual circuit design, it should not be limited to this. In FIG. 1B, the first switch 12 is composed of a transistor Q 7 and a resistor R 1 5 4. The second switch 1 3 0 is composed of a resistor R 1 5 6 and a transistor Q 8. The control circuit 1 40 is composed of resistors R159, R158 and R157, capacitors C128, C127, and transistors Q10, Q9. In Figure 1B, the coupling relationship between the first switch 1 2 0, the second switch 1 3 0, the control circuit 1 4 0 and the Zener diode 1 1 0 in the clipped wave generating circuit 100 As described in Figure 1A. Please refer to FIG. 2, which illustrates a preferred embodiment of the present invention.

12026twf1.ptc Page 15 1228693 Case No. 92131751 is replacing the year (__ «V. Description of the Invention (7)! '^ G3. ^ -8r shows a flat display *' In Figure 1 ', the flat display 2 0 0 includes a clipped wave generating circuit 2 1 0, four gate integrated circuits 2 2 0 and a liquid crystal panel 2 3 0. In this embodiment, as described in FIG. 1A, the clipped wave generating circuit The output of the circuit 2 0 includes the output voltage without a chamfer and the output voltage with a chamfer, and the chamfer wave generating circuit 2 0 outputs the output voltage to the gate product circuit 2 2 0. Among them, the The first to fourth stage gate integrated circuits 220 are connected in series, and all have corresponding driving lines 2 2 2. Please refer to FIG. 2 and FIG. 3 A and FIG. 3 B, which are drawn separately. A waveform diagram of driving voltage and time of a first-stage gate-integrated circuit and a second-stage gate-integrated circuit according to a preferred embodiment of the present invention, and a first-stage gate-integrated circuit and a fourth stage Waveform diagram of output drive voltage and time of gate integrated circuit. In Figure 3A, the output of the first-stage gate integrated circuit 2 2 0 The dynamic voltage is curve 3 2 and the driving voltage output of the second-stage gate integrated circuit 2 2 0 is curve 3 0. From the curves 3 0 2 and 3 0 4 in the waveform diagram, it can be seen that the first The difference between the driving voltages of the two-level gate integrated circuit 2 2 0 and the second-level gate integrated circuit 220 is very small, which is small compared with the two driving voltages of 375 mV in the conventional figure 8 A. Many, and in FIG. 3B, the difference between the driving voltages output by the first-stage gate integrated circuit 2 2 0 and the fourth-stage gate integrated circuit 2 2 0 can be as large as 1069 mV from the conventional figure 8C. Reduced to only a gap of 220 m V. Please refer to FIG. 4A, which shows a flowchart of the steps of a method for generating a clipped wave according to a preferred embodiment of the present invention. In this embodiment, this method is First provide the trigger voltage and input voltage to the clipped wave generating circuit (s402) °

12026twf1.ptc Page 16 1228693 [WTT ^ ~ 1 _Case No. 92131751_ > Acoustic Correction_ 彳 Correction_ V. Description of the Invention (8): Year 93Ύ · 8F, and then, Xiao Shao ’s angular wave generation circuit control If electric 1 ^ is to decide whether to close the first switch and the second switch of the clipped wave generating circuit (s 4 0 4) according to the trigger voltage. Among them, when the first switch is turned off and the second switch is turned on, the input voltage is not changed; conversely, when the first switch is turned on and the second switch is turned off, the waveform of the input voltage is changed within the chamfer time Cut off a chamfer amplitude to get a chamfered wave. Finally, when the first switch is turned off and the second switch is turned on, the original input voltage waveform is output, and when the first switch is turned on and the second switch is turned off, this clipped wave (s 4 0 6). Please also refer to FIG. 4B, which shows an input voltage waveform diagram after chamfering according to a preferred embodiment of the present invention. In Figure 4B, T represents the chamfering time, and D represents the chamfering amplitude. Among them, at 1/5 T, the amplitude of the input voltage being clipped is between 3/7 D and 6/7 D. In a preferred embodiment of the present invention, when the chamfering time is 2/5 T, the amplitude of the input voltage being cut off is between 60/7 0 D and 67/7 0 D. In a preferred embodiment of the present invention, when the chamfering time is 3/5 T, the amplitude of the input voltage being cut off is between 6 5/7 0 D and 6 8/7 0 D. In the preferred embodiment of the present invention, the chamfering time is 4/5 T, and the input voltage is clipped between 6 7/7 0 D and 6 9/7 0 D. To sum up, the clipped wave generating circuit of the present invention uses a Zener diode to reduce the difference between the clipped waveforms of the driving voltages output from the first-stage gate product circuit to the fourth-stage gate product circuit. In order to reduce the feed-through effect of the first-level gate integrated circuit to the fourth-level gate integrated circuit, not only the flicker of the daytime display of the flat display is reduced, but also the brightness of the daytime display of the flat display is left

12026twf1.ptc Page 17% 1212693 Replacement of Amendment No. 92131751 V. Description of Invention (9) 93. y. The year Λ is the right average, and there will not be 4 M bands. The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be regarded as The appended application patents shall prevail.

12026twf1.ptc Page 18

1228693 Brief description of the diagram The wave after the 7B corner The 8A body circuit and diagram. Section 8B body circuit and diagram. 8C body circuit and diagram. [Schematic symbol 1 00 1 02 110 112 120 1 30 140 200 220 230 302 600

Amendment No. 92131751 The figure shows a cut-out diagram of the driving voltage at the end of the gate drive line in Figure 5B. The figure is a waveform diagram showing the driving voltage and time of the first-stage gate product and the second-stage gate product circuit in a conventional flat-screen display. The waveform diagram of the driving voltage and time of the gate integrated circuit is a waveform description of the driving voltage and time of the first-level gate product and the fourth-level gate integrated circuit in a conventional flat display.] 2 1 0 : Clipped wave generating circuit, 1 14: Output terminal: Zener diode: Input terminal, 6 2 0: First switch, 6 3 0: Second switch control circuit, flat display, gate integrated circuit, liquid crystal panel 3 0 4 > 3 0 8, 802, 804 > 8 0 6, 808:, driving voltage reducing flicker device

12026twf1.ptc Page 20 1228693 Case No. 92131751 rw J curtain replacement correction 93. Simple illustration of the diagram 640: reverse brake C, C21, C1 27, C128: capacitors R, R17, R154, R156, R157, R158, R159: Resistors Q7, Q8, Q9, Q10: Transistor s402: Provides input voltage and trigger voltage s 4 0 2: Selectively cuts the input voltage by a clip angle within the clip time in accordance with the trigger voltage to obtain a clipped wave s 4 0 6: Output this clipped wave

B

12026twf1.ptc Page 21

Claims (1)

1228693 Case No. 92131751 Amendment VI. Patent Application Scope 1. A flat display voltage and a trigger voltage, the first switch, the second output terminal of the first switch; 'a Zener diode' with The input terminal is electrically coupled to the second switch for whether or not; and a control circuit receives one of the switch and the second switch, and when the output terminal of the first open circuit is opened as the first switch The output end is connected to its angular wave production pressure, which generates a voltage. 2. Generate electricity 3. The fourth 4. Generate circuit. 5. The second switch of the first patent application is a circuit of the scope of patent application of Jingru, including a clipped wave generating circuit that receives an input. The clipped wave generating circuit includes: one end of a switch receives the input. Voltage, it is electrically coupled to the input terminal and output terminal of the clipped wave generating circuit, and the output terminal of the Zener diode clipped wave generating circuit; determines that the output terminal of the Zener diode is grounded and paralleled. According to the trigger voltage, it is used to determine whether the first switch is turned off or not. When the second switch is turned on, the cutting output is output from the first switch, and when the second switch is turned off, the clipping wave The output wave clamped by the Zener diode is as described in the flat-panel display of the flat-panel display as described in the first item of the patent application scope, which is composed of a transistor. The body of the clipped wave generating circuit described in item 1. The clipped wave of the flat panel display described in item 1 is coupled to the gate integrated circuit of one of the flat display devices. The clipped wave of the flat panel display described in item 4 of the scope of patent application 12026twf1.ptc Page 22 1228693 Case No. 92131751 1¾¾ Page Amendment 1228693 Case No. 92131751 1¾¾ Page Amendment Thousand Days 6. Patent application range generation circuit, which outputs the output voltage to the gate product of the flat display Circuit. 6. A method for generating a chamfered wave, which is applicable to a flat display, the method includes: providing a trigger voltage; providing an input voltage; selectively cutting the input voltage within a chamfer time according to the trigger voltage. Removing a chamfering amplitude to obtain a chamfering wave; and outputting the chamfering wave, wherein, at a time of the chamfering time of 1/5, the amplitude at which the input voltage is cut off is the chamfering of 3/7 The amplitude is between 6/7 of this chamfered amplitude. 7 · The method of generating a chamfered wave as described in item 6 of the scope of the patent application, wherein when the chamfering time reaches 2/5, the input voltage is clipped by the chamfering angle of 60/70 The amplitude is between this and 7 7/7 0. 8. The method of generating a chamfered wave as described in item 6 of the scope of the patent application, wherein when the chamfering time reaches 3/5, the amplitude of the input voltage being cut off is at the chamfering of 6 5/70 Between the amplitude and this clipped amplitude of 6 8/70. 9. The method of generating a chamfered wave as described in item 6 of the scope of the patent application, wherein when the chamfering time reaches 4/5, the input voltage is clipped by an amplitude of 6 7/70 Between the amplitude and this clipped amplitude of 6 9/70. 12026twf1.ptc Page 23