TWI227836B - A computer system with multi-function input/output interface architecture - Google Patents

Abstract

A computer system with multi-function input/output interface architecture. The computer system uses the bus of a plurality of multi-function IO interface between central processing unit (CPU), memory modules, peripheral components and chipset units. The computer system includes a CPU; a first chip connected to CPU via a front side bus; a system memory connected to the first chip via a bus of a multi-ratio bandwidth memory architecture; a graphic card module connected to the first chip via a bus of a multi-function IO interface architecture and a second chip connected to the first chip, the peripheral components and a plurality of connecting ports via a bus of a multi-function IO interface architecture.

Description

1227836 V. Description of the invention (1) 1. [Technical field to which the invention belongs] The present invention relates to the connection of buses in the electrical system architecture using a computer system with a multiplexed I / O interface architecture, and particularly relates to a use Computer system architecture of PCI-EX pres S bus interface. I. [Other technologies] In current or conventional technologies, the data processing speed of the central processing unit (Centr «ai Pirocessing Unit, CPU) is much faster than this central processing unit and system memory (ie, random dynamic access memory, DRAM ) Of the bus data transmission speed, and the central processing unit must access the system memory at any time when processing the data, so to improve the overall computer system performance, you can improve the data transmission bus. In terms of the current general architecture, please refer to the first diagram of the internal architecture of the conventional computer system. As shown in the figure, the computer system architecture includes a central processing unit 1 1 that processes various information and data operations of the overall computer system. The processing unit 11 is connected to other peripherals through the first chip 12 and the system memory 13. This first chip 12 is in a north bridge in a general personal computer architecture, and the central processing unit η and the first chip 12 The first system bus 101 is called the front side bus. The first chip 12 is provided with a memory controller. The second system bus 1 0 2 is connected to the system § self-memory 1 3 'Currently, most of them are connected by 64-bit double data rate (Double Data Rate, DDR) bus. The system memory 1 3 is a double data rate memory module (Doub 1 e

Data Rate_Synchronous DRAM (DDR-SDRAM), the first chip 12 and the third system bus 1 103 are used to access the data to the graphics card module

1227836 V. Description of the invention (2) Group 1 4. The third system bus 1 03 is currently implemented by the Accelerated Graphic Port (AGP) bus. The green map acceleration port is the computer motherboard. One of the slots on the upper interface is specially designed for the graphics acceleration port graphics card. Its function is to transmit the image information between the central processing unit and the graphics card. The first chip 丨 2 is also connected to the second chip by the fourth system bus 1 0 4! 6. The fourth system bus 1 04 is currently implemented with peripheral component connection interface buses (Peripheral C0mp0nent interconnect, pci). The fourth system bus 1 0 4 not only connects the first chip 12 and the first. The two chips 16 are more expansion buses for various computer systems, such as sound cards and network cards. This first chip 16 is commonly used as a south bridge in the chipset, and it is controlled by the second chip 丨 6 to control various peripherals, such as a keyboard, a mouse U-side device 17, such as a disk controller 18 , Used to connect the hard disk controller string ^ control 15 and other peripheral storage devices, there are multiple types of connection cockroach 19, such as = = fu (senal port), parallel port (paraalUl serial bus (USB), etc.) P rt ): ¾ Taiyuan, this is the second diagram of the internal architecture of the computer system of conventional technology. This "memory controller" was moved from the first chip 12 to the center: "Single connection": the sixth system bus 1 06 is connected to the control system recording body 1 3, and is connected to the first processing unit of the central processing unit ii. 己 u body N 105 is connected to a frame for temporary storage of the piano. ) 21 »w ^ ^ ^ ^ The bus 105 currently uses 64-bit units. This is the fifth system. The frame register 2 is a ffl system. &Quot; Special input rate bus implementation ... ° 1 is for 黠 -θ 内 built into the motherboard of the computer. It is an additional option for the display chip early remittance / melon display card set 1 on the graphics acceleration port ^.

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V. Description of the invention (3) For many years, the mainstream technology standard for data transfer in the brain (peripheral component connection interface bus, PCI) has been in charge. The current computer system, which is costly for Intel-level PCI speed in the United States, has been improved to become the first, and the chip company will take the above thiM generati0n 1 / 〇, 3GI〇), = generation string, interface (

Streaming data transfer speed is expected to be faster than the highest speed of the second-generation serial interface: the second, which will improve the execution of various applications 1 technology (two 1) faster six conventional technology computer system internal architecture third audio =. Please read the third picture, 11 by the first chip-12 and the system memory 胄 13 :; = of which the central processing unit 107 is connected, this seventh system bus 107 is based on the seventh bus, the bus, Sun A τday > 4 α for group C DDR-SDRAM) sink SDRAM) ^ (Added the second to increase the system bandwidth without adding its own reference frequency. 5 ,,, and _ 5 memory system data bandwidth, and solve The problem of the transmission line between the central processing unit and the system and the slow implementation of the storage system in the conventional computer system. The first chip 12 and the second chip 16 are connected to the f-plane by the third generation. Eight system buses 108 are connected.

-The fourth diagram is the fourth schematic diagram of the internal architecture of a conventional computer system. The second is to move the §memory controller to the central processing unit 11 and use the current 9th series of dual-data-rate memory module or quad-band memory technology. 3 $ 排 109 connection system Memory 13, and the first chip 12 is also connected to the frame register 2 丨 by the tenth system bank of the memory module or quadruple bandwidth memory technology. Choose according to actual needs

1227836 V. Description of the invention ^ ----- One of the double data transfer rate memory module or quad bandwidth memory technology. The first chip 12 and the second chip 6 are also connected by the eighth system bus 108 of the third generation serial interface. The above is the current computer motherboard architecture. In order to improve the internal bus transmission speed of the current computer system architecture, the present invention uses a quadruple-bandwidth memory technology (QBM) and a third-generation serial interface with a multiplexing function. To improve overall transmission performance. Third, [invention content]

The present invention is a computer system with a multiplexed I / O interface structure. It is a central processing unit connected to an electrical system, a memory, and a connection bus between each peripheral and a chip set. A plurality of multiplexed I / O interface structures are used. Confluence achieves the purpose of multiplexing the internal bus of the computer system and increasing the transmission speed. The computer system includes: a central processing unit; a first chip, which is connected to the central processing unit by a front-end system bus; a system chronicle system that uses a multi-bandwidth memory architecture to converge Connected to the first and second body, a graphics card module is connected to the first chip by a sink having a multiplexed I / O interface structure, and a second chip is provided by a multiplexed I / O. The bus of the surface structure is connected to the first chip, and the second chip is connected to peripheral devices of system 1 and a plurality of connection bees. Electric month since

Regarding the detailed content and technology of the present invention, we will explain it in conjunction with the drawings as follows: [Embodiment] The computer has a processing structure. Please refer to the fifth figure. The first schematic diagram of the multiplexed I / O interface rack system of the present invention. The computer system architecture shown below includes

1227836 V. Description of the invention (5) Central processing unit 11 for computing various information and data of the body computer system, the central processing unit 11 borrows the first chip 12 and the system memory 13 and connects to other peripherals & the central processing unit 1 1 The first system bus 1 with the first chip 12 is implemented as a front-end system bus. A memory controller is provided in the first chip 12 to connect to the system memory. The present invention uses the first bus 5 1 Connected to the first system memory 1 3 a 'Is the first bus 5 2 Connected to the first system memory 1 3 b, this first bus 5 1 is compatible with the second bus 5 2 4-bit memory bus with double data transfer rate and a multi-bandwidth memory technology bus. This multi-bandwidth memory technology bus is based on 64 of the quad-band memory technology. The double-bit data transmission rate bus is used to implement the computer system described above. It is the motherboard bus transmission speed. The quad-band memory system is used between the memory 13 and the memory system to increase the transmission bandwidth of electrical data. Conditions for adding rates in the pass rate memory module Problem of increasing the transmission system between the memory system storage system processing unit and system memory slow execution. The memory components that require higher clock frequencies are designed to be high frequency, which makes it easy to implement data, achieves a high-speed, economical solution to the increasing processing shield in the system. 0 To improve the current general computer architecture, it is stated in the central processing unit The computer system with the system memory technology to increase the transmission bandwidth is a double improvement in the current architecture. It does not increase the data bandwidth of its own reference frequency, but solves the influence of the central line and the quadruple bandwidth memory in the conventional computer system. No technology is needed '. Therefore, this computer system also does not need the high-speed transmission design of the bus. It is a more efficient and scalable solution. The conflict between capacity and memory bandwidth.

1227836 V. Description of the invention (6) The principle of the technology structure of the quadruple bandwidth memory is that when the data to be processed is processed, the system memory (13a, 13b) is output through the first chip 12 rounds ^ to & middle ^ When the processing unit 11 is 1, it outputs at a transmission reference frequency, and uses a transistor as a switch to switch at a 90 degree phase shift output of the transmission reference frequency ^ of the current double data transmission rate bus. The phase and bit time of each transmission is divided, so that a valid data bit is inserted into the time that the previous data bit is not occupied, and it is doubled under the current double-rate two-frame transmission rate bus architecture. Purpose of the quadruple bandwidth memory architecture. In the computer system architecture shown in the fifth figure, the first chip 2 is connected to the graphics card module 53 via the bus 53 of the first multiplexing input / output interface structure. , Ple ;; 4e / ;; ^ generation I / O, 3G10) bus instead of the conventional graphics acceleration connection bee (AGP) bus' but still maintains the compatibility of the conventional graphics acceleration port bus, increasing the cost The flexibility of the invention. In addition, the second multiplexed output interface interface bus 54 is connected to the second chip. 6 f replaces the ^ ^ second peripheral component connection interface bus (p CI), which can achieve greater bandwidth and transmission speed. The purpose of "faster" also maintains the compatibility of the conventional peripheral component connection interface% bus, which must be adopted according to different. The buses 5 3 of the first multiplexed I / O interface structure and the buses of the second multiplexed I / O interface structure described above can be changed and used according to the motherboard design. I / O interface architecture bus, increasing multiple selectivity. The second chip 16 can also be connected to a multiplexed I / O interface bridge chip (3GI0 bridge chip) by using a bus of another multiplexed I / O interface structure (shown in Figure 7).

1227836 -----V. Description of the invention (7) This third-generation serial interface with the input and output function of the industrial machine is a confluence of the industrial and commercial value department, and it can solve the current problem. It is a bottleneck to accelerate the connection of peripheral ports with conventional peripheral components, which is because of the multiplexing function. It can be used on all kinds of interface cards and computer peripherals, and it can also exist in any of them. Because the chipset on the computer motherboard (such as edge: 1 ^, second chip 16, etc.) has a limited number of chip pins, if the number of pins is increased because it is connected every week, it will increase the cost and expand the bomb. If the third-generation serial interface of this multiplexing input / output function is used, the two pins can be used multiplexed, which makes the system expand and consider the cost factor. The flexibility of the positive angle increases and it has the advantage of cost savings. . & As shown in the second schematic diagram of FIG./ and FIG. 2, the second memory controller of the first embodiment of the fifth diagram may also be provided in the central processing unit 11, and as described above, it has a multi-bandwidth memory. The first bus 5 of the technology is connected to the system memory 13a, and the memory controller can be set to the body m 'at the same time, so that the second system memory 1 can borrow the memory technology with multiple bandwidths. The second bus bar 52 has = borrowed another multiplexed output to enter the daily film 12. The first chip 16 can also be a bridge chip (3GI0 bus connected to a multiplexed output agent. The seventh picture is the improvement of the invention) (the picture is shown in the seventh picture). Figure, with the central processing unit 丨 丨 Multi-bandwidth computer system, the second fish bar 5 1 is connected to the memory of the first system 丨 3 The first bus of the wide memory architecture, the third bus of the J bus 73 Connection brother-chip 12 is recorded with multi-bandwidth " · Xigong I / O interface structure of the bus, pivot register 21, and in addition to accelerate the port bus with graphics, but connected to the graphics card module 1 4 In place of Xi Youbai, the graphics port 1227836 is accelerated. 5. Description of the invention (8) The compatibility of the stream line can be used in multiple choices. The first chip 1 2 has a second multiplexed I / O interface structure bus 5 4 is connected to the second chip 16 'and a third multiplexed I / O interface structure has a separate third-generation serial interface bus 7 5 Connected to a multiplexer I / O interface bridge chip 70, this multiplexer I / O interface bridge chip 70 is set to provide more options for connecting peripheral devices, and has multiple expandability. The bus 5 3 of the first multiplexed I / O interface structure and the bus 5 4 of the second multiplexed I / O interface structure described above can be changed to use the current bus or have multiplexed I / O according to the motherboard design. Interface architecture bus, increasing multiple options. The above is a detailed description of an embodiment of a computer system with a multiplexed I / O interface structure according to the present invention. Each bus in the computer system uses a plurality of multi-bandwidth memory structures and a third-generation serial interface with a multiplexing function. Multiple selectivity, to achieve the purpose and effect of increasing the transmission bandwidth and expansion flexibility of the computer system. The above are only the preferred embodiments of the present invention, and it should not be used to limit the scope of the present invention. That is, all equal changes and modifications made in accordance with the scope of the patent application for the present invention should still fall within the scope of the patent of the present invention.

Page 13 1227836_ Brief description of the drawings [Simplified description of the drawings] The first diagram is the first diagram of the internal architecture of a conventional computer system; the second diagram is the second diagram of the internal architecture of a conventional computer system; the third diagram is a conventional diagram The third diagram of the internal architecture of a computer system; the fourth diagram is the fourth diagram of the internal architecture of a conventional computer system; the fifth diagram is the first diagram of a computer system with a multiplexed input / output interface architecture according to the present invention; the sixth diagram is This is a second schematic diagram of a computer system with a multiplexed input / output interface structure according to the present invention, and a seventh diagram is a third schematic diagram of a computer system with a multiplexed input / output interface structure according to the present invention. [Symbol description] Π-central processing unit; 12-first chip; 1 3-system memory; 1 3a-first system memory; 1 3b-second system memory; 1 4-graphics card module; 1 5-Peripheral component connection interface; 1 6-Second chip; 1 7-Peripheral device; 1 8-Disk controller; 1 9-Port; 1 (Π-First system bus; 1 0 2-Second System bus; 103-third system bus; 104-fourth system bus; 105-fifth system bus; 106-sixth system bus; 107-seventh System bus; 1 0-8th system bus; 10 9-9th system bus; 1 10-10th system bus; 1 Π-11th system bus; 2 1-frame temporarily Memory; 5 1-the first bus;

Page 14 1227836 Schematic description 5 2-Second bus; 5 3-Bus of the first multiplexed I / O interface structure 5 4-Bus of the second multiplexed I / O interface structure 7 〇-Multiplex output Input interface bridge chip; 7 3-third bus; 7 5-third multiplexed I / O interface architecture bus

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Claims (1)

1227836 6. Scope of patent application 1. A computer system with a multiplexed I / O interface structure, which includes at least a central processing unit; a first chip, which is connected to the central processing unit by a front-end system bus; a system memory, Is connected to the first chip by a bus with a multi-times bandwidth memory structure; a display card module is connected to the first chip by a bus with a first multiplexed I / O interface structure; and a second chip Is connected to the first chip by a bus of a second multiplexed input / output interface structure, and the second chip is connected to peripheral devices of the computer system and a plurality of ports; wherein the first multiplexed input / output interface structure The bus is switched between the third-generation I / O interface (3GI0) bus and the peripheral component bus (PCI bus). 2. The computer system with a multiplexed input / output interface structure as described in item 1 of the scope of the patent application, wherein the first chip is a north bridge chip and the second chip is a south bridge chip. 3. The computer system with a multiplexed I / O interface structure as described in item 1 of the scope of patent application, wherein the transmission bus of the system memory and the first chip is selectable from the quad-band memory (QBM) Architecture and a double data rate (DDR) bus. 4. The computer system with a multiplexed input / output interface structure as described in item 1 of the scope of patent application, wherein the first multiplexed input / output interface structure is selectively switched Page 16 1227836_ VI. Scope of patent application A graphics acceleration port (AGP) third-generation serial interface with bus and multiplex transmission functions. 5. The computer system with a multiplexed I / O interface structure described in item 1 of the scope of patent application, further includes a third multiplexed I / O interface structure bus connecting the first chip with a multiplexed I / O interface bridge chip. (3GI0 bridge chip) 0 6. —A computer system with a multiplexed I / O interface structure that includes at least a central processing unit; a first system memory that borrows the first bus with a multi-bandwidth memory architecture Connected to the central processing unit; a first chip connected to the central processing unit via a front-end system bus; a second system memory connected to the first via a second bus having a multi-bandwidth memory architecture A chip; a graphics card module connected to the first chip via a bus of a first multiplexed I / O interface structure; and a second chip connected to the first chip via a bus of a second multiplexed I / O interface structure The first chip, the second chip and peripheral devices connected to the computer system and a plurality of connections; wherein the bus of the first multiplexed I / O interface structure is in the third-generation output Interface (3GI0) as a switching element between the bus and the peripheral bus (PCI bus). 7. Multiplexed input / output interface structure as described in item 6 of the scope of patent application Page 17 1227836_ VI. Patent application computer system, wherein the first chip is a north bridge chip and the second chip is a south bridge chip. 8. The computer system with a multiplexed input / output interface structure as described in item 6 of the scope of the patent application, wherein the bus of the multiplexed input / output interface structure is a third-generation serial interface with a multiplexed transmission function. 9. The computer system with a multiplexed input / output interface structure as described in item 6 of the scope of the patent application, wherein the transmission bus of the first system memory and the central processing unit is selectable from the multi-bandwidth memory architecture Bus with double data rate. 10. The computer system having a multiplexed input / output interface structure as described in item 6 of the scope of patent application, wherein the transmission bus of the second system memory and the first chip is selectable from the multi-bandwidth memory Bus of architecture and double data rate. 11. The computer system with a multiplexed input / output interface structure as described in item 6 of the scope of the patent application, wherein the transmission bus of the display card module and the first chip is selected from the multiplexed input / output interface structure and a Graphics acceleration bus for ports. 1 2. The computer system with a multiplexed I / O interface structure as described in item 6 of the scope of the patent application, further comprising a third multiplexed I / O interface structure. The streamer connects the first chip to a multiplexed I / O interface bridge. Chip (3GI0 bridge chip). 1 3. —A computer system with a multiplexed I / O interface architecture, including at least: a central processing unit; a system memory, which is the first sink of a multi-times bandwidth memory architecture Page 18 1227836 VI. Patent application range The bus is connected to the central processing unit; a first chip is connected to the central processing unit by a front-end system bus; a frame register is used to borrow a multi-bandwidth memory A third bus connected to the first chip; a graphics card module connected to the first chip via a first multiplexed input / output interface bus; a second chip connected to the second multiplex The bus of the I / O interface structure is connected to the first chip, the second chip is connected to the peripheral devices of the computer system and a plurality of ports; and a multiplexed I / O interface bridge chip is connected to the third multiplexed I / O interface structure. The bus is connected to the first chip; the current bus structure is replaced by the bus of the multiplexed I / O interface structure to increase the transmission bandwidth in the computer system. 14. The computer system with the multiplexed input / output interface structure described in item 13 of the scope of patent application, wherein the first chip is a Northbridge chip. 1 5. The computer system of the multiplexed input / output interface structure as described in item 13 of the scope of the patent application, wherein the second chip is a south bridge chip. 16. The computer system with a multiplexed input / output interface structure as described in item 13 of the scope of the patent application, wherein the bus of the multiplexed input / output interface structure is a third generation Ning interface with a multiplexed transmission function. 1 7. The computer system with the multiplexed input / output interface structure as described in item 13 of the scope of the patent application, wherein the transmission bus of the system memory and the central processing unit is selectable from the multi-bandwidth memory architecture and Double the data transfer rate Page 19 1227836_ VI. Bus for patent application scope. 1 8. The computer system of the multiplexed input / output interface structure as described in item 13 of the scope of the patent application, wherein the transmission bus of the frame register and the first chip can select the multi-bandwidth memory Bus of architecture and double data rate. 19. The computer system with a multiplexed input / output interface structure as described in item 13 of the scope of patent application, wherein the transmission bus of the display card module and the first chip is selectable from the multiplexed input / output interface structure and A drawing accelerates the connection of the bus. 2 0. The computer system of the multiplexed input / output interface structure as described in item 13 of the scope of the patent application, wherein the transmission bus of the second chip and the first chip is selected from the multiplexed input / output interface structure and a peripheral. Bus for component connection interface. Page 20