TWI225690B - Dynamic random access memory cell array and method for fabricating contact - Google Patents

Abstract

A method for fabricating contact is provided. A plurality of semiconductor devices has been formed on a substrate. A conformal spacer material layer is formed on the substrate to cover the semiconductor devices. A plurality of material pillars is formed between the semiconductor devices to cover a portion of the semiconductor devices on the substrate. A dielectric layer is formed between the material pillars on the semiconductor devices. A top surface of the dielectric layer is lower than of the material pillars. A passivation layer is formed on the dielectric layer. The material pillars are removed for forming a plurality of contact openings. A portion of the spacer material la is exposed by the contact openings. The exposing portion of the spacer material layer is removed for exposing a portion of the substrate. A spacer is formed on the sidewalls of the semiconductor devices. A conductor layer is filled into the contact openings to form a plurality of contacts.

Description

1225690 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a semiconductor process, and more particularly to a semiconductor memory device and a contact window process. [Previous Technology] With the increasingly powerful functions of today's computer microprocessors (Micr 0 p r 0 c e s s 0 r), the programs and calculations performed by the software are becoming more and more huge. Therefore, the memory fabrication technology has become one of the important technologies in the semiconductor industry. Generally speaking, memory can be divided into volatile memory and non-volatile memory according to the type of data it stores. The dynamic random access memory (DRAM) is a kind of volatile memory, and its memory cell line is composed of a gold-oxide semiconductor transistor and a capacitor. The memory cells in the memory are connected to each other by a word line (w 〇rd 1 ine) and a bit line (bit 1 ine) which are electrically connected to the gate and source of the metal-oxide semiconductor transistor, respectively. . FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a bit line of a conventional random access memory. Please refer to FIG. 1. In the conventional bit line contact window process, a metal-oxide semiconductor 120 is formed on a substrate 100, and then a dielectric layer 108 is formed on the substrate 100. Then, An etch-back process is performed on the dielectric layer 108 to form an auto-aligned contact window opening 1 06 between the metal-oxide-semiconductor crystal 102 and the auto-aligned contact window @ 口 1 0 6 A conductive layer is filled in to form a contact window 1 1 2. In the above-mentioned DRAM bit line contact window manufacturing process, borophosphosilicate glass is usually selected as the dielectric layer 108, and the borophosphosilicate glass contains silicon oxide molecules. Moreover, the spacers 104 of the metal oxide semiconductor transistor 102 are located at

12337twf.ptd Page 7 1225690 V. Description of the invention (2) The material of the cap layer 1 1 8 on the gate 1 1 6 is usually silicon nitride. Because silicon nitride and stone oxide are etched at a similar rate, the dielectric layer 1 0 8 is formed to form an opening 10 6 at the same time that the spacer 1 0 4 and the cap layer 1 1 8 are also etched. The top angle of the gate electrode 1 1 6 is exposed by the destruction of the electrode, as indicated by A in FIG. 1. The exposed gate electrode 1 16 may cause a short circuit between it and the contact window 112, thereby causing the semiconductor element to fail. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for forming a bit line contact window, which can avoid a short circuit with a gate electrode to increase production yield. The invention proposes a dynamic random access memory cell (DRAM Cell) array 歹 U. An ilbDRAM cell array is arranged on a substrate and includes a plurality of DRAM cells, a spacer material layer, and a dielectric layer. , Protective layer, multiple bit line contact windows, multiple bit lines, and multiple character lines. Among them, the DR A M cell line is arranged on the substrate in an array of a plurality of rows and a plurality of columns. Each DRAM cell includes a metal-oxide semiconductor and a capacitor. Among them, the metal-oxide semiconductor transistor further includes a gate structure and a source / drain. The gate structure is arranged on the substrate, and the source / drain system is formed in the substrate on both sides of the gate structure. The capacitor is electrically connected to the metal-oxide semiconductor transistor through one of the source / drain electrodes in the substrate. In addition, each bit line is electrically coupled to another source / drain in the same row through its corresponding bit line contact window. Each word line is electrically coupled to the gate structure of the same row. The spacer material layer is arranged on the gate structure of the metal-oxide semiconductor transistor and covers the sidewall thereof. The material of the spacer material layer is, for example, silicon oxide. The dielectric layer is arranged in between

12337twf.ptd Page 8 1225690 V. Description of the invention (3) The barrier material layer, the protective layer is arranged on the dielectric layer, and the material of the protective layer is, for example, nitrided nitride, oxynitride or carbonized silicon. The material of the dielectric layer is, for example, borophosphosilicate glass. The bit line contact window is formed in the protective layer and the dielectric layer, and is connected to another electrical source of the corresponding source / drain in the substrate. The present invention also provides a method for forming a contact window. This method first provides a substrate on which a plurality of semiconductor elements have been formed, and each semiconductor element includes at least a stacked structure and a conductive region. A conformal spacer material layer is formed on the substrate to cover the semiconductor element. Next, a plurality of material pillars are formed on the spacer material layer between the stacked structures, and extend to cover part of the stacked structures. A dielectric layer is then formed on the substrate so that the upper surface of the dielectric layer is lower than the upper surface of the material pillars. A protective layer is formed on the dielectric layer, and the material layer is removed by using the protective layer as a mask to form a plurality of contact window openings. Then, a part of the spacer material layer exposed in the opening of the contact window is removed to form a spacer on the side walls of each stacked structure, and a part of the conductive area is exposed. Then, a conductive layer is filled in the opening of the contact window, and the gap wall of the stacked structure is covered to form a plurality of contact windows. In the method for forming a contact window opening of the present invention, a pillar of material is formed first, and then removed to form an opening. In a preferred embodiment of the present invention, the material of the spacer wall is, for example, oxidized stone, and the material of the material column is, for example, polycrystalline silicon. In the process of forming the opening of the contact window, the etching rate of polycrystalline silicon is higher than the etch rate of oxidized stone. Therefore, when the polycrystalline silicon layer is removed, the gap wall can be prevented from being damaged by the etching and the gate electrode is exposed. Top corner. So be able

12337twf.ptd Page 9 h to solve the conventional semiconductor In order to make the present invention easier to understand, a comparison is given below. % Pieces produce a short circuit between the contact window and the gate, and other purposes, features, and advantages can be a better embodiment, and in accordance with the accompanying drawings, γ is shown in detail. [Embodiment] Brother 2 Α to 2 J It is not intended to illustrate a cross-section of a manufacturing process of a preferred embodiment of the present invention. Please refer to FIG. 2A. First, US-200 is provided, and a plurality of semiconductor elements have been formed on the substrate 200, and each body element includes at least a stacked structure and a conductive region. In one embodiment of the present invention, the 'semiconductor element is, for example, a metal-oxide semiconductor transistor 2 02, and the stacked structure is, for example, a gate dielectric layer 2 1 4, a gate electrode 2 1 6, and a cap layer 2 1 8 Stacked gate structure 2 2 2. The material of the cap layer 2 1 8 is, for example, silicon nitride. The conductive region is, for example, a source / drain 2 2 0. Then, a spacer-shaped material layer 204 in the shape of a soldier is formed on the substrate 200, and is covered on the metal-oxide semiconductor transistor 202. Referring to FIG. 2B, a plurality of materials 枉 206 are formed on the barrier material layer 204 between the gate structures 2222, and extend to cover part of the gate structures 222. Among them, the material of the material pillar 206 and the material of the spacer material layer 204 have a relatively high etching selection ratio, for example, it is 100: 1. In this embodiment, the material of the f-forming material column 206 is, for example, polycrystalline silicon, and the method of forming the column is, for example, first depositing a polycrystalline layer on the spacer material layer 204 to cover it. It is patterned by, for example, a mask etching method to form a shape

1225690 V. Description of the invention (5) Column of material 206. The material of the spacer material layer 204 is silicon, and the formation method is, for example, thermal oxidation or chemical vapor deposition. Please refer to FIG. 2C to form a ray of 208 frost and even a spacer material layer 204. Among them, the dielectric is called 2.08; the material column 206 and the tester 2 π # +; The material of the tail layer ζ υ 8 is, for example, borophosphosilicate glass, and the formation method is, for example, chemical vapor phase Deposition method.图 According to FIG. 2D, a chemical mechanical polishing process is performed, and the dielectric layer 208 is removed to expose the material pillar 206. Only 208 on Mb, please perform a one-button engraving process with the dielectric layer 208, so that the upper surface is lower than the upper surface of the material pillar 206. In the 2F and 2G pictures, a protective layer 2 1 0 is formed on the dielectric 8 2 n 8 band & only 1 hemp, 'connected 1 ..., the first onc, ^ #; 丨 the power increase Z υ 8 Cover material column 206. Then perform a chemical mechanical polishing process or a money engraving process, move + remove the column ^ the protective layer 21G on the material column 2G6 to expose the material column, as shown in Figure ^. One of the materials of the tritium protective layer is different from the material of the partition wall 2 0 4a. In the embodiment, the material constituting the protective layer 2 1 0 is, for example, nitride f, silicon oxynitride, or boron carbide. The formation method is, for example, a chemical vapor deposition method. — After that, referring to the second figure, using the protective layer 2 10 as a hard mask, the material column 206 is removed by an etching process to form a contact window opening 2 丨}. Move the exposed spacer material layer 204 by j points in parallel to form the gate structure 2 2 2 gap J2 0 4a ′ and expose the source / drain electrode 22 in the substrate 200. Moreover, in the above-mentioned etching process, the etching rate of the partition wall 2 0 4 a is greater than that of the protective layer 2 10.凊 Referring to Figure 2I and Figure 2j, a conductive layer is formed in the opening of the contact window. Page 12337twf.ptd 1225690 V. Description of the invention (6) The layer 212 is connected to the exposed source / drawn from the protective layer 210 on. Among them, the material of the lightning guide is connected and covers the sub-electrical layer Z 1 Z, such as a county quilt. The chemical and mechanical polishing process is carried out by the calibrator. The conductive layer 212 is made on the female connector, to form a V-etchback protective layer 210. The corpse and the contact window 21 , As shown in Figure 2J. Since the opening point of the contact window opening 2 1 1 of the present invention is the method of forming the material column 206, the opening A 2 of the opening 211 is formed 211. In addition, in the present invention, the division of the contact window openings, such as 3 ^, is preferred. In the preferred embodiment, what is the effect of the partition wall 2 0 4 a is, for example, oxidized stone, and the blindness is 0. Η. ^ Α η shell layer 218 is different in silicon. Therefore, the exposed layer k is broken during the removal of the exposed part of the gap. The material of the material pillar 206 is, for example, polycrystalline silicon, and the polycrystalline silicon and silicon oxide have a high etching selection ratio, such as 丨 〇〇: 丨. Therefore, in the etching process of removing the polycrystalline silicon layer, the gap 2 can be avoided. 〇 牦 k is excessively engraved and the top angle of the gate electrode 2 1 6 is exposed, so the present invention can effectively solve the problem that the conventional semiconductor element generates a short circuit between the contact window and the gate electrode. 0 More particularly, the present invention A protective layer 2 10 is formed over the dielectric layer 2 0 8, and the protective layer 2 10 has a higher etching selectivity ratio to the spacer, so it can be avoided in the process of forming the spacer material layer 2 0 4 in the etching portion. , Causing damage to the protective layer 210. Therefore, the conductive layer 212 can be prevented from remaining on the upper surface of the protective layer 210, thereby preventing a short circuit between a bit line or a metal interconnect formed later. For example, the method for forming a contact window of the present invention can be applied to form a bit line contact window of a Dynamic Random Access Memory Cel (DRAM). The following methods will be used

12337twf.ptd Page 12 1225690 V. Description of the invention α) The D R A M formed is described in detail. FIG. 3 is a schematic diagram of a single-row circuit configuration of a dynamic random access memory cell array according to a preferred embodiment of the present invention. Referring to FIG. 3, the power source 2 2 4 is electrically coupled to the source / drain 22 i of the metal oxide semiconductor transistor 200 2. = Several lines 2 2 6 are electrically connected to the gate 2 16 of each metal oxide semiconductor transistor 2 0 2 in a single row, and the bit line 2 2 8 is connected to the metal oxide semiconductor transistor 2 0 2 Source / Waiji 2 2 0 electrical connection. ^ Αΐ ί 4- * 1 shows the two gold-oxygen semi-transistors 2 0 2 纴 1 99 in the same row in Figure 3. Please refer to FIG. 4, the metal-oxide semiconductor transistor 202 includes a gate electrode structure and a source / drain electrode 22. The gate structure 2 2 2 is composed of a gate dielectric layer: „and a cap layer 218, and is sequentially arranged at the base, and 炻? Η ^. The material of the cap layer 2 1 8 is, for example, Gasification is broken. And the source electrode // and the electrode 220 are formed in the base 200 on both sides of the gate structure 2 22. The partition wall 204a is disposed on the side wall of the gate structure 22 On the part of the gap wall 22 and the second layer of the gap wall material layer 2G4 arranged on the top cover layer 218 by etching, a dielectric layer is sequentially arranged and the frost bit line contact window 21 2 & It is formed between the gate structures 2 2 2 and 2 2 0 electrically; the gate structure 2 2 2 is connected to the source / drain m ice in the substrate 2 0 to form a bit. The material of the line contact window 212a is, for example, bit line 2 2 8 is disposed on the bit line contact window 2 2 ^ and passes through the bit line contact window 2 1 2 a to be electrically connected to the source / drain 2 2 〇 It is worth noting that in the structure of the above DRAM cell array, the gap

12337twf.ptd Page 13 1225690 V. Description of the invention (8) The material of the wall material layer 2 0 4 is different from that of the material column 2 06, and there is a higher etching selection ratio between the two. In addition, the material of the protective layer 2 10 and the material of the gap material layer 2 4 also have a higher etching selection ratio. Therefore, the above-mentioned DRAM cell array can be prevented from causing a short circuit between the bit lines 2 2 8 or between the gate 2 16 and the contact window 2 1 2 a due to improper process parameter control. Although the above description uses DRAM as an example for description, the present invention does not actually limit the scope of application of this method, and the present invention can also be applied to the method of forming contact windows of other components. Those skilled in the art must understand that as long as the contact window is formed by using the characteristics of the above method, it is the spirit of the present invention. In summary, the present invention utilizes the characteristics of different materials having different etching rates, and appropriately applies these materials to semiconductor elements to prevent over-etching and thereby improve production yield. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

12337twf.ptd Page 14 1225690 Brief Description of Drawings Figure 1 is a schematic cross-sectional view of the manufacturing process of the bit line contact window of the conventional dynamic random access memory. FIG. 2A to FIG. 2J are schematic cross-sectional views illustrating a manufacturing process of a contact window of a semiconductor device according to a preferred embodiment of the present invention. FIG. 3 is a schematic diagram showing a single-row circuit configuration of a DRAM cell array according to the present invention. FIG. 4 is a schematic cross-sectional view of two metal-oxide semiconductor transistors in the same row in FIG. 3. [Illustration of diagrammatic symbols] 1 00, 200: substrate 1 0 2, 2 0 2: metal-oxide semiconductor transistor 1 0 4, 2 0 4 a: partition wall 1 0 6, 2 1 1: contact window opening 1 08, 2 0 8: Dielectric layer 1 1 2: Bit line contact window 1 1 4, 2 1 4: Gate dielectric layer 1 1 6, 2 1 6: Gate electrode 1 1 8, 2 1 8: Cap layer 1 2 0, 2 2 0, 2 2 1: source / drain 1 2 2, 2 2 2: stacked structure 204 spacer material layer 206 material column 21 0 protective layer 2 12 conductive layer

12337twf.ptd Page 15 1225690 Brief description of the diagram 2 1 2 a: Contact window 2 2 4: Capacitor 2 2 6: Word line 2 2 8: Bit line Page 16 12337twf.ptd

Claims (1)

1225690 VI. Scope of patent application 1. A dynamic random access memory cell array disposed on a substrate. The dynamic random access memory cell array includes: a plurality of memory cells arranged on the substrate in an array of a plurality of rows and a plurality of columns. Each of the memory cells includes: a gold-oxygen semi-transistor including: a gate structure disposed on the substrate; and a source / inverter formed in the substrate on both sides of the gate structure; and A capacitor electrically coupled to one of the source / drain of the metal-oxide semiconductor transistor; a spacer material layer covering the gate structure and part of the substrate; a dielectric layer configured On the spacer material layer; a protective layer disposed on the dielectric layer, and the material of the protective layer and the dielectric layer is different; a bit line contact window penetrates the protective layer and the dielectric layer And is electrically coupled to another source / drain in the substrate; most bit lines, each bit line is in the same row as the corresponding bit line contact window The source / drain electrical couplings in the substrate ; Word line and a majority of bars, each of the word line and the plurality of gate structures is electrically coupled to the same column. 2. The dynamic random access memory cell array according to item 1 of the scope of patent application, wherein the material of the spacer material layer and the protective layer are different. 12337twf.ptd Page 17 1225690 6. Scope of patent application 3. The dynamic random access memory cell array described in item 2 of the patent application scope, wherein the material of the spacer material layer includes silicon oxide. 4. The dynamic random access memory cell array described in item 2 of the scope of patent application, wherein the material of the protective layer includes one of silicon nitride, silicon oxynitride, and boron carbide. 5. A method for forming a contact window, comprising: providing a substrate on which a plurality of semiconductor elements have been formed, each of which includes at least a stacked structure and a conductive region; forming a conformal shape on the substrate A spacer material layer covers the semiconductor elements. A plurality of material pillars are formed on the spacer material layer. The material pillars are located between the stacked structures and extend to cover part of the stacked structures. A dielectric layer is formed on the substrate, and the upper surface of the dielectric layer is lower than the upper surfaces of the material pillars; a protective layer is formed on the dielectric layer; the protective layer is used as a mask to remove the materials Pillars to form a plurality of contact window openings; removing an exposed portion of the spacer material layer in the contact window openings to form a spacer on the side walls of each of the stacked structures and exposing a portion of the conductive area; A conductive layer is filled in the contact window openings to form a plurality of contact windows. 6. The method for forming a contact window as described in item 5 of the scope of patent application, 12337twf.ptd Page 18 1225690 6. Method of applying for a patent The method for forming the dielectric layer includes: forming a dielectric material layer on the substrate to cover the spacer material layer and the material column, and performing a chemical mechanical polishing A process to remove the dielectric material layer on the material pillars; and an etch process to remove a portion of the dielectric material layer so that the upper surface of the dielectric material layer is lower than the Some material on the top surface. 7. The method for forming a contact window according to item 5 of the scope of patent application, wherein the method for forming the protective layer comprises: forming a protective material layer covering the dielectric layer and the material columns; and performing a chemical mechanical polishing process To remove the protective material layer on the material pillars. 8 · The method for forming a contact window as described in item 5 of the scope of patent application, wherein in the step of removing the material columns to form a contact window opening, the removal rate of the material columns is greater than the spacer material layer Removal rate. 9. The method for forming a contact window as described in item 8 of the scope of patent application, wherein the material of the material columns includes polycrystalline silicon. 10. The method for forming a contact window according to item 8 of the scope of the patent application, wherein the material of the spacer material layer includes silicon oxide. 11. The method for forming a contact window as described in item 5 of the scope of the patent application, wherein the material of the spacer material layer is different from the material of the protective layer. 1 2. The method for forming a contact window according to item 11 of the scope of patent application, wherein in the step of removing the exposed part of the spacer material layer in the openings of the contact windows, the removal of the spacer material layer Divide rate is greater than this protection 12337twf.ptd Page 19 1225690 12337twf.ptd Page 20