TWI225333B - Class D amplifier - Google Patents

Abstract

The invention provides a class-D amplifier capable of driving and controlling MOS transistor output power using no special circuit technology or electronic component. The signal generation circuit 301H of the class-D amplifier generates same phase signal H1 of modulated pulse signal and reverse phase signal H2 for output. While maintaining constant relation between signal level of same phase signal H1 and reverse phase signal H2, the signal conversion circuit 302H converts to same phase signal H3 and reverse phase signal H4. The same phase signal H3 and reverse phase signal H4 follow the source voltage VS of MOS transistor 401 for output power as standard voltage VR1. Besides, the driving circuit 303H takes source voltage VS as basis of internal power P12 to function and drive MOS transistor 401 for output power in accordance with relation of same phase signal H3 and reverse phase signal H. Likewise, the MOS transistor 402 for output power conducts complementary driving with respect to the MOS transistor 401 for output power.

Description

1225333 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a technology related to a class D amplifier (digital amplification) that converts an analog signal such as a music signal into a pulse signal and applies power amplification, and particularly relates to the use of Circuit technology to drive and control the power Mos transistor. [Prior art] It is known that there is a D-class amplifier that uses an analog signal such as a music signal as an input signal and converts it into a pulse signal to apply power amplification. The output terminal is a low-domain filter. Connected to the input terminal of the amplifier. According to this class D amplifier, the amplitude (data component) of the input signal is reflected by the pulse width and the pulse signal amplified by power is output. Moreover, the pulse ## is passed through a low-domain filter to extract an analogue amount of music signal amplified by electric power, and the music signal drives the player. Because the D-class amplifier can be formed on a silicon chip, it can realize a small and inexpensive design. It is often used in portable terminals or personal computers that require low power consumption. FIG. 12 shows an example of use of the configuration of the D-class amplifier 900. In the figure, the “仏” source SIG is a generation source of a music signal VIN using the ground potential (0v) as an analog of the amplitude midpoint, and it is an input capacitor that the DC component of the music signal is blocked by the intermediary ( (Not shown), and is connected to the input terminal TI of the D-class amplifier 900. The Class D amplifier 900 is a so-called PWM amplifier (PWM: Pulse Width Modulation), which is composed of an input section 901, a modulation circuit 902, a driving circuit 903, and n-type power MOS transistors 904 and 905. The input section 901 shifts the midpoint of the music signal VIN, and changes the audio signal 80426 into a waveform of the input characteristics of the modulation circuit 902 suitable for the operation of the power supply VDD (for example, 10 V). The modulation circuit 902 converts the music signal output from the input section 901 into a pulse signal, and reflects the information component of the music signal in a pulse width to perform PWM modulation. The driving circuit 903 drives the control output power MOS transistors 904 and 905 complementarily based on the pulse signal modulated by the modulation circuit 902. The power MOS transistor 904 is connected with a current path between the positive power source VPP + (for example, +50 V) and the output terminal TO, and is used to output a high level. In addition, the power MOS transistor 905 is connected with a current path between the negative power supply VPP- (for example, _50 V) and the output terminal TO, and is used to output a low level. The output terminal TO is connected to the input terminal of the SPK via a low-domain filter composed of an inductor L and a capacitor C. According to the class D amplifier 900, the music signal VIN input from the signal source SIG is converted into a pulse signal through the input section 901 and the modulation circuit 902. At this time, the modulation circuit 902 performs pulse width modulation on the carrier signal in accordance with the music signal VIN. The driving circuit 903 is based on the modulated pulse signal to complementarily turn on and control the power MOS transistors 904 and 905, and outputs a pulse signal amplified by electric power to the output terminal TO. The power-amplified pulse signal is supplied to the amplifier SPK by removing a carrier frequency component by a low-domain filter composed of an inductor L and a capacitor C, and forming an analog signal of a power amplification. However, the above-mentioned modulation circuit 902 operates with a single power source VDD (for example, 10V). Therefore, the low level of the pulse signal of the output signal forms the ground potential (0V) and the high level It is the 80426 1225333 voltage (10 V) supplied with the power supply VDD. Therefore, if a pulse signal with such a signal level is used as it is, the characteristics of the MOS transistor cannot fully control the power MOS transistor 904 connected to the positive power supply VPP + (+50 V) to ON. State, and the power MOS transistor 905 connected to the negative power source VPP- (-50V) cannot be controlled to the OFF state. Therefore, in the driving circuit 903, it is necessary to create a function for controlling the power MOS transistors 904 and 905 according to the pulse signal modulated by the modulation circuit 902. The driving circuit 903 will be described below. In order to control the conduction state of the power MOS transistor that outputs a signal that changes from the positive power supply VPP + to the negative power supply VPP-, although the self-driving circuit 903 supplies a pulse signal that can balance the positive power supply VPP + and the negative power supply VPP- to the power MOS The gates of the transistors 904 and 905 are sufficient, but a driving circuit 903 ′ composed of a high-withstand piezoelectric crystal must be used, resulting in an increase in cost. That's why. By separating (insulating) the power supply system that drives the circuits of the power MOS transistor 904 and the power MOS transistor 905 separately, the driving circuit is constructed by using a method that reduces the effective power supply voltage applied to each circuit. 903. In the example shown in FIG. 12, both of the power MOS transistors 904 and 905 are n-type, so the driving circuit 903 is a source voltage of the MOS transistor 904 with a success rate of separation, that is, the output signal appearing at the output terminal TO. The reference power supply system and the source voltage of the power MOS transistor 905, that is, the power supply system based on the voltage of the negative power supply VPP-. Therefore, the power supply system for driving the circuit of the power MOS transistor 904 changes in accordance with the voltage change of the output signal appearing at the output terminal TO. However, when the power supply system of the driving circuit 903 follows the output signal appearing at the output terminal TO in this way, the input level of the driving circuit 903 is critical relative to the signal level of the pulse signal output from the modulation circuit 902 on the front side. The value is in a fluctuating state, and the unsuitable situation in which the first pigeonhole method correctly transmits a signal from the modulation circuit 902 to the driving circuit 903 is generated. The first known technique to solve such uncomfortable situations is to use the technique of self-help ^^ l (b〇otstrap clrcu⑴) to boost the pulse number 仏 output by the modulation circuit to be suitable for the driving circuit. The signal level on the 903 side. In addition, as a second conventional technique, an insulated transformer is used to convert the pulse signal voltage output from the modulation unit 902 to a signal level suitable for the drive circuit side. Even as The third conventional technique is to use an optical coupler to modulate each of the 902 ports of the modulation circuit. The # signal is converted into an optical signal and transmitted to the 903 side of the drive circuit. It is based on the first conventional technique described above. The self-benefit circuit is used to change the level of the signal output from the modulation circuit, so there is a problem that the signal frequency becomes high and the operation is unstable. According to the above-mentioned second and third conventional techniques, the insulation transformer Electronic components such as or couplers have higher prices and increase costs. Moreover, 'the space for the installation of such electronic components must be determined, and the device must be constructed in the system'. Traditional power supply and operating structure It is assumed that the input section 90m, the modulation private circuit 902, and the drive circuit 903 are all ^ vpp, ^ E blocks are the positive electricity of the south voltage system, the original VPP +, and the negative power supply vppj. The signal structure is changed as described above to simplify the circuit configuration .... In this case, for all blocks of 80426 1225333, it is necessary to use a manufacturing technology capable of withstanding high voltages. Even if each block is assumed to be separate, The implementation of IC technology will also inevitably increase the manufacturing cost of each individual. The present invention was created in view of the above circumstances, in order to provide a power transistor that can drive and control output without using special private circuit technology or electronic components. In order to solve the above problems, the present invention has the following structure. That is, the invention described in item 丨 of the application scope The stage amplification is as follows: it has a first output transistor, which is connected between the positive power source and the output terminal: "between the current path a; a second output transistor, which is between the negative power source and the aforementioned output terminal. Connect the current path; reflect the information component of the signal input from the external input terminal and from outside # to the pulse width and modulate the signal into a pulse signal, and turn on the aforementioned first part complementaryly according to the pulse signal The first and second outputs are composed of transistors, and are characterized in that they include: a complementary signal generating electric $, which generates and outputs a complementary signal composed of an in-phase signal and an in-phase signal of the pulse signal; The signal conversion circuit transforms the first complementary signal into a second complementary signal while maintaining the magnitude relationship between the signal level of the in-phase signal and the signal level of the inverted signal. And the third complementary signal is a predetermined voltage that follows the source voltage of the first or second output transistor as a reference; the driving circuit is operated by an internal power source based on the source voltage, And input the second complementary signal and drive according to the signal component of the in-phase signal and the signal component of the inverting signal included in the 80426 -10- 1225333 second complementary signal. Operate the first or second output transistor. According to this configuration, the signal levels of the in-phase signal and the reverse-phase signal constituting the first complementary signal can be determined according to the signal level of the pulse signal output from the modulation circuit. For example, when the pulse signal is at a high level, the in-phase signal is at a high level and the inverting signal is at a low level. Conversely, if the pulse signal is at a low level, the in-phase signal is formed at a low level and the inverted signal is formed at a high level. That is, the signal level of the pulse signal output by the modulation circuit is converted into a combination of the signal levels of the in-phase signal and the inverse signal constituting the first complementary signal, and such in-phase signals are re-presented. And the magnitude of the inverted signal. Therefore, while maintaining this magnitude relationship as it is, each signal component of the in-phase signal and the reverse-phase signal is presented as a second complementary signal. The driving circuit controls the first or second output transistor based on the difference between the in-phase signal and the inverting signal constituting the second complementary signal. Therefore, even if the second complementary signal follows a predetermined voltage based on the source voltage of the first or second output transistor as a reference, the second complementary signal is included in the in-phase signal and the inverting signal included in the second complementary signal. The magnitude relationship of each component is maintained, so the signal level of the pulse signal output by the modulation circuit can be grasped from the magnitude relationship. Therefore, according to the present invention, it is not necessary to use a special manufacturing process or electronic components, that is, the pulse signal can be transmitted to the power supply system as a separate driving circuit, and the output transistor can be driven. The invention described in item 2 of the scope of patent application is the D-class amplifier described in item i of the scope of Shen Ertai's patent, which is characterized in that the conversion circuit 2 is provided with: a pair of first resistors, It is connected between a pair of output sections of the aforementioned signal conversion circuit which presents the aforementioned No. 11-80426 and a pair of input sections of the aforementioned drive circuit which presents the aforementioned second complementary signal; The second resistor has one input side connected to a pair of input portions of the driving circuit, and the bias circuit 'bias the other terminal side of the second resistor of the pair to the predetermined voltage. The application is called the invention described in item 3 of the patent library, which is a class D amplifier as described in item 2 of the scope of the patent application, and is characterized by: more: a capacitor /, which is used to repair JL parasitic The unbalanced state of the capacitance component on the signal path of the input pair of the driving circuit of the pair of input circuits of the aforementioned driving circuit is not mentioned separately. The invention described in item 4 of the application for patent is not a class D amplifier as described in item 2 or item 3 of the patent scope, which is further equipped with a current injection circuit which injects current into the circuit. The i-th resistor of the pair is used to eliminate the in-phase current flowing through the i-th resistor of the pair. The invention described in item 5 of the patent application is the D-class amplifier described in the fourth item of the scope of the application. The current injection is composed of the following: a current monitoring circuit that monitors the flow of electricity. The in-phase current of the first! Resistor. The current mirror circuit, its input is the current monitoring circuit monitored by the two monitors, the cloud, the shock, the ha, six, and k 1 dishes as "private, melon, and output the current equivalent to the current The Jth resistance of a pair. The present invention described in item 6 of Sit 'is a class D amplifier as described in Zhongyou 3, characterized in that the aforementioned bias circuit is composed of a dual output type operational amplifier, and the operational amplifier has, Inverting input section, which is connected to the other end of the second resistor; not 80426 -12-1225333 Inverting input section, which inputs the predetermined voltage; a pair of output sections, which are connected to the first One end of the second resistor pair. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. (Embodiment 1) Fig. 1 shows a configuration and a use example of a D-class amplifier DAMP according to the first embodiment. In the figure, the signal source SIG is a source of generating a music signal (analog quantity) with an analog quantity using the ground potential (0 V) as the midpoint of the amplitude. The input capacitor CIN is used to block the DC component. The supplied signal is an intermediate capacitor CIN, and is supplied as a music signal VIN to the input terminal TI of the D-class amplifier DAMP. The D-class amplifier DAMP is a so-called PWM amplifier. The input section 100, the modulation circuit 200, and the drive control circuit 300, n-type power MOS transistors 401, 402. Here, the input section 100 is equivalent to the input section 901 of the conventional technology, which is composed of an input resistor R1 and a feedback resistor R2 (= R1) and an inverting feedback type operational amplifier OP. One end of the input resistance R1 is connected to the inverting input section (-) of the operational amplifier OP, and the other end is connected to the input terminal TI. The feedback resistor R2 is connected between the inverting input section and the output section of the operational amplifier OP. A reference voltage VREF is applied to a non-inverting input section of the operational amplifier OP. Since the reference voltage VREF is generated by a voltage generating unit (not shown), it is generated by dividing the voltage with a standard power supply VDD, for example, and is set to 1/2 of the power supply VDD. The input section 100 thus constituted is an inverting amplifier with an amplification factor "1" -13-

80426 1225333 operates and outputs a signal that inverts the phase of the music signal VIN with the reference signal VREF as the midpoint. Accordingly, the music signal VIN input from the signal source SIG is converted into a signal suitable for the modulation circuit 200 on the rear stage side. In this embodiment, the power supply VDD voltage is made "+10 V" as a standard power supply voltage in the technical field. The modulation circuit 200 has the same structure as the modulation circuit 902 of the above-mentioned conventional technology. It converts the music signal output from the input section 100 of the previous stage into a pulse signal, and reflects the information component of the music signal to the pulse. Wide PWM modulation. In the following description, the PWM signal and the pulse signal output from the self-modulation circuit 200 are referred to as "PWM signals". The drive control circuit 300 is the inventor of the present invention. It drives the power MOS transistor 401 and the power MOS transistor 402 for control output in a complementary manner based on the PWM signal output from the modulation circuit 200. Although the driving control circuit 300 corresponds to the driving circuit 903 of the aforementioned conventional technology, its structural feature is that the PWM signals output by the self-modulation circuit 200 generate complementary signals (in-phase signals and inverted signals). According to the in-phase signal and the inverting signal constituting the complementary signal, the pair of power MOS transistors 401 and 402 can be driven and controlled complementarily. The details of the drive control circuit 300 are described later. The 0 power MOS transistor 401 is used to output Micro Motion at the output terminal TO, and its drain and source are connected to the positive power supply VPP + and the output terminal TO, respectively. The other power MOS transistor 402 is used for outputting a person who is located at the output terminal TO, whose drain and source are connected to the negative power supply VPP- and the output terminal TO, respectively. In the first embodiment, the voltage of the positive power source VPP + is made -14-

80426 1225333 The voltage of "+50 V" and negative power supply VPP- is made "-50 V". The output terminal TO is a low-domain filter composed of an inductor L and a capacitor C, and is connected to one input terminal of the sounder SPK, and the other input terminal of the sounder SPK is grounded. The constants of the low-domain filter composed of the inductor L and the capacitor C are set so that the carrier frequency component of the pulse signal output from the D-level amplifier DAMP can be removed from the intermediate output terminal TO, and can pass through the state of the music signal component. As described above, the D-class amplifier DAMP operates with three power sources: a standard power source VDD, a positive power source VPP +, and a negative power source VPP-. Next, the configuration of the drive control circuit 300 will be described in detail. FIG. 2 shows a configuration of the drive control circuit 300. In this figure, the same elements as those shown in FIG. 1 are assigned the same reference numerals. The structure of the drive control circuit 300 shown in FIG. 2 is provided with a complementary signal generating circuit 301H, a signal conversion circuit 302H, and a drive circuit 303H as a circuit system for driving one power MOS transistor 401 (hereinafter referred to as high Side drive), and a complementary signal generating circuit 301L, a signal conversion circuit 302L, and a drive circuit 303L are provided as a circuit system for driving the other power MOS transistor 402 (hereinafter referred to as low-side drive). The signal presented at the connection point of the drain terminals of the power MOS transistor 401 and the power MOS transistor 402 is output as the output signal OUT of the class D amplifier DAMP, and is output to the outside via the output terminal TO described above. First, the configuration of the high-side drive will be described in detail. The complementary signal generating circuit 301H generates an in-phase signal H1 and an inverting signal H2 from the PWM signal output by the above-mentioned modulation circuit 200.

80426 1225333 CMOS (Complementary Metal Oxide Semiconductot) buffers B11, B12 and inverting input type buffer (inverter) B13. Here, the input section of the buffer B11 is supplied with the PWM signal output from the modulation circuit 200, and its input section is connected in common to the input sections of the buffers B12 and B13. These buffers B11, B12, and B13 are operated by supplying power VDD, and output the in-phase signal H1 and the inverted signal H2 of the PWM signal from the buffers B12 and B13, respectively. These in-phase signals H1 and anti-trust signals H2 are output to the signal conversion circuit 302H as complementary signals (HI, H2). The signal conversion circuit 302H converts the in-phase signal H1 and the inverted signal H2 to a predetermined level and follows the source voltage VS of the power MOS transistor 401 (that is, the signal level of the output signal OUT) as a reference. The in-phase signal H3 and the inverting signal H4 of the voltage vr 1 are a pair of resistors ri2 (a pair of first resistors), a pair of resistors R13, R14 (a pair of second resistors), and The bias circuit P11 is configured. The non-inverting signal H3 and the inverting signal H4 are input to a pair of the comparator CM1 (the non-inverting input section and the inverting input section) which are supplied to the comparator CM1 constituting the driving circuit 303H on the rear side. Here, the buffers B12 and B13 presenting the in-phase signal H1 and the inverted signal H2. The pair of output sections and the pair of input sections of the comparator CM1 presenting the in-phase signal H3 and the inverting signal are connected to the pair of resistors R ^, R12. That is, one end of the resistor Ru is connected to the output of the buffer M, and the other end thereof is connected to the non-inverting input portion of the comparator 0] ^ 1. The-terminal of this = 'resistor R12 is connected to the output portion of the buffer Bn, and the other terminal thereof is connected to the inverting input portion of the comparator CM1. These resistors r ^, ri2 80426-16 form a line that generates a self-complementary signal generating circuit 301H for transmitting the in-phase signal HI and the inverted signal H2 to the driving circuit 303H. In addition, one pair of inputs of the comparator CM1 is connected to one end of a pair of resistors R13 and R14, and the other ends of the resistors R13 and R14 are biased to a power MOS by a bias circuit P11. The source voltage VS of the transistor 401 is a predetermined voltage VR1 based on the reference voltage. In the present embodiment, the predetermined voltage VR1 is set to a value (= VS + VDD / 2) in which one-half of the power source VDD is added to the source voltage VS. At this time, since the power source VDD is 10 V, the voltage of half of 5 V is added to the source voltage VS to form the predetermined voltage VR1. FIG. 3 shows a configuration example of the bias circuit P11. As shown in the figure, the bias circuit P11 is connected between the positive power supply VPP + and the node showing the above-mentioned source voltage VS (that is, the source of the power MOS transistor 401), followed by a resistor PR and Schottky II. The polar body PD is formed by connecting the Schottky diode PD and the stabilizing capacitor PC in parallel, and the voltage appearing at the connection point between the resistor PR and the Schottky diode PD is set to a predetermined voltage VR1. In the first embodiment, the barrier voltage of the Schottky diode PD is set to 5 V corresponding to one-half of the power source VDD (10 V). Based on this, the predetermined voltage VR1 described above is generated plus the power source VDD. 1/2 is the value of the source voltage VS (= VS + VDD / 2). Next, the structure of the driving circuit 303H will be described referring back to FIG. 2. The driving circuit 303H is a driver MOS transistor 401, which is composed of a comparator CM1, a buffer B14, and an internal power source P12. Here, the non-inverting input section of the comparator CM1 is connected to the output section of the buffer B 12 through the intermediate resistor R11, and the inverting input section is connected to the input section of the buffer B 13 through the intermediate resistor R12. In addition, the output part of the comparator CM1 is connected to the input part of the buffer 80426 -17-1225333 state B14, and the output part 0 of the buffer B14 is connected to the gate of the power MOS transistor 401. The internal power source P12 generates a voltage VD1 corresponding to the power source VDD based on the source voltage of the power MOS transistor 401 and 8 ', and basically has the same configuration as the bias circuit shown in FIG. 2 described above. Among them, the barrier voltage of the Schottky diode fa PD at this time is set to be equal to the voltage of the power supply vdd. This internal power source P12 generates a voltage VD1 corresponding to the power source VDD based on the source voltage vs. and supplies it to the above comparison < CM1 and the buffer B14 as the power source voltage. Therefore, the power supply system of the drive circuit 303H is the same as the source voltage vs. of the power MOS transistor 401 and changes as well as being equivalent to the comparator (^ 乂 丨 related to the buffer B14). The above is a description of the configuration of the high-side drive for driving the power transistor 401. Next, the configuration of the low-side drive for driving the power transistor 402 is described. The complementary signal generating circuit 301L, the signal conversion circuit 302L, and the driving circuit 303L constituting the low-side drive are respectively the mutual signal generating circuit 301H, the signal conversion circuit 302H, and the signal converting circuit 302H constituting the above-mentioned high-side drive. The driving circuit 303H has the same structure. That is, the complementary signal generating circuit 3〇 丨 L generates an inverted signal of the PWM signal output from the modulation circuit 2000 described above and the in-phase signal L2. Or, it is composed of buffers B21, B22, and B23, and such buffers correspond to the configurations of the complementary signal generating circuit 30m, which are respectively a positive logic input type and a negative logic input type, and the buffers are 80426 -18-B22 B23 and B23 are respectively a negative logic input type and a positive logic input type. In addition, the signal conversion circuit 302L is composed of resistors R21, R22, R23, R24, and a bias circuit P21, and these types correspond to The resistors R1, R12, R13, R14, and bias circuit P11 constituting the above-mentioned signal conversion circuit 302H. Among them, the bias circuit P21 generates one-half of the power supply VDD based on the negative power supply VPP- as a reference. Voltage VR2. The driving circuit 303L is composed of a comparator CM2, a buffer B24, and an internal power supply P22, and these types correspond to the comparator CM1, the buffer B14, and the internal power supply P12, respectively, which constitute the driving circuit 303H. Among them, the internal power source P22 generates a voltage VD2 corresponding to the power source VDD based on the source voltage of the power MOS transistor 402 (ie, the negative power source VPP-), and supplies it to the comparator CM2 and the buffer B24 as the power source voltage. Hereinafter, the operation of this embodiment will be described with reference to the waveform diagram shown in Fig. 4 and the drive control circuit 300 shown in Fig. 2. In Fig. 4, the PWM signal output by the self-modulation circuit 200 is the same as Phase signal H1 is the same phase It is presented using the waveform of the in-phase signal H1. First, the operation of the high-side drive will be described. The signal generating circuit 301H generates the same signal as the PWM signal in response to the PWM signal output from the aforementioned modulation circuit 200. Phase in-phase signal H1 and phase-inverted signal H2. Specifically, if the PWM signal is at a low level, a low level is output as an in-phase signal H1, and a high level is output as an inversion Signal H2. Conversely, if the PWM signal is at a high level, the high level is output as the in-phase signal H1, and the low level is output as the inverted signal H2. That is, the complementary signal 80426 -19-1225333 generating circuit 301H transforms the signal level of the PWM signal into a combination of the signal level of the in-phase signal H1 and the inverted signal H2, and re-presents the signal level of this type. Size relationship. In the waveform diagram shown in FIG. 4, in the initial state, the output of the modulation circuit 2000 is

The output PWM signal is a high level, and the complementary signal generating circuit 3 01H inputted thereto outputs a high level as an in-phase signal 111 and a low level as an inverted signal H2. Therefore, in the initial state, there is a level difference corresponding to the power supply VDD between the in-phase signal m and the reverse-phase signal H2, and the same confidence signal H1 is higher than the reverse-phase signal H2 by a voltage equivalent to the power supply VDD. The in-phase signal m and the inverting signal H2 output from the self-complementary signal generating circuit 3101H are the resistors rii and ri2 that constitute the signal conversion circuit 302H, and are supplied to the drive by the in-phase signal H3 and the inverting signal H4. Circuit 3031 side. At this time, the input part of the comparator CM1 constituting the driving circuit 303H is

The dielectric resistors R13 and R14 are connected to the bias circuit pu. Therefore, the #blaze level of the in-phase signal shows the voltage VR1 and the in-phase signal H1 generated by the bias circuit ρι through the resistors Ru and R13. The voltage obtained by dividing the potential difference between the voltages, and the reverse phase H4 represents a voltage obtained by dividing the potential difference between the voltage and the reverse phase signal H2 by the resistors R12 and Ri4. Therefore, the in-phase signal H3 and the inverting signal H4 # are given to the company, and you follow the voltage VR1 in a state of maintaining the magnitude relationship, and change. The comparator CM1 of the driving circuit 303H outputs a signal from the knock-in mountain m — the flat hybrid LM1 system according to the magnitude relationship between the in-phase signal H3 and the inverting signal H4. In the initial state, since the in-phase signal H3 is larger than the inverting signal H4, the bass bit is larger. Therefore, the comparator CM1 outputs the “level” and buffers its input.

J. Youhengpu B14 is based on the source of power MOS 80426 -20-1225333 transistor 401 and outputs a signal H5 with a signal level equivalent to the power supply VDD to its gate. Accordingly, the power MOS transistor 401 is turned on. As described later, the power MOS transistors 401 and 402 are controlled to be in a complementary conducting state. Therefore, when the power MOS transistor 401 is in the conducting state, the power MOS transistor 402 is in a non-conducting state, and the signal of the output signal OUT is output. The level (ie, the source voltage VS) rises to the power supply voltage of the positive power supply VPP +. t

At this time, the drive circuit 303H is supplied with the voltage VD1 based on the source voltage VS from the internal power supply P12, so the power supply system of the drive circuit 303H rises in accordance with the source voltage VS of the power MOS transistor 401. Therefore, the input threshold value of the comparator CM1 also rises at the same time as the source voltage VS, but the voltage VR1 generated by the bias circuit P11 also rises following the source voltage VS, so the in-phase signal H3 and the inverted signal H4 Each signal level is maintained in a state suitable for the input characteristics of the comparator CM1 constituting the driving circuit 303H, and the power MOS transistor 401 is maintained in an on state. In this state, the signal level of the signal H5 is in a state that is 1 part higher than the positive power supply VPP + voltage VD (= VDD). That is, the internal power supply P12 has the same structure as the internal power supply P11 shown in FIG. 3, so when the signal level of the output signal OUT rises to the positive power supply VPP +, the intermediary is equivalent to the capacitor of the stabilization capacitor PC and boosts the voltage. VD1, and bears the voltage, and the signal level of the signal H5 forms a state higher than the positive power supply VPP + by a voltage VD1 (= VDD). In this state, although the voltage VD1 is lower than the voltage of the positive power supply VPP + due to the presence of a resistance equivalent to the resistance PR shown in FIG. 3, because this amplifier has a higher frequency of the output signal OUT, The capacitor V of the capacitor PC is maintained at a voltage of 80426 -21-1225333, and the signal level of the signal H5 is maintained at a state higher than the positive power supply VPP +. In one low-side drive, a complementary signal generating circuit 301L that inputs a high-level PWM signal in an initial state outputs a low-level as an inverted signal L1 and outputs a high-level as an in-phase signal L2. Therefore, in the initial state, there is a level difference corresponding to the power supply VDD between the inverted signal L1 and the in-phase signal L2 due to the magnitude relationship, and the inverted signal L1 is substantially lower than the in-phase signal L2. The voltage portion of the power supply VDD. The inverted signal L1 and the same signal L2 outputted from the complementary signal generating circuit 301L are supplied to the drive circuit 303L side with the inverted signal L3 and the in-phase signal L4 via the resistors R21 and R22 constituting the signal conversion circuit 302L. At this time, the signal level of the inverted signal L3 is a voltage obtained by dividing the potential difference between the voltage VR2 generated by the bias circuit P21 and the inverted signal L1 through the resistors R21 and R23, and the same The signal level of the phase signal L4 is a voltage obtained by dividing the potential difference between the voltage VR2 and the in-phase signal L2 by the resistors R22 and R24. Therefore, the inverted signal L3 and the in-phase signal L4 follow the voltage VR2 and fall in a state of maintaining the magnitude relationship. In the initial state, the comparator CM2 of the driving circuit 303L outputs a low level because the inverted signal L3 has a lower signal level than the in-phase signal L4, and the buffer B24 inputted thereto has an equivalent The signal L5 of the signal level of the source voltage (VPP-) of the power MOS transistor 402 is output to its gate. Therefore, the power MOS transistor 402 is in a non-conducting state. At this time, the internal power supply P22 generates a voltage VD2 based on the negative power supply VPP-, so the power supply system of the driving circuit 303L is in a low state, and the input of the driving circuit 303L is -22-

The 80426 5s threshold is in a reduced state. However, because the voltage VR2 generated by the bias circuit p2 丨 also follows the source voltage of the power MOS transistor 401 and is in a reduced state, the respective levels of the inverted signal L3 and the in-phase signal L4 are formed. The signal level of the input characteristic of the comparator CM 1 suitable for constituting the driving circuit 303L is maintained, and the power MOS transistor 402 is maintained in a non-conducting state. Therefore, in the initial state, the power MOS transistor 401 is turned on, and the power transistor 402 is turned off, and a high level state capable of outputting a voltage equivalent to the positive power supply vpp + is formed. Output signal out. From such an initial state, at time ti shown in FIG. 4, when the pwM signal shifts to a low level, the in-phase signal 扪 forms a low level in response to this and the inverse k number H2 forms a high level. Therefore, the magnitude relationship between the in-phase signal H1 and the inverted signal η] is reversed. At time t2, the magnitude relationship between the in-phase signal H3 and the inverted signal H4 is also reversed. Therefore, the output signal of the comparator CM 1 that inputs the in-phase signal H3 and the inverting signal H4 is changed from a high level (higher voltage state than the positive power supply vpp + higher than the voltage VD) to a low level (equivalent to the positive power supply VPP + Voltage state), and the output signal H5 of the buffer b14 to which it is input also changes to a low level (equivalent to the voltage state of the positive power supply VPP +). As a result, the gate voltage of the power MOS transistor 401 is equal to the source voltage vs (= positive power supply VPP +), and the power transistor 401 is in a non-conducting state. On the other hand, at time t1, when the PWM signal shifts to a low level, the inversion signal L1 forms a high level and the in-phase signal L2 forms a low level in response to this. Therefore, the magnitude relationship between the inverted signal L1 and the in-phase signal L2 is reversed, and the magnitude relationship between the inverted signal L3 and the in-phase signal L4 is reversed in response thereto. For this reason, the output signal of the comparative CM2 is changed from a low level (equivalent to the voltage state of the negative power supply 80426 -23-1225333 VPP-) to a high level (higher voltage state than the negative power supply VPP- higher than the voltage VD2) The output signal L5 of the input buffer B24 is also changed to a high level. As a result, the gate voltage of the power MOS transistor 402 is higher than the source voltage by VD2, and the power MOS transistor 402 is A conduction state is formed. When the power MOS transistor 402 is turned on, the source voltage VS of the power MOS transistor 401 decreases with the output signal OUT. Based on this, the voltage VD1 generated by the internal power source P12 also decreases. At this time, the voltage VR1 generated by the bias circuit P11 also decreases with the change of the source voltage VS of the power MOS transistor 401, so the magnitude relationship between the in-phase signal H1 and the inverting signal H2 remains the same, and so on The signal level drops with the power supply system of the driving circuit 303H. Therefore, the level of the signal output from the comparator CM1 is maintained at a low level (source voltage VS). Accordingly, the power MOS transistor 401 remains in a non-conductive state while the output signal OUT is shifted to a low level (negative power supply VPP-). Due to the above situation, when the PWM signal transitions to a low level from the initial state at time t1, one power MOS transistor 401 is in a non-conducting state, and the other power MOS transistor 402 is in a conducting state, and The output signal OUT is migrated from the positive power supply VPP + to the negative power supply VPP- and outputs a low level. Next, at time t3, when the PWM signal returns to the high level, in response to this, at time t4, the in-phase signal H3 on the high-side drive side forms a high level and the inverting signal H4 forms a low level. Therefore, the comparator CM1 that inputs such in-phase signal H3 and inverted signal H4 outputs a high level, and the power MOS transistor -24- a

80426 1225333 The body 401 is in a conducting state. On the low-side drive side, the inverted signal forms a low level and the in-phase signal L4 forms a high level. Therefore, the comparator CM2, which inputs such an inverted signal L3 and an in-phase signal L4, outputs a low level, and the power MOS transistor 402 is in a non-conducting state. Therefore, when the power MOS transistor 401 is turned on, its source voltage vs. rises with the output signal οτ, and based on this, the voltage VD1 generated by the internal power supply pi2 also rises. However, the voltage VR1 generated by the bias circuit pii also increases following the source voltage vS and maintains the magnitude relationship between the in-phase signal η 1 and the inverting signal Η2. Therefore, the signal accuracy of the output signal output by the comparator CM1 The bit system maintains a high level (a voltage state where the source voltage VS is higher than the voltage VD by 1). Therefore, during the transition of the output signal OUT to a high level, the power MOS transistor 401 maintains an on state. Therefore, when the P WM signal forms a high level at time t3, the power M0S transistor 401 forms a conducting state, and the power m0s transistor 402 forms a non-conducting state, and outputs a high level equivalent to the positive power source VPP + As the output signal OUT, the respective signal levels of the in-phase signal H3 and the inverting signal H4 on the high-side drive side can be obtained by the following formula. (High level of in-phase signal H3) = [Rll {(VPP +) + VRl} + R13 X VDD] / (Rll + R13) (Low level of in-phase signal H3) = [R1 {(VPP +) + yR1 } + R13 X 0] / (R11 + R13) (high level of the inverted signal H4) = [R12 {(VPP +) + VRi} + R14X VDD] / (R12 + R14) -25-

80426 (Low level of inverted signal H4) = [R12 {(VPP +) + VR1} + R14 X 0] / (R12 + R14) Similarly, each of the inverted signal L3 and the in-phase signal L4 on the low-side drive side The signal level can also be obtained by the following formula. (High level of inverted signal L3) = [R21 {(VPP-) + VR2} + R23 X VDD] / (R21 + R23) (Low level of inverted signal L3) = [R21 {(VPP-) + VR2} + R23 X 0] / (R21 + R23) (high level of in-phase signal L4) = [R22 {(VPP-) + VR2} + R23 X VDD] / (R22 + R24) (in-phase signal Low level of L4) = [R22 {(VPP-) + VR2} + R23 X 0] / (R22 + R24) As described above, the first embodiment will be described. According to this embodiment, the output signal of the modulation circuit 200 can be converted into a signal level suitable for a power Mos transistor without using special circuit technology or electronic components'. Therefore, the power supply VDD can be used to operate the input stage 100 or the conversion circuit 200 to form a circuit, and the use of a high withstand voltage process can be suppressed to the minimum required. In addition, since the signal level is converted using a resistor, the complexity of the circuit configuration can be suppressed to the minimum required, and the cost can be effectively suppressed. (Embodiment 2) Next, Embodiment 2 of the present invention will be described. In the first embodiment described above, no consideration is given to the capacitance on the signal path 80426 -26-1225333 which is parasitic on the in-phase signal and the inverting signal generated by the complementary signal generating channels 301H and 301L, but actually exists. Various electric capacity. When the parasitic capacitance f forms an unbalanced state with respect to the in-phase signal and the reverse-phase signal, the amplitudes of the in-phase signal and the reverse-phase signal become smaller, and there is a problem that the relationship between the levels of such signal levels causes the opposite. In addition, when the parasitic capacitance is too large, for example, the in-phase signal H3 and the inverting signal H4 input to the driving circuit 30H, that is, the source voltage vs. which is equivalent to the ground of the driving circuit is lower, and There is a problem that the comparator CM 1 becomes inoperable. Fig. 6 (a) shows waveform examples of the in-phase signal H3 and the reverse-phase signal H4 when there is no unbalanced state of parasitic capacitance on the signal path. Fig. 6 (b) shows an example of a waveform when an unbalanced state exists between each signal path and a node exhibiting the source voltage VS. This waveform example is the capacitance between the signal path of the in-phase signal H3 and the node showing the source voltage VS, which is larger than the signal path of the reverse-phase signal H4. Fig. 6 (c) shows an example of a waveform when the parasitic capacitance between each signal path and a fixed node such as a ground is too large. This type of waveform example corresponds to the waveform when the amplified output signal OUT rises from a low level to a high level in FIG. 4 described above. When the capacitance parasitic on the signal path of the in-phase signal H3 and the inverting signal H4 is not in an unbalanced state, as shown in FIG. 6 (a), the in-phase signal H3 and the inverting signal H4, when at time η When the signal level is established, the magnitude relationship is maintained and it rises following the output signal OUT. Therefore, the input car driver CM1 has no error operation, and maintains the signal level corresponding to the magnitude relationship between the in-phase signal H3 and the anti-phase signal H4 determined at time t4. In contrast, when there is an unbalanced state of the parasitic capacitances connected in parallel to the resistors R11 and R12, as shown in FIG. 6 (b), the parasitic capacitances are received during the change process of the signals HI and H2 80426 -27- The non-fu stealing and non-weighing shirt sounds, but there is a magnitude relationship between the in-phase signal H3 and the inverse k1 H4, that is, ^ τ 1 inverted b-shape. When the magnitude relationship between the in-phase signal Η3 and the inverse 1: is reversed, the 'comparator' will malfunction. Yes, there is a case where the transistor 4G1 is temporarily turned off. Similarly, when the capacitance of the resistor R2im parasitic on the low-side driving side is unbalanced, the comparator ⑽ may malfunction. H3: 1: When the generating capacity is too large, as shown in Figure 6⑷, the signal level of the in-phase signal == cannot follow the output of the time signal 输 (that is, the source electrode) and has a relatively high output. When the signal υτ is low. Therefore, it is impossible to satisfy the input characteristic of the ratio M1 based on the voltage VD1 with the source voltage VS A and its best AA + ra: b as the base voltage, and the comparator cM1 malfunctions. Therefore, in this actual state 2, in the above-mentioned implementation ㈣m configuration, a pair of output nodes that are 1U positive from the L-number conversion circuit reach the capacitance component parasitic on the signal path of the node of the drive circuit. Unbalanced capacitor. Fig. 5 shows an example in which correction capacitors CU, ⑴ < are provided on the high-side drive side. As shown in this riding example, a correction capacitor CU is connected between the non-inverting input_ of the car CM1 connected to the signal path of the rib 3 and the node showing the source voltage π '. Further, a capacitor c 14 for correction is connected between the inverting input section of the comparator CM1 connected to the signal path of the inverting signal H4 and a node showing the source voltage £ VS. The value of capacitor C14 is set to be substantially equal to the capacitance of each signal path connected to the in-phase signal and the inverting signal H4. Accordingly, the amount of voltage variation in each signal path due to the reversion of the output signal becomes slightly equal, 80426 -28-, and the magnitude relationship between the in-phase signal H3 and the inverting signal H4 can be maintained. In addition, if the capacitors C13 and C14 are set sufficiently large with respect to the capacitance parasitic between each signal path and a fixed node such as ground, the output signal out is an intermediate capacitor when the signal level of the output signal OUT changes. C13 and C14 pull up the in-phase signal H3 and the inverting signal H4 to make it higher than the output signal OUT. Accordingly, the in-phase signal H3 and the inverting signal H4 satisfy the input characteristics of the comparator CM1, and the situation in which the comparator cmi does not operate can be avoided. In addition, in the example shown in FIG. 5, the resistors r1] L and R12 are connected to the capacitors C 11 and C 12 respectively, and accordingly, the in-phase signal H1 and the inverted signal H2 output from the buffers b 12 and B 13 The bit change is quickly transmitted to the comparator CM1 side, and the signal delay caused by the resistors R11 and r12 can be improved. Next, an example of each setting value of the capacitor and the resistance shown in FIG. 5 will be described. In addition, in FIG. 5, for convenience of explanation, the capacitance values corresponding to the respective capacitors and the resistance values corresponding to the respective resistors are prepared. When the parasitic capacitance is in an unbalanced state, if R1 丨: R13 = C13: C11, R12: R14 = C14: C12, the matching impedance for DC characteristics (static operation characteristics) and AC characteristics (dynamic motion characteristics) That is complete, and a waveform without over shoot can be obtained. Among them, ci4: C12 = C13: C11. For example, when R11 = R12 = 1001 ^ Ω and Rl3 = R14 = 5k ^, C11 = C12 = 1PF 'Cl3 = C14 = 2 pF. In this state, when the source voltage VS (ie, the output signal ουτ) of the high-side drive changes, the in-phase signal Η3 and the inverting signal Η4 follow the source voltage ^^ and satisfy the input of the comparator CM1 characteristic. 80426 -29- 1225333 In contrast, when there is an unbalanced state in the parasites, the magnitude relationship between the in-phase signal and the anti-phase signal is reversed as described above, which causes the malfunction. Therefore, in order to eliminate the unbalance of the parasitic capacitance, the capacitances C13 and C14 of the high-side driving side are made unbalanced. For example, when creating a button = R12 = 100 kQ, R13 = R14 = 5 buckle, cu = ci2 =] pF, then C = 18 pF, C14 = 12 pF. According to this, the operating limit can be obtained, and even if there is an imbalance in the parasitic capacitance, it can be prevented from being caused by the imbalance.

And cause malfunction. Fig. 6 shows an example of a waveform when the capacitances C13 and C14 on the high-side driving side are set to be unbalanced and the capacitance value is corrected. This example shows that during the transition of the output signal OUT, the difference between the signal levels of the in-phase signal H3 and the in-phase signal H4 is amplified. Therefore, the signal levels of the in-phase signal H3 and the in-phase signal H4 are not reversed, and the comparator CM1 inputting such signals does not malfunction. As described above, the second embodiment is described. (Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described. In the third embodiment, in the second embodiment, the high-speed is achieved by eliminating the in-phase current flowing through the resistors R11 and R12 on the high-side drive side and the resistors R21 and R22 on the low-side drive side. Here, referring to FIG. 7, the resistors Rii and R12 are taken as examples to explain the in-phase current generating mechanism and the problems caused by the in-phase current. FIG. 7 shows the signal paths from the buffers bi2 and B13 of the complementary signal generating circuit 3111 to the comparator CM1 of the driving circuit 303H in FIG. 2 described above, and the same components as those shown in FIG. 2 are given the same symbol. 80426 -30- In Fig. 7, when the source voltage vs. increases following the output signal, the voltage VR1 generated by the bias circuit P11 also increases based on this. Therefore, the voltage of the output node of the bias circuit pii is higher than the # mark output by the buffers B12 and B13, and the self-bias circuit P11 faces the buffers b12 and bi3 to pass through the same-phase current 11, respectively. 12 in resistance ri 1, R12. Therefore, the signal levels of the in-phase signal H3 and the inverted signal H4 are somewhat lower than the voltage VR1 generated by the bias circuit ρι. On the other hand, when the source voltage vs decreases following the output signal out, the voltage VR1 generated by the bias circuit P11 also decreases based on this. In this case, in-phase currents Π, 12 flowing in the opposite direction from the buffers b 12, b 13 toward the bias circuit P11 are in the resistors R11, R12. Therefore, the signal levels of the in-phase signal H3 and the inverted signal H4 are somewhat higher than the voltage VR1 generated by the bias circuit P11. If the R11 / R13 ratio is set to be small, the difference between the in-phase signal H3 and the inverting signal H4 can be increased, and the speed can be increased. However, as described above, the signal levels of the in-phase signal H3 and the inverting signal H4 change the voltage VR1 up and down according to the change of the output signal OUT, so that the in-phase signal H3 and the inverting signal H4 can not exceed The non-inverting input range of the comparator CM1 must set the ratios of R11 / R13, R12 / R14. Therefore, the R11 / R13 ratio cannot be arbitrarily reduced, and the difference between the in-phase signal H3 and the inverting signal H4 input to the comparator CM1 cannot be fully obtained, which affects the comparator CM1 which is input thereto. Response speed. In the third embodiment, by eliminating the above-mentioned in-phase currents II and 12, only the current flowing through the resistors R13 and R14 is made into an inverted current (based on the current component of the difference between the in-phase signal and the inverted signal). , And suppress the input change of comparator CM1 80426 -31-. According to this, the R11 / R13 ratio can be reduced, and the response speed of the comparator can be improved. Hereinafter, the configuration of the third embodiment will be described in detail. Fig. 8 is a diagram showing a characteristic of the structure of a class D amplifier according to the third embodiment. In this figure, the same components as those shown in Fig. 2 of the first embodiment are given the same reference numerals. FIG. 8 shows the structure of the high-side drive side. In the structure shown in FIG. 8, it further includes buffers BD12, BD13, resistors RD11, RD12, NMOS transistors Nil ~ N14, PMOS transistors P11 ~ P14, and so on. It is a current injection circuit for injecting a current for eliminating the above-mentioned in-phase currents II and 12 into the resistors R11 and R12. Here, the buffers BD12 and BD13 are analog buffers corresponding to the above-mentioned buffers B12 and B13. As described later, the voltages corresponding to the voltage VR1 are in the range of the NMOS transistor N14 and the PMOS transistor P14. Those driving the resistors RD11 and RD12, and a voltage VREFC corresponding to a voltage equal to one-half of the power source VDD is commonly applied to the input portion of this type. The resistors RD11 and RD12 have the same resistance value as the resistors R11 and R12. The resistor RD11 is connected between the output node of the buffer BD12 and the node of the NMOS transistor N14. The resistor RD12 is connected to the output node of the buffer BD13 and PMOS transistor P14. The NMOS transistor N14 sets the current flowing through the resistor RD 11 and sets its gate voltage VRP1 so that its source voltage can be equal to the above-mentioned voltage VR1. The PMOS transistor P14 sets the current flowing through the resistor RD12 and sets its gate voltage VRN1 so that its source voltage can be equal to the above-mentioned voltage VR1. 80426 -32- In addition, the source of PMOS transistor P11 is supplied with voltage VD1, and its drain and gate are connected to the drain of NMOS transistor N14. The source of the PMOS transistors P12 and P13 is supplied with a voltage VD1, and such an anode is connected to the inverting input section and the non-inverting input section of the comparator CM1, respectively. These PMOS transistors P11, P12, and P13 constitute a current mirror that monitors the current flowing through the resistor RD11 and injects current into the resistors R11 and R12. In FIG. 8, the voltage VR1 is the same as the voltage VR1 in FIG. 2, and is the voltage based on the source voltage VS, and the voltage VD1 is also the same. Therefore, the potentials of the gate voltages VRP1 and VRN1 are also supplied based on the source voltage VS. Similarly, the source of the NMOS transistor Nil is supplied with a voltage VS, and its anode and gate are connected to the drain of the PMOS transistor P14. The source of the NMOS transistors N12 and N13 is supplied with a voltage VS, and such a drain is connected to the inverting input section and the non-inverting input section of the comparator CM1, respectively. These NMOS transistors Nil, N12, and N13 form a current mirror that monitors and flows through the resistor RD12 and injects current into the resistors R11 and R12. Hereinafter, the third embodiment will be described starting with the above-mentioned current injection circuit. According to the above configuration, the voltage HD3 between the resistor RD11 corresponding to the resistor R11 and the source of the NMOS transistor N14, and the signal HD4 appearing at the connection point between the resistor RD12 corresponding to the resistor R12 and the source of the PMOS transistor P14. The voltage is roughly equal to the voltage VR1, and the output signal OUT is reciprocated between the positive power source VPP + and the negative power source VPP-. Therefore, when the output signal OUT is the positive power supply VPP +, the current IP11 flowing through the PMOS transistor P11 is expressed by the following formula. IP11 = {(VPP +) + VR1 — VREFC} / RD11 80426 -33-1225333 In addition, when the output signal OUT is VPP-, the current IN11 flowing through the NMOS transistor Nil is expressed as follows. IN11 = {VREFC — (VPP-)-VR1} / RD12 This type of current IP11, IN11 is roughly equal to the in-phase currents II, 12 flowing through the resistors Rll, R12, and forms a current that monitors this type of in-phase current. Among them, the current corresponding to the current IP11, and the PMOS transistor P11 are injected into the resistors R11 and R12 from the PMOS transistors P12 and P13 constituting the current mirror. In addition, a current corresponding to the current INI 1 and the NMOS transistor N11 are injected into the resistors R11 and R12 from the NMOS transistors N12 and N13 constituting a current mirror. As a result, the in-phase currents II and 12 flowing through the resistors R1 and R12 can be eliminated. On a large scale, the in-phase currents II and 12 do not exist in the resistors R13 and R14, and only the reverse-phase current is formed. Therefore, due to the decrease of the voltage based on the inversion current, the in-phase signal H3 and the inversion signal H4 are centered on the voltage VR1, and the in-phase input range of the driving circuit 3 0 3 比 is lower than that of the driver ’s benefit C1. According to the third embodiment, the in-phase current flowing through the resistors R13 and R14 can be eliminated, and the current flowing through such a resistor becomes smaller, so that the values of the resistors R13 and R14 can be set larger. As a result, the difference (differential potential difference) in the input signal of the comparator CM1 can be increased, which can increase the speed, stabilize the circuit operation, and improve reliability. In addition, because the input signal of the comparator CM1 can be increased in the state where the in-phase input range is small, the positive power supply VPP + and the negative power supply VPP- can be further increased, and it can correspond to the large output of the class D amplifier. Into. (Embodiment 4) Hereinafter, Embodiment 4 will be described. -34- 80426 1225333 The third embodiment described above is the one that monitors the current flowing through the resistors RD11 and RD12 to inject current, and biases the resistors R13 and R14 to the resistor VR1 by the bias circuit P11, but this embodiment 4 uses an operational amplifier to simultaneously bias the resistors R13 and R14 into a resistor VR1 while performing current injection. FIG. 9 is a diagram showing the configuration of a class D amplifier according to the fourth embodiment. In the fourth embodiment, in the configuration of the first embodiment shown in Fig. 2 described above, a two-output type operational amplifier OP60 having a pair of output sections 01 and 02 is used as a bias circuit. Here, its inverting input section is connected to a common connection terminal, and its non-inverting input section is applied with a voltage VR1, and its pair of output sections are respectively connected to the other ends of a pair of resistors R13 and R14. FIG. 10 shows the configuration of the operational amplifier OP60. In this figure, the constant current sources SI1, PMOS transistors P20, P21, and NMOS transistors N20 and N21 form a differential amplifier, and the output is connected to the gates of NMOS transistors N22 and N23. In the NMOS transistors N22 and N23, the drains of the NMOS transistors N22 and N23 are supplied with a voltage VD1, and the source of the transistors is supplied with a source voltage VS. The drains of these NM0S transistors N22 and N23 form a pair of output sections. According to the configuration of the operational amplifier OP60, a current is output to a pair of output sections 01 and 02 in response to a differential potential difference applied to the gates of the PM0S transistors P20 and P21. Here, returning to the description of FIG. 9 and describing the operation of the fourth embodiment. The output signal OUT shown in FIG. 2 is a voltage state corresponding to the voltage of the power supply VPP +. When the drive circuit 303H on the high-side drive side is the power supply VPP + side, the potentials of the in-phase signal H3 and the reverse-phase signal H4 shown in FIG. 9 It is reduced by in-phase electricity -35- 80426 1225333 currents II and 12, but because the reference voltage applied to the inverting input section of the operational amplifier OP60 is voltage VR1, the operational amplifier OP60 injects in-phase current from a pair of output sections. With the resistors R11 and R12, the voltage of the node Q is equal to the voltage VR1, and when the voltage of the node Q is equal to the voltage VR1, the output current of the operational amplifier OP60 is stable. When the output signal OUT is on the VPP- side, the voltages of the in-phase signal H3 and the inverting signal H4 rise due to the in-phase current, but the OP60 system injects the in-phase current into the resistors Rll and R12 to make the voltage at the node Q equal to the voltage VR1. . Based on this, the resistors R13 and R14 are formed like a reverse-phase current. The in-phase signal H3 and the reverse-phase signal H4 are differentially input for comparison based on the potential effect of the reverse-phase current and centered on the voltage VR1.器 CM1. The non-inverting input also operates around the voltage VR1. According to the fourth embodiment, even if the resistors R13 and R14 are increased, the differential potential difference of the comparator CM1 can be increased. Therefore, the consumption current can be suppressed, and the operation speed can be improved. In addition, since the non-inverting input range is small, the positive power supply VPP + and the negative power supply VPP- can be increased. Although one embodiment of the present invention has been described above, it is not limited to the above embodiment, and design changes made without departing from the scope of the present invention are included in the present invention. For example, in the first embodiment described above, although the complementary signal generating circuits 301H and 301L are designed to output a high value or a low level binary value, they can also be used to output an analog signal. An example of this configuration is shown in FIG. 11. In the figure, the amplifiers B52 and B53 correspond to the buffers B12 and B13 shown in Fig. 2 and output -36- 80426 I225333 analog signals corresponding to the PWM signals. The operational amplifiers OP51, resistors R52, and r53 constitute a differential amplifier, and the resistors R11 and R12 are used to amplify the difference of the analog signals input by the amplifiers B52 and B53. The resistors R54, R55, and operational amplifiers are configured as amplifiers. The amplifiers are used to convert the waveform having the reference voltage VREF following the emitter voltage of the power transistor 501 as the center of the amplitude. The power transistor 501 is used to drive an output terminal (not shown). With this structure, it is also applicable to linear amplifiers. As described above, according to the present invention, a first complementary signal composed of an in-phase signal and an inverted signal modulated by a modulated pulse signal is generated, and the signal level of the in-phase signal and the inverted signal are maintained. The magnitude of the relationship between the signal levels of the signal is complained about, and the aforementioned complementary signal is transformed into the second complementary signal following the predetermined voltage, and based on the other in-phase in the second complementary L number The magnitude of the signal component and the signal component of the inverted signal can drive the output transistor, so there is no need to use special manufacturing processes or electronic components to drive the power MOS transistor for output control. [Brief description of the drawings] Each and FIG. 1 is a diagram showing the overall structure of a class D amplifier according to Embodiment 1 of the present invention. · The diagram is a circuit diagram showing the configuration of a signal conversion circuit according to the first embodiment of the present invention. Figure 3 is a table-taxi style. "The structure of the bias circuit according to the first embodiment of the present invention. Fig. 4 is a waveform diagram for explaining the operation of the D-class amplifier according to the first embodiment of the present invention. The present invention > ^, Schematic diagram of the special desire part, Fig. 6 (a) ~ (d) on the structure of the Class D amplifier of the second embodiment are used to form a second embodiment of the present invention. D-level amplifier < action < waveform diagram. Fig. 7 is a circuit diagram for explaining the generation mechanism of the in-phase current of 菰 M, 椹 椹, two Zanyue < implementation mode 3. Fig. 8 shows the present invention Fig. 9 is a diagram showing the characteristics of the structure of the D-class amplifier in Form 3. Fig. 9 is a diagram showing the features of the structure of the D-class amplifier in Embodiment 4 of the present invention. The structure of the output-type operational amplifier according to the third embodiment of the invention. Fig. 11 is a diagram showing a characteristic part of the structure of a class D amplifier according to a modification of the present invention. Fig. 12 is a diagram for explaining a conventional technique. Structure of Class D amplifier. [Description of Symbols in Drawing] SIG signal source CIN capacitor DAMP D Stage amplifier 100 input section 200 modulation circuit 300 drive control circuit 301H, 301L signal generation circuit 80426 -38-302H, 302L signal conversion circuit 303H, 303L drive circuit 401, 402 output MOS transistor L inductor (coil) C capacitor (Capacitor) SPK Bn, B12, B13, B14, B2, B22, B23, B24, BD12, BD13 buffer 1225333

Rll, R12, R13, R14, R2, R22, R23, R24, R52, R53, R54, R55 Resistors Cll, C12, C13, C14 Capacitors

Pll, P12 Bias circuit CM1, CM2 Comparator P12, P22 Internal power supply P11, P12, P13, P14 PMOS transistor N11, N12, N13, N14 NMOS transistor OP60, OP52 Operational amplifier B52, B53 amplifier 501 transistor ( npn type) 80426 -39-

Claims (1)

1225333 Patent application park: A Class D amplifier, which has: a first output transistor, which is in the current path; U + "is connected to the output terminal, and a second output transistor is connected to the current path; Between the negative power supply and the aforementioned output terminals ^ The signal included in the input terminal of the intermediary and input from the outside: ^ T reflects the pulse width to modulate the signal into a pulse signal, and according to the pulse signal, the i and It is composed of a transistor; It is characterized by: Complementary signal generating circuit which generates and outputs an i-th complementary signal composed of the in-phase # signal and the inverse signal of the aforementioned pulse signal; and a signal conversion circuit. It is to maintain the signal level of the aforementioned in-phase signal and the magnitude relationship between the aforementioned signal level of the inverting signal to be in the same state. 'The first complementary signal is level-transformed into the second complementary Ihan number. And the second complementary signal follows a predetermined voltage that is based on the source voltage of the aforementioned first or second output power supply *; and the driving circuit is based on the aforementioned source voltage It is operated by an internal power supply, and the second complementary signal is input, and the first or second output is driven according to a signal component of the in-phase signal and a signal component of the inverting signal included in the second complementary signal. Crystals. For example, the D-class amplifier in the first scope of the patent application, wherein the above-mentioned conversion circuit of 80426 1225333 is provided with: a pair of first resistors connected to a pair of output portions of the signal conversion circuit showing the first complementary signal, And a pair of input portions of the driving circuit that presents the second complementary signal; a pair of second resistors whose one end side is a pair of input portions connected to the driving circuit; and The bias circuit biases the other ends of the pair of second resistors to the predetermined voltage. 3. For example, the D-level amplifier in the second item of the patent application scope further includes: a capacitor for correcting a pair of input sections parasitic from the pair of output circuits of the signal conversion circuit and a pair of input sections of the driving circuit. The unbalanced state of the capacitance component on the signal path. 4. If you apply for a Class D amplifier in item 2 or item 3 of the patent scope, which has: The current injection circuit injects a current into the first resistor of the pair to eliminate the in-phase current flowing through the first resistor of the pair. 5. The Class D amplifier of item 4 of the patent application, wherein the current injection circuit is composed of the following: a current monitoring circuit that monitors the in-phase current flowing through the aforementioned first resistors in a pair, and a current mirror circuit It is to input the current monitored by the current monitoring circuit and output a current equivalent to the current to the first resistor of the pair. 80426 -2- If the D-level amplifier of the second or third item of the scope of patent application, the aforementioned bias circuit is constituted by a dual output type operational amplifier, the operational amplifier has: 'pain inverting input section, non The output side of the pair of inverting input sections is on the end side. It is connected to the other end of the second resistor; ′ It is input with the predetermined voltage; and, it is connected with the above-f, pair of the second resistor 80426