TWI224866B - Method for defining silicon seed to form polysilicon layer and TFT manufactured by this method - Google Patents

Abstract

A method for defining silicon seed to form polysilicon layer comprises the following steps. First, form a sacrifice layer on a substrate and pattern the sacrifice layer to make an opening on the sacrifice layer. Second, form a first amorphous silicon layer on the sacrifice layer and substrate and then etch the first amorphous silicon layer to leave the silicon seed in the opening. Third, remove the sacrifice layer and form a second amorphous silicon layer on the silicon seed. Finally, let the amorphous silicon crystallize to make a polysilicon layer. This invention can precisely control the silicon seed to be formed on the channel region. Therefore, the grain size is enlarged and the grain boundary counts that cover along the channel region are reduced.

Description

1224866 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for forming a polycrystalline silicon layer, and more particularly to a method for defining a silicon seed crystal to form a polycrystalline silicon layer. [Prior technology] Because of the day-to-day Shixi; 4-membrane transistor (p〇1 y s U i cn t h i n f i 1 m transistor (p〇ly-Si TFT)) is more amorphous than

s i 1 i c ο n) T F T has relatively high electron mobility, faster response time, and higher resolution, so ‘multicrystalline silicon TFTs are now commonly used in LCDs to drive LCDs. Generally, the manufacturing method of the polycrystalline silicon TFT is a low temperature polysilicon (LTPS) method. Figures la to lb show cross-sectional views of the process of forming a polycrystalline spar layer using the LTPS method in a conventional tft array process. Referring to FIG. 丨 a, a barrier layer 120 and an amorphous silicon layer 2000 are sequentially formed on a substrate OO. The method of forming the amorphous silicon layer 2000 is generally by chemical vapor deposition (CVD; chemical vapor deposition) ° and then 'crystallization of the amorphous stone layer 200, such as the use of excimer laser annealing (ELA excimer laser annealing) for crystallization to form a polycrystalline silicon layer 3 0 0 (as shown in Figure 1b).

Traditionally, the amorphous silicon layer grown by CVD cannot directly control the position of nucleation (nuc 1 eati ο η) of laser crystals, so the grain size is not uniform, and the average grain size is usually Less than 1 # m, causing the number of grain boundaries covered by the channel area to be different, thus affecting the electrical properties and stability of the TFT.

1224866 V. Description of the invention (5) The crack "3a" is generated at the bottom of the "first amorphous stone layer 30", and the wet cracking "3a" is the most susceptible to erosion by the silver etching solution. Therefore, a silicon seed crystal 3 2 can be left in the opening 27 after the etching (as shown in FIG. 2d). Next, 'the sacrificial layer 2 5' is removed to form the structure shown in Fig. 2e. Next, referring to FIG. 2f, a second amorphous silicon layer 35 is formed on the silicon seed crystal 32. The second amorphous silicon layer 35 can be formed by chemical vapor deposition (CVD) using silicon methane (si iane; si H4) as a reaction gas, such as plasma-assisted chemical vapor deposition (PECVD; p 1 asma — enhanced chemical vapor depos iti on) or &LPCVD;LPCVD; low pressure chemical vapor deposition o o 'the same tea reading brother 2 f picture' make the second amorphous stone Layer 35 is crystallized to form a polyspar layer 40, as shown in Figure 2g. The first amorphous stone layer 30 (silicon seed 32) and the second amorphous silicon layer 35 may be formed using different methods, for example, the first amorphous stone layer 30 may be formed by a sputtering method, and the second The amorphous stone layer 35 can be formed by a chemical vapor deposition method. The present invention can use many conventional methods for crystallization, including excimer laser annealing (ELA) at low temperature, solid phase crystallization (SPC) at high temperature, and continuous grain growth method. (CGG; continuous grain growth), metal induced crystallization (MIC; metal induced crysta 1 1 iza 1: i ο n), metal induced lateral crystallization (M ILC; meta 1 induced lateral crystal 1 izat ion), spear mouth Continuous phase J direction solid 4 dagger method (SLS; sequential lateral solidification) and so on.

0632-9767TWf (Nl); AU91426; .ptd Page 9 1224866, description of the invention (6) The present invention can make use of the yellow light process to insert the stone 27 in the center of the opening 27. Invent the small size of ϋ ;;; 3] The size is less than 1 ... so, inch, the critical ruler required for crystalline heterogeneous nucleation is gradually based on the way of heterogeneous nucleation; i said: layer 3 door 5 is based on this The silicon seed crystal 32 is larger than the crystal, for example, and can be formed in a larger size. Then, according to the 2h figure, the patterned polycrystalline stone layer is doped using the lithography and etching method. = Doping to form Channel region 4Mση-type source / drain region 45 and zhao. Next, referring to FIG. 2i, a gate dielectric layer 50 is formed, and a gold layer is formed: :), and then lithography and photolithography are performed on the metal layer. Etch, and a gate layer 60 is formed at the corresponding position in the pass region 42. At this point, τρτ is completed. Then, referring to FIG. 2i, an interlayer dielectric 52 is formed, and then interlayer dielectric is formed. An opening 53 is formed in the electric layer 52 to reach the source / drain regions 45 and 46. Then, a metal is filled into the opening 53, The source / drain electrodes 65 and 66 are formed. In summary, the present invention uses a yellow light process to form an opening in a sacrificial layer, and forms a first amorphous silicon layer in the opening, and then etches this. The first amorphous silicon layer has a silicon seed crystal smaller than 1 m in the opening. In this way, during the crystallization, the second amorphous silicon layer uses the silicon seed crystal as a nucleation point and is formed heterogeneously. The nucleation is gradually crystallized, so the polycrystalline spar layer can have grains with a relatively large size (such as greater than 1 // m). "Furthermore, this Isming can be formed by controlling the openings in the future. τ f τ in the channel region, so that Shi Xi seeds can be formed in the channel region.

0632-9767TWf (Nl); AU91426 · .ptd Page 10 1224866 V. Description of the invention (7) There are large and uniform grains, which can reduce the number of grain boundaries covered by the channel area, and make the channel of each TFT The number of grain boundaries covered can be controlled within the same range, which can make the TFT have good electrical properties and stability. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be as defined by the scope of the patent application attached hereafter.

0632-9767TWf (Nl); AU91426; .ptd Page 11 1224866 Brief description of the diagrams Figures 1a to 1b show cross-sectional views of the traditional TFT array process using the LTPS method to form a polycrystalline silicon layer. Figures 2a to 2i show cross-sectional views of the process of defining a silicon seed crystal to form a polycrystalline silicon layer according to a preferred embodiment of the present invention. Fig. 3 is a top view relative to Fig. 2b, and Fig. 2b is a cross-sectional view taken along line A-A 'of Fig. 3. Explanation of reference numerals: conventional technology tags ~ 100 ~ substrates; 120 ~ barrier layers; 200 ~ amorphous silicon layers 3 0 ~ polycrystalline silicon layers of the present invention ~ 10 ~ substrates; 1 2 ~ Barrier layer; 20 ~ Sacrificial layer; 2 2 ~ Photoresist pattern; Φ 2 5 ~ Patterned sacrificial layer; 27 ~ Opening; 30 ~ First amorphous silicon layer; 30a ~ First amorphous silicon Cracks in layer 30 2 2 ~ silicon seeds;

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Claims (1)

1224866 6. The scope of patent application 1. In the picture, remove the famous insects 2. Crystal layer 3. Crystal seconds layer 4. Crystal seconds layer 5. Crystal seconds layer 6 · Crystal seconds layer 7. Between crystal fragments A 8 . Crystalline layer line 0 a kind of-the substrate file the sacrifice and the sacrifice to the second sacrifice the second method such as the application method such as the application method such as the application method such as the application method such as the application method. Application method ^ ^ 7 methods for forming a polycrystalline silicon layer, wherein a sacrificial layer is formed on the silicon wafer; the sacrificial layer is to form an opening in the sacrificial layer and a first amorphous layer is formed on the substrate Shi Xi layer, Shi Xi layer, and left Shi Xi seeds, amorphous layer in the opening; seeded amorphous broken patents, including patents, patents, patents, patents, and The patent model, wherein the patent model, forms a second amorphous stone layer; and the layer is crystallized to form a multi-crystal crushed layer. The sacrifice layer is defined as described in item 1 to form the sacrificial layer. The sacrificial layer is a metal or a metal alloy. The sacrifice layer is defined as described in item 2 to form a complex compound. The sacrificial layer is a chromium aluminum alloy. The definition of the silicon seed crystal described in item 1 to form a complex sacrificial layer is oxidation; The depth-seeking ratio of the silicon seed crystals defined in item 1 to form the opening is between 2 and 1-5. The definition of the silicon seed described in item 1 to form a complex compound: the amorphous stone layer is formed by the method. The definition of the silicon seed crystal described in item 1 to form the first amorphous stone layer and the thickness of the latter layer is 1 0 0 0 to 3 0 0 0. The silicon seed crystals were formed by the wet etching method to form a complex of engraved-amorphous stone Xiyu Valley 7. 1224866 The scope of the patent application is 9 · The method for defining a silicon seed to form a complex silicon layer as described in item 1 of the scope of the patent application, wherein the second amorphous silicon layer is formed by chemical vapor deposition 0, v 1 0 · A method for manufacturing a polycrystalline silicon thin film transistor, comprising: ... forming a channel region, a source region, a drain region, a gate dielectric layer and a closed electrode on a substrate, wherein the formation of the channel region The method includes the following steps: forming a sacrificial layer; Patterning the sacrificial layer to form an opening in the sacrificial layer; forming a first amorphous stone layer on the sacrificial layer and the substrate; etching the first amorphous silicon layer, leaving a stone in the opening Seed crystal; removing the sacrificial layer; forming a second amorphous silicon layer on the silicon seed crystal; crystallizing the second amorphous stone layer to form a polycrystalline silicon layer and patterning the polycrystalline silicon layer And the method of forming the edge & complex silicon thin film crystal as described in item 0 of the scope of the patent application, wherein the sacrificial layer is a metal or a metal alloy. ° 1 12 The method of making & crystal film crystal according to item 1, wherein the sacrificial layer is a chrome aluminum alloy: a method for forming a polycrystalline silicon thin film 1 3 · The method for crystal as described in item 10 of the scope of patent application, The sacrificial layer is silicon oxide. Manufacture of polycrystalline silicon thin film 14. As described in item 5 of the scope of patent application, between 5 and 5. Crystal method, wherein the depth-to-width ratio of the opening is 2 ^ made of a polycrystalline silicon thin film 1 5 · As described in item 10 of the scope of patent application ’ 0632-9767TWf (Nl); AU91426; .ptd 15th buy