TWI223429B - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
TWI223429B
TWI223429B TW92117360A TW92117360A TWI223429B TW I223429 B TWI223429 B TW I223429B TW 92117360 A TW92117360 A TW 92117360A TW 92117360 A TW92117360 A TW 92117360A TW I223429 B TWI223429 B TW I223429B
Authority
TW
Taiwan
Prior art keywords
spare
block
semiconductor integrated
integrated circuit
functional block
Prior art date
Application number
TW92117360A
Other languages
Chinese (zh)
Other versions
TW200402865A (en
Inventor
Hiroshi Miyagi
Original Assignee
Toyota Ind Corp
Niigata Seimitsu Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Ind Corp, Niigata Seimitsu Co Ltd filed Critical Toyota Ind Corp
Publication of TW200402865A publication Critical patent/TW200402865A/en
Application granted granted Critical
Publication of TWI223429B publication Critical patent/TWI223429B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An unsuitable element in a functional black 11 can be substituted by a spare element if a spare element group black 12, each of the functional blocks 11 is respectively arranged on the surrounding of the spare element group block 12.

Description

1223429 玖、發明說明: [發明所屬之技術領域] 本發明係關於一種半導體積體電路,特別是關於一種具 有可用以代用最初所用元件之備用元件的半導體積體電路 者。 [先前技術] 一般,在半導體積體電路中,爲了代用在製造過程中所 產生品質不良之電路或元件等,係預備以冗長之電路。又 ’所製造之電路如有做錯時,則須準備用以修正該電路做 錯部分之代用元件。 關於冗長電路之代表例,則如半導體記憶體之冗長電路 者。半導體記憶體之狀況中,其最多不良者,因係發生於 記憶胞(memory cell),因之,乃準備了以字碼(word)線或 以比特(bit ’或稱位元)線爲單位之冗長記憶胞。冗長電路 亦係和正規電路同樣的,藉熔栓(f u s e )作配線連接。因之, 乃在發生不良之階段,遂行切斷連接於不良電路之熔栓等 之處理,依此種方式,則至此所使用之冗長電路即取代不 良電路,成爲可使用之狀態。 此外,如係使用電晶體、電阻、電容器等備用元件之狀 況時,因備用元件本身已搭載於半導體積體電路中,故不 作配線連接。但是,所製造之半導體積體電路之元件如爲 不適合時,其作法係在擬取代該不適合元件之備用元件上 ’使用掩罩(mask)等’並另增加以金屬配線以達取代功能 ’則至此所使用之備用元件即可成爲可使用之狀態。 -6- 1223429 近年,具系統L S I (大型積體電路)代表性之半導體積體電 路,甚多係以複數個功能塊(functional block)搭載於1個 晶片上構成之。此狀況中,習用之半導體積體電路上,作 爲代替用之備用元件者,係搭載於各功能塊間所形成之空 隙空間(dead space,下稱死角)中。 第1圖爲習用半導體積體電路之構成模式平面圖。 如第1圖所示,半導體晶片4 0上,構成有複數之工能塊 4 1,4 卜 1,4 1 -2,…4 1 -7)等。 將複數個功能塊4 1實裝於1個的半導體晶片4 0時,因 爲各功能塊4 1之大小及形狀均不同,故在各功能塊4 1之 間,即產生了手法設以任何種元件,亦手法作配線之死角 42-1及42-2。習用技術中,通常係在該等死角上搭載不常 使用之備用元件,以企求半導體晶片4 0之面積有效利用。 例如,在第1圖中,於死角4 2 - 1處配置以電容器4 3及 電阻44,而於死角42-2處,則配置以NMOS電晶體45、 PMOS電晶體46、NOT鬧47、及NAND聞48,等之備用元 件。 但是,該等死角4 2 - 1及4 2 - 2,係因配置該各功能塊4 1 結果所致之產物,故其距離實難以限制令其與哪一個功能 塊之距離爲最近,例如,功能塊4 1 - 7與p M 〇 S電晶體4 6 即相距甚遠。又,死角42-1及42-2多係發生於複數個功 能塊4 1周圍的狹小領域中。 因之,如把備用元件搭載於該種死角42-1及42-2處時 ,由某一功能塊4 1內所使用之元件須另增加配線至備用元 1223429 件作取代,該種配線本身實甚困難,即或勉爲配線,但因 其配線長度甚長,故亦問題叢生。特別的是,如爲類比電 路時’配線長度太長則所形成之雜訊亦大,結果,造成了 所不希望之機器性能低落。 本發明之目的’係爲了解決上述之諸種問題,而提供一 種丰導體積體電路’可用最簡單之方式,由某一功能塊內 最初使用之元件朝備用元件作配線以作取代,同時,其朝 備用元件之配線亦可爲最短者。1223429 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a spare element that can be used in place of the element originally used. [Prior art] Generally, in a semiconductor integrated circuit, a redundant circuit is prepared in order to substitute a circuit or a component having a poor quality generated in the manufacturing process. Also, if the circuit is made wrong, substitute components must be prepared to correct the wrong part of the circuit. A typical example of a redundant circuit is a redundant circuit of a semiconductor memory. Among the conditions of semiconductor memory, the most bad ones occur in memory cells. Therefore, the unit is prepared by using word lines or bit lines. Long memory cells. The redundant circuit is the same as the regular circuit, and is connected by a fuse (f u s e). Therefore, it is necessary to cut off the fusible link connected to the defective circuit at the stage where the defect occurs. In this way, the redundant circuit used so far will replace the defective circuit and become usable. In addition, in the case of using spare components such as transistors, resistors, and capacitors, since the spare components themselves are already installed in the semiconductor integrated circuit, wiring connections are not required. However, if the manufactured semiconductor integrated circuit components are not suitable, the method is to 'use a mask, etc.' on a spare component intended to replace the unsuitable component, and additionally use metal wiring to replace the function. The spare components used so far can be used. -6- 1223429 In recent years, semiconductor integrated circuits, which are representative of the system L S I (large-scale integrated circuit), are often constructed by mounting a plurality of functional blocks on a single chip. In this case, the conventional semiconductor integrated circuit, as a replacement component, is mounted in a dead space (hereinafter referred to as a dead space) formed between the functional blocks. FIG. 1 is a plan view showing a configuration pattern of a conventional semiconductor integrated circuit. As shown in FIG. 1, the semiconductor wafer 40 includes a plurality of work blocks 4 1, 4 b 1, 4 1 -2, ... 4 1 -7) and the like. When a plurality of functional blocks 41 are mounted on one semiconductor wafer 40, since the size and shape of each functional block 41 are different, a method is created between each functional block 41 Components, also used as dead angles 42-1 and 42-2 for wiring. In conventional technology, spare parts that are not frequently used are usually mounted on such dead corners in order to effectively utilize the area of the semiconductor chip 40. For example, in the first figure, a capacitor 43 and a resistor 44 are disposed at the dead corner 4 2-1, and an NMOS transistor 45, a PMOS transistor 46, a NOT 47, and 47 are disposed at the dead corner 42-2. NAND smells 48, etc. However, these dead angles 4 2-1 and 4 2-2 are the products caused by the configuration of the functional blocks 4 1, so it is difficult to limit the distance between them and which functional block is the closest. For example, The function blocks 4 1-7 are far away from the p M 0S transistor 4 6. Further, the dead angles 42-1 and 42-2 mostly occur in a narrow area around the plurality of function blocks 41. Therefore, if a spare component is mounted at the dead corner 42-1 and 42-2, the component used in a certain functional block 41 must be additionally wired to the spare element 1223429 to replace it. The wiring itself It is very difficult, even if it is barely wiring, but because its wiring length is very long, it is also problematic. In particular, if the wiring length is too long in the case of an analog circuit, the noise generated is also large, and as a result, the undesirable performance of the machine is lowered. The purpose of the present invention is to provide an abundance conductive volume circuit in order to solve the above-mentioned problems. The simplest way is to replace the components originally used in a certain functional block with a spare component and replace them. The wiring to the spare component can also be the shortest.

[發明內容] 爲了解決上述問題之本發明,採用了下述之構成。 亦即,依本發明之半導體積體電路,係一種具有一個以 上、PJ貫現所疋機㊆之電路予以群集之功能塊< f i a na丄 block),的半導體積體電路者,並具有備用元件塊,其內 設有備用元件’可對該功能塊內之元件作代用,而該功能 塊則係配置在該備用元件塊之周圍者。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the present invention, the following configuration is adopted. That is, the semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having more than one functional block < fia na) block), which are clustered by a PJ circuit, and has a spare. The component block is provided with a spare component, which can substitute the components in the functional block, and the functional block is arranged around the spare component block.

此處,倘該功能塊係例如以高頻無線電路之半導體構成 時,如調諧器(tuner)部或介面部(inter face)等,係圍繞著 設有備用元件之備用元件塊作配置。 由於功能塊係配置在備用元件塊之周圍,因自某功能塊 至備用元件間之配線距離最短,故除了當某功能塊內之元 件發生有不適合狀況時,可用最簡單之方式朝備用元件作 配線之外,同時,亦可縮短其朝備用元件之配線長度者。 又,上述之半導體積體電路,該功能塊係以該備用元件 塊爲中心而配置於該備用元件塊之四周。 - 8- 1223429 藉此’由任可一個功能塊朝備用兀件之配線即可簡早的 實行,並可縮短朝配線元件之配線長度。 再者,上述半導體積體電路中,該功能塊係具有供給該 功能塊電源電壓之電源軌;及用以設定該功能塊內基準電 壓之接地軌,故該備用元件塊,乃可配置在:由配置於該 功能塊之該電源軌起至該接地軌止,兩者間之領域以外之 位置上。 依此,因自電源軌至接地軌之領域並未變大,故可抑制 整個電路之大型化。 又,該半導體積體電路中,該備用元件塊可和該功能塊 作平行配置,且作成細長形之構成者。 依此,乃可將該備用元件單元以省空間方式配置於半導 體積體電路之中央部分上。 又,上述之半導體積體電路,該備用元件可作成連接於 複數配線層最上位之配線層的構造者。 依此,如有不適合之半導體元件時,因僅變更最上位配 線層之掩罩,即可遂行備用元件之取代替換,而不須由上 至下作各蛇線層之掩罩變更作業,此一部分之作業時間及 成本乃可大幅降低。 [圖式簡單說明] 本發明將佐以如下之附圖說明而更爲顯見,其中: 第1圖爲習用半導體積體電路之構成模式平面圖。 第2圖爲本發明半導體積體電路一實施例之構成模式平 面圖。 -9- 1223429 第3圖爲第2圖中之虛線部分放大圖。 第4圖爲本發明半導體積體電路另一實施例之構成模式 平面圖。 爲了實施發明之最佳形態 以下,佐以圖面說明本發明之實施例。 第2圖爲本發明半導體積體電路一實施例之構成模式平 面圖。Here, if the functional block is composed of, for example, a semiconductor of a high-frequency wireless circuit, such as a tuner section or an inter face, the functional block is arranged around a spare element block provided with a spare element. Since the function block is arranged around the spare component block, the wiring distance from a certain functional block to the spare component is the shortest. Therefore, except when the component in a certain function block is unsuitable, the simplest method can be used for the spare component. In addition to wiring, at the same time, the length of the wiring toward the spare component can be shortened. In the above-mentioned semiconductor integrated circuit, the functional block is arranged around the spare element block around the spare element block. -8- 1223429 By this means, the wiring from any functional block to the spare element can be implemented early and shorten the wiring length to the wiring element. Furthermore, in the above-mentioned semiconductor integrated circuit, the functional block has a power rail for supplying a power voltage of the functional block; and a ground rail for setting a reference voltage in the functional block, so the spare component block can be configured in: The position from the power rail to the ground rail in the function block is located outside the area between the two. Accordingly, since the area from the power rail to the ground rail is not enlarged, the size of the entire circuit can be suppressed. Further, in the semiconductor integrated circuit, the spare element block may be arranged in parallel with the functional block and formed into an elongated configuration. According to this, the spare component unit can be space-savingly arranged on the central portion of the semiconductor volume circuit. In the above-mentioned semiconductor integrated circuit, the spare element can be constructed as a structure connected to the uppermost wiring layer of the plurality of wiring layers. According to this, if there is an unsuitable semiconductor element, only the mask of the uppermost wiring layer is changed, and the replacement of the spare element can be performed instead of changing the mask of each snake layer from top to bottom. Part of the operation time and cost can be greatly reduced. [Brief Description of the Drawings] The present invention will be more apparent with the following description of the drawings, in which: FIG. 1 is a plan view showing the structure of a conventional semiconductor integrated circuit. Fig. 2 is a plan view showing a configuration pattern of an embodiment of a semiconductor integrated circuit of the present invention. -9- 1223429 Figure 3 is an enlarged view of the dotted line in Figure 2. Fig. 4 is a plan view showing a constitution pattern of another embodiment of a semiconductor integrated circuit of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 2 is a plan view showing a configuration pattern of an embodiment of a semiconductor integrated circuit of the present invention.

如第2圖所示,半導體晶片1 〇係由複數個功能塊丨丨(丨丨_ j, 1 1 - 2 5…1 1 - 7 );及備用元件群塊1 2 ;所構成。爲了實現一 個機能之電路,乃依MOS構造或依雙極構造等方式予以積 體化之。As shown in FIG. 2, the semiconductor wafer 10 is composed of a plurality of functional blocks 丨 丨 (丨 丨 _ j, 1 1-2 5 ... 1 1-7); and a spare element group block 1 2; In order to realize a functional circuit, it is integrated according to the MOS structure or the bipolar structure.

此處所稱之機能,係指將以一個半導體晶片1 0即可實現 全體之處理予以分割成某些個較小單位之機能單位者,其 之處理內容或分割數量則依半導體晶片1 0之用途而不同 。例如,倘該半導體積體電路係實現高頻手線電路時,則 可分割成含有射頻調諧器部、中頻處理部、介面部等之機 能單元1 1。而晶片尙可含基帶(base band)信號處理部。 在該等功能塊1 1上,經擴散過程而藉全屬掩罩遂行金屬 配線,即完成上述電路之配線。本實施例之半導體積體電 路中,除了複數個功能塊1 1外,並對將來替換可能性較高 之功能塊另設1個備用元件塊作爲備用,因此,乃在半導 體晶片1 〇之中心配設多數個備用元件所構成之備用元件 群塊1 2,依此,備用元件群單元塊1 2所配置之位置距離 功能塊最近。 -10- 1223429 又,功能塊1 1內之元件有不適合時,則使用金屬等之配 線,即可用備用元件群1 2內之備用元件替換該不適合之元 件。 再者,本實施例之半導體積體電路如爲多層構造之狀況 時,變更最上位層之掩罩,即可令備用元件替代發生不適 合狀況之功能塊。亦即,半導體積體電路如係以3片之VIA (通孔)層及2片之配線層構成爲5層構造時,則預先在最 下位層配置以備用元件群塊1 2。因此,自備用元件至最上 位層以通孔(VI A)及金屬配線連接上,依此,發生有不適合 之半導體元件時,僅變更最上位置之掩罩,即可用備用元 件取代之,而不須施作由上至下位置爲止之掩罩變更,故 可大幅削減此一部分之作業時間及成本。 依此,因功能塊1 1係以備用元件群塊1 2爲中心而配置 在其四周,故該功能塊1 1即可用最近位置之備用元件取代 之。亦即,功能塊1 1至備用元件1 2間之配線長度可短縮 者。 第2圖所示之備用元件群塊1 2,係配置有電容器1 2- 1、 電阻 12-2、NMOS 電晶體 12-3、PMOS 電晶體 12-4、NOT 閘12-5、N AND閘12-6等。又,第2圖所示之備用元件僅 爲舉例而已,當非限制係該等元件。 又,上述之備用元件係就功能塊內積體化電路中發生有 有不適合狀況時,用以修正該電路以令其可使用之代用元 件者,因此,備用元件群塊1 2上設置何種元件、多少個元 件等,則依配置在該備用元件群塊1 2四周之功能塊1 1的 1223429 電路內容而有所不同。但是’倘事先已知嗣後將來用到之 可能性極高的備用元件時,可將該備用元件配置在最近於 該對應之功能塊的位置上。The function referred to here refers to the functional unit that can be divided into certain smaller units by one semiconductor wafer 10 to achieve the entire processing. The processing content or the number of divisions depends on the use of the semiconductor wafer 10 But different. For example, if the semiconductor integrated circuit implements a high-frequency hand line circuit, it can be divided into a functional unit 11 including a radio frequency tuner section, an intermediate frequency processing section, and a face section. The chip may include a base band signal processing unit. On these functional blocks 11, the metal wiring is completed through the masking process through the diffusion process, and the wiring of the above circuit is completed. In the semiconductor integrated circuit of this embodiment, in addition to a plurality of functional blocks 11, a spare element block is set as a spare for a functional block having a higher possibility of replacement in the future, so it is at the center of the semiconductor wafer 10 A spare element group block 12 composed of a plurality of spare elements is arranged, and accordingly, the position of the spare element group unit block 12 is closest to the function block. -10- 1223429 In addition, if the components in the function block 11 are not suitable, use metal or other cables to replace the unsuitable components with the spare components in the spare component group 12. Furthermore, if the semiconductor integrated circuit of this embodiment has a multilayer structure, changing the mask of the uppermost layer can replace the spare component with a functional block that is not suitable for the situation. In other words, if the semiconductor integrated circuit has a five-layer structure with three VIA (through-hole) layers and two wiring layers, a spare element group 12 is arranged in the lowermost layer in advance. Therefore, VIA and metal wiring are used to connect the spare element to the uppermost layer. Therefore, if an unsuitable semiconductor element occurs, only the mask at the uppermost position can be changed, and the spare element can be used instead. There is no need to change the mask from the top to the bottom position, so the operation time and cost of this part can be greatly reduced. According to this, since the function block 11 is arranged around the spare element group block 12 as the center, the function block 11 can be replaced with the spare element at the nearest position. That is, the wiring length between the function block 11 to the spare element 12 can be shortened. The spare component group 12 shown in Fig. 2 is configured with capacitors 1 2-1, resistance 12-2, NMOS transistor 12-3, PMOS transistor 12-4, NOT gate 12-5, and N AND gate. 12-6 and so on. In addition, the spare components shown in Fig. 2 are just examples, and they are not restricted. In addition, the above-mentioned spare component is a substitute component used to modify the circuit so that it can be used when an unsuitable condition occurs in the integrated circuit in the functional block. Therefore, what kind of spare component group 12 is provided? Components, how many components, etc., are different according to the 1223429 circuit content of the function block 1 1 arranged around the spare component group block 12. However, if a spare component with a high probability of being used in the future is known in advance, the spare component can be placed closest to the corresponding functional block.

又,如上述,習用之半導體積體電路,備用元件係配置 於各功能塊間所形成之死角4 2 - 1、4 2 - 2上。則例如,功能 塊4 1 - 5須要電阻4 4,及功能塊4 1 - 7須要Ρ Μ 0 S電晶體4 6等 狀況時,須在該等備用元件施作配線以達替代之功能,惟 因例如功能塊4 1 - 6等其他功能塊4 1之存在,對該配線即 造成妨礙,故該種配線本身實極困難。又,倘配線本身係 繞過該其他功能塊而成爲迂迴形,亦使配線長度增長甚多。 對此,依本實施例之半導體積體電路,具有所須備用元 件之備用元件群塊1 2,係配置於具有各功能塊1 1之半導 體晶片1 〇的中心處,則例如,功能塊1 1 - 1及功能塊1 1 - 7 內之元件發生有不適合時,可用配線方式使用備用元件群 塊1 2內配置之備用元件代用之,該不適合功能塊及該擬代 用備用元件間之配線甚爲簡單,且配線長度甚短者。As described above, in the conventional semiconductor integrated circuit, the spare components are arranged on the dead corners 4 2-1 and 4 2-2 formed between the functional blocks. Then, for example, when the function blocks 4 1-5 need resistance 4 4 and the function blocks 4 1-7 need PM 0 S transistor 4 6 and other conditions, the spare components must be wired for replacement functions. Because of the existence of other functional blocks 41 such as functional blocks 4 1-6, the wiring is hindered, so this kind of wiring itself is extremely difficult. In addition, if the wiring itself bypasses the other functional blocks and becomes a circuitous shape, the length of the wiring will be greatly increased. In this regard, according to the semiconductor integrated circuit of this embodiment, a spare element group block 12 having necessary spare elements is arranged at the center of a semiconductor wafer 10 having each functional block 11, for example, the functional block 1 1-1 and function block 1 1-7 When components are not suitable, you can use the wiring method to use the spare component group 12 in place of the replacement component, which is not suitable for the functional block and the replacement component to be replaced. For simplicity, and the wiring length is very short.

又,本實施例之半導體積體電路中,備用元件群塊1 2上 僅爲配置備用元件,衡諸習用之半導體積體電路,其備用 元件係配置在死角內,本實施例所可配置之備用元件數量 自然較多。 第3圖爲第2圖虛線部分放大圖。 如第3圖所示,各功能塊(第3圖中爲功能塊1 1-2、1 1-3 及1 1-4)係設在:用以供給功能塊1 1電源電壓之電源(VCC) 軌20 ;及用以設定各機能中基準電壓之接地(GND)軌21 ; -12- 1223429 兩者之間。因之,備用元件群塊1 2係設在接地軌2 1之隔 鄰(外側)°亦即,備用元件群塊1 2並非位在配置功能塊之 電源軌2 0、及接地軌2 1兩者間之領域a內,而係位在其 外側之領域b中。又,電源軌2 〇及接地軌2 1,亦係位在 其他之功能塊1 1 - 1、1 1 - 4、1 1 - 5、1卜6及1 1 - 7的兩側,惟 第3圖中未示。又,第3圖中,備用元件群塊1 2係配置於 接地軌2 1之外側,依功能塊n之構成,再於其側面配置 電源軌2 0。Moreover, in the semiconductor integrated circuit of this embodiment, the spare element group block 12 is only configured with a spare component. For the conventional semiconductor integrated circuit, the spare component is arranged in a dead space. The number of spare components is naturally high. FIG. 3 is an enlarged view of a dotted line in FIG. 2. As shown in Fig. 3, each function block (function blocks 1 1-2, 1 1-3, and 1 1-4 in Fig. 3) is provided at: a power supply (VCC) for supplying a power supply voltage to the function block 11 ) Rail 20; and ground (GND) rail 21 for setting the reference voltage in each function; -12-1242929. Therefore, the spare element group block 12 is located adjacent to (outside) the ground rail 21, that is, the spare element group block 12 is not located on the power rail 20 and the ground rail 2 1 of the function block. The area a between them is in area b outside it. In addition, the power rail 2 0 and the ground rail 21 are also located on the two sides of the other function blocks 1 1-1, 1 1-4, 1 1-5, 1 6 and 1 1-7, but the third Not shown in the figure. In Fig. 3, the spare element group block 12 is arranged outside the ground rail 21, and according to the structure of the function block n, a power supply rail 20 is arranged on its side.

如是’備用元件塊1 2係設於領域b內,惟如將備用元件 群塊1 2設於電源軌20及接地軌2 1間之領域a的構成時, 因爲可縮小電源軌2 0及接地軌之距離(領域),故可令整個 半導體晶片1 〇之面積縮小。For example, 'spare component block 12 is located in area b. However, when the spare component group block 12 is provided in the area a between the power rail 20 and the ground rail 21, the power rail 20 and the ground can be reduced. The distance (area) of the rails can reduce the area of the entire semiconductor wafer 10.

以上,倘依本實施例之半導體積體電路,如有某一功能 塊內之使用元件發生有不適合狀況時,可甚簡單的朝備用 元件作配線即可,且,其朝備用元件配線之長度亦甚短, 可極力抑制機器性能之劣化(尤以雜音爲然)。又,因該等 備用元件群塊1 2係配置在中心,其四周係配置以功能塊 1 1,雖使半導體晶片1 〇之尺寸稍微增大些,但此種構成較 諸習用者可大幅減省作業時間及成本的利點而言,其優點 大於缺點甚多,足資彌補。 又,以上所說明實施例之半導體積體電路,僅不過爲實 施本發明之一化表性例示而已,在不脫離本發明精神範圍 內,自有其他各種之修改及變更。 例如,第4圖所示,即爲其他實施形態之半導體積體電 -13- 1223429 路之構成模式平面圖。 第4圖所示之半導體晶片3 0,與第2圖所示半導體晶片 10同樣的,功能塊…11-7)係以備用元件群 3 1爲中心環繞配置。 與第2圖之半導體晶片1 0的不同處爲,把備用元件群塊 3 1平行於功能塊1 1配置,且,其構成係細長形者。又’Above, if the semiconductor integrated circuit according to this embodiment has any unsuitable conditions for the used components in a certain functional block, it can be simply wired to the spare component, and the length of the wiring towards the spare component It is also very short, which can minimize the degradation of machine performance (especially noise). In addition, since these spare element group blocks 12 are arranged in the center and the functional blocks 11 are arranged around them, although the size of the semiconductor wafer 10 is slightly increased, this structure can be greatly reduced compared with those of conventional users. In terms of saving operating time and costs, its advantages outweigh its disadvantages and are fully compensated. In addition, the semiconductor integrated circuit of the embodiment described above is merely an illustrative example for implementing the present invention, and various other modifications and changes are possible without departing from the spirit of the present invention. For example, FIG. 4 is a plan view showing the structure of the semiconductor integrated circuit -13-1223429 of another embodiment. The semiconductor wafer 3 0 shown in FIG. 4 is the same as the semiconductor wafer 10 shown in FIG. 2. The functional blocks 11-11) are arranged around the spare element group 31. The difference from the semiconductor wafer 10 shown in FIG. 2 is that the spare element group block 31 is arranged parallel to the functional block 11 and its structure is slender. also'

第4圖所示之備用元件群塊3 1,其各備用元件係一個接一 個成一排或一列配設構成,倘塊之形狀爲細長形時,對於 備用元件之配列形成並無任何限定。 如是,將備用元件塊3 1作成細長形,則可將備用元件群 塊3 1以省空間之方式配置在半導體晶片3 0之中心,因而 可令半導體晶片3 0之面積縮小。又,備用元件群塊3 1因 其細長形狀致使面積縮小;故配置於其上之備用元件數量 自然較少·,則整個半導體晶片3 0之面積即變小。The spare element group block 31 shown in FIG. 4 is configured by arranging each spare element one by one in a row or a row. If the shape of the block is elongated, there is no limitation on the arrangement of the spare element. If it is, if the spare element block 31 is made slender, the spare element block 31 can be arranged in the center of the semiconductor wafer 30 in a space-saving manner, so that the area of the semiconductor wafer 30 can be reduced. In addition, the spare element cluster 31 has a reduced area due to its slender shape; therefore, the number of spare elements arranged thereon is naturally small, and the area of the entire semiconductor wafer 30 becomes smaller.

由上述可知,依本發明之半導體積體電路,係具有備用 元件塊’當功能塊內之元件不適合時。可用備用元件代用 之’因該備用元件塊之四周配置該功能塊,故如有某一功 能塊內之元件發生有不適合狀況時,可用極簡單之方式朝 代用之備用元件施行配線以遂行其機能,且配線之長度復 甚短者。 主要部分之代表符號說明 10 半導體晶片 11 功能塊 12 備用元件群塊 -14 - 電源軌 接地軌 半導體晶片 備用元件群塊 半導體晶片 功能塊 死角 電容器From the above, it is known that the semiconductor integrated circuit according to the present invention has a spare element block 'when the elements in the functional block are not suitable. It can be replaced by a spare component. Because the functional block is arranged around the spare component block, if there is an unsuitable condition for a component in a functional block, wiring to the substitute spare component can be performed in a very simple way to perform its function. , And the length of the wiring is very short. Description of Representative Symbols of Main Parts 10 Semiconductor Wafer 11 Function Block 12 Spare Component Block -14-Power Rail Ground Rail Semiconductor Wafer Spare Component Block Semiconductor Wafer Functional Block Dead End Capacitor

NMOS電晶體 PMOS電晶體 NOT聞 NAND 閘NMOS transistor PMOS transistor NOT NAND gate

-15--15-

Claims (1)

1223429 拾、申請專利範圍: 1 · 一種半導體積體電路,具有1個以上之群集有用以實現 所定機能之電路的功能塊,其特徵爲: 該半導體積體電路具有備用元件塊,其設有可對該功 能塊內之元件作代用之備用元件;且 該功能塊係配置在該備用元件塊之四周者。 2 ·如申請專利範圍第1項之半導體積體電路,其中1223429 Scope of patent application: 1 · A semiconductor integrated circuit with more than one functional block that can be used to achieve a predetermined function. It is characterized in that the semiconductor integrated circuit has a spare component block, which is provided with Substitute spare parts for the components in the functional block; and the functional block is arranged around the spare component block. 2 · Semiconductor integrated circuits such as the one in the scope of patent application, where 該功能塊係以該備用元件塊爲中心而配置於該備用元 件塊之四周者。 3 .如申請專利範圍第丨項之半導體積體電路,其中 該功能塊係具有用以對該功能塊供給電源電壓之電源 軌’及用以設定該功能塊內之基準電壓的接地軌; 其特徵爲,該備用元件塊係配置在:自配置有該功能 塊之該電源軌至該接地軌爲止之間領域以外之位置上。 4 ·如申請專利範圍之第1項之半導體積體電路,其中The functional block is arranged around the spare component block with the spare component block as a center. 3. The semiconductor integrated circuit according to item 丨 of the patent application scope, wherein the functional block has a power rail for supplying a power voltage to the functional block and a ground rail for setting a reference voltage in the functional block; It is characterized in that the spare element block is arranged at a position outside the area from the power rail to the ground rail where the functional block is arranged. 4 · If the semiconductor integrated circuit of item 1 of the patent application scope, wherein 該備用元件係與該功能塊相平行配置,且係以細長方 式形成者。 5 ‘ %申請專利範圍第i項之半導體積體電路,其中 該備用元件係連接於複數個配線層最上位之配線層者。 -16-The spare element is arranged in parallel with the functional block and is formed in a slender manner. 5 ′% The semiconductor integrated circuit of the scope of application for patent item i, wherein the spare element is connected to the uppermost wiring layer of the plurality of wiring layers. -16-
TW92117360A 2002-06-28 2003-06-26 Semiconductor integrated circuit TWI223429B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002190288A JP2004039664A (en) 2002-06-28 2002-06-28 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
TW200402865A TW200402865A (en) 2004-02-16
TWI223429B true TWI223429B (en) 2004-11-01

Family

ID=29996881

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92117360A TWI223429B (en) 2002-06-28 2003-06-26 Semiconductor integrated circuit

Country Status (3)

Country Link
JP (1) JP2004039664A (en)
TW (1) TWI223429B (en)
WO (1) WO2004004009A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4652861B2 (en) 2005-03-23 2011-03-16 三菱電機株式会社 Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3083547B2 (en) * 1990-07-12 2000-09-04 株式会社日立製作所 Semiconductor integrated circuit device
JP2830636B2 (en) * 1992-07-22 1998-12-02 日本電気株式会社 Method for manufacturing semiconductor device
JPH0676594A (en) * 1992-08-25 1994-03-18 Mitsubishi Electric Corp Semiconductor memory
JPH10261781A (en) * 1997-03-17 1998-09-29 Hitachi Ltd Semiconductor device and system

Also Published As

Publication number Publication date
WO2004004009A1 (en) 2004-01-08
TW200402865A (en) 2004-02-16
JP2004039664A (en) 2004-02-05

Similar Documents

Publication Publication Date Title
US8174052B2 (en) Standard cell libraries and integrated circuit including standard cells
KR100477042B1 (en) Semiconductor integrated circuit and standard cell layout designing method
US20080180132A1 (en) Semiconductor device and method of fabricating the same
US20140252653A1 (en) Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
US7294892B2 (en) Multi-transistor layout capable of saving area
BR112019009940A2 (en) adaptive multilayer power distribution networks for integrated circuits
US20190138682A1 (en) Engineering change order (eco) cell architecture and implementation
US11101265B2 (en) Apparatuses and methods for semiconductor circuit layout
US8124469B2 (en) High-efficiency filler cell with switchable, integrated buffer capacitance for high frequency applications
JP4932980B2 (en) Semiconductor die with on-die decoupling capacitance
JPH10275898A (en) Semiconductor integrated circuit device
US9053960B2 (en) Decoupling capacitor for integrated circuit
TWI223429B (en) Semiconductor integrated circuit
US6477696B2 (en) Routing definition to optimize layout design of standard cells
JP2005259905A (en) Semiconductor integrated circuit and its correction method
CN101727526A (en) Method and device for designing MOS tube layout and chip
US10157902B2 (en) Semiconductor devices with cells comprising routing resources
JP3644138B2 (en) Semiconductor integrated circuit and placement and routing method thereof
US20050071798A1 (en) Power supply layout for an integrated circuit
US20060198219A1 (en) Semiconductor integrated circuit device
US20080067551A1 (en) Semiconductor device having pseudo power supply wiring and method of designing the same
US20170338180A1 (en) Method of making vertical and bottom bias e-fuses and related devices
KR101523952B1 (en) Semiconductor device and method for fabricating the same
JPH11204766A (en) Semiconductor integrated circuit and its design method
US7900176B2 (en) Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees