1222188 五'發明說明（1) 、 【發明所屬之技術領域】 _ 本發明是有關於一種保護方法，且特別是有關於一種接腳 墊片之保護方法。 ^ 【先前技術】 參見第一圖所示為傳統的接腳墊片結構，係在半導體底材 100上形成一金屬導電層作為接腳墊片102，其中此接腳墊_ 片102可以銘銅合金（AlCu)所組成，而半導體底材1〇〇上形 成有復數個半導體元件與電路。 之後在接腳墊片102上沈積一層保護層104，以保護半導體 底材100上之半導體元件與電路，其中此保護層可由氮 化石夕層（Nitride)所形成。並利用微影蝕刻技術蝕刻部份保 護層1 04，把做為接腳墊片之用的金屬區域，以濕式或乾式 飯刻法加以挖開，以便於接著進行後續之晶片封裝。 在進行後續之晶片封裝前，通常會進行如第二A圏至第二b 圖所示之點探針測試電性，其係利用測試探針丨〇6直接接觸 =腳墊片102以量測電性。由於傳統接腳墊片1〇2係由鋁銅> 合金所形成，因為鋁銅合金本身材質過於酥軟（s〇ft)，因 此當測試探針1 〇 6直接接觸接腳墊片丨〇 2以量測電性時， $在接腳塾片102之表面留下測試後之痕跡1〇8。 當進行封裝時，會對半導體底材1〇〇進行切割，於切割時 了避免靜電效應，通常會於含微酸性之環境中進行切割，”、、1222188 Five 'invention description (1), [Technical field to which the invention belongs] _ The present invention relates to a protection method, and in particular to a protection method for a pin gasket. ^ [Prior art] See the first figure for a traditional pin pad structure. A metal conductive layer is formed on the semiconductor substrate 100 as the pin pad 102, where the pin pad _ sheet 102 can be copper Alloy (AlCu), and a plurality of semiconductor elements and circuits are formed on the semiconductor substrate 100. A protective layer 104 is then deposited on the pin pads 102 to protect the semiconductor components and circuits on the semiconductor substrate 100. The protective layer may be formed of a nitrided layer (Nitride). The lithographic etching technology is used to etch a part of the protective layer 104, and the metal area used as the pin pad is excavated by a wet or dry rice engraving method to facilitate subsequent wafer packaging. Before the subsequent chip packaging, the point probe test is usually performed as shown in the second A 第二 to the second b, which uses the test probe to directly contact the foot pad 102 to measure Electricity. Since the traditional pin gasket 102 is formed of an aluminum-copper alloy, the aluminum-copper alloy itself is too soft (s0ft), so when the test probe 1 06 directly contacts the pin gasket 丨 〇2 When the electrical property is measured, $ 10 8 is left on the surface of the pin blade 102 after the test. When packaging, the semiconductor substrate 100 is cut. During the cutting to avoid static effects, cutting is usually performed in a slightly acidic environment. ",,
第4頁 1222188Page 4 1222188
匕θ導致接腳墊片1〇2再次被電解，亦即會從痕跡1〇8處 冉彺下侵蝕。一旦此侵蝕深度過大，亦即形成如第三圖所 示之If况，部分之半導體底材1〇〇會被暴露出來而影響電性 表現’尤其隨著接腳墊片面積越做越小之情形下，此 況會越來越嚴重。 【發明内容】 本發明的主要目的就是在提供一種避免接腳墊片再次被侵_ 钱之保護方法，以降低接腳墊片於後續封裝製成中被侵 餘，進而增接腳墊片之良率。 本發明的另一目的在提供一種接腳墊片之保護方法，以減 少接腳墊片被侵蝕，導致接腳墊片接觸電阻增高。 根據以上所述之目的，本發明提供了 一種接腳墊片之保護 方法，首先於半導體底材上形成一金屬導電層。之後在金 屬導電層上沈積一層保護層，並將部分之金屬導電層暴露 出以形成接腳墊片。接著於進行完點探針量測後，於接腳 墊片與保護層之表面形成一有機保護層，作為阻擋層，以 降低切割製成對接腳墊片之影響。 【實施方式】 在不限制本發明之精神及應用範圍之下，以下即以一實施 例，介紹本發明之實施；熟悉此領域技藝者，在瞭解本發Dagger θ causes the pin gasket 102 to be electrolyzed again, that is, to erode from the trace 108. Once this erosion depth is too large, that is, if conditions are formed as shown in the third figure, a part of the semiconductor substrate 100 will be exposed and affect the electrical performance. Especially as the area of the pin pad becomes smaller and smaller Under the circumstances, this situation will become more serious. [Summary of the Invention] The main purpose of the present invention is to provide a method for protecting the pin pads from being invaded again, so as to reduce the invasion of the pin pads in subsequent packaging and increase the number of pin pads. Yield. Another object of the present invention is to provide a method for protecting a pin pad, so as to reduce the erosion of the pin pad, resulting in an increase in the contact resistance of the pin pad. According to the above-mentioned object, the present invention provides a method for protecting a pin pad. First, a metal conductive layer is formed on a semiconductor substrate. A protective layer is then deposited on the metal conductive layer, and a portion of the metal conductive layer is exposed to form a pin pad. After the point probe measurement is completed, an organic protective layer is formed on the surface of the pin pad and the protective layer as a barrier layer to reduce the effect of cutting on the pin pad. [Embodiment] Without limiting the spirit and application scope of the present invention, the following is an example to introduce the implementation of the present invention; those skilled in the art will understand the present invention.
1222188 五、發明說明（3) 明之精神後，當可應用本發明接腳墊片之保護方法於各種 不同之封裝過程中。以避免接腳墊片於後續封裝製成中再 被侵蝕，進而增接腳墊片之良率，同時避免接腳墊片接觸 電阻增高。本發明之應用當不僅限於以下所述之較佳實施 例0 參見第四圖所示，半導體底材2〇〇上形成一金屬導電層，其 係為鋁銅合金（AlCu)作為接腳墊片202。之後在接腳墊片 202上以化學氣相沈積法（CVD)沈積一層保護層 204(Passivation Layer)，一 般為氮化矽層（Nitride)。《 之後覆蓋一層光阻層（圖中未展示出）於保護層 204 (Passivation Layer)上，利用微影蝕刻技術以定義出 一做為接腳墊片之區域，接著以該光阻層為罩幕，並以濕 式或乾式蝕刻法蝕刻未被光阻層保護之保護層2 〇 4，以形成 接腳墊片 202 (Bond pad)。 接著會進行如第五A圖至第五B圖所示之點探針測試以量測 電性，一測試探針2 〇 6直接接觸接腳墊片2 0 2以量測電性。 由於接腳墊片202係由鋁銅合金所形成，因為鋁銅合金本身 材質過於酥軟（Soft)，因此當測試探針206直接接觸接腳墊 片2 02以量測電性時，常會在接腳墊片2〇2之表面留下測試 後之痕跡2 08。傳統上若以此結構進行後續之切割，由於通 常會於含微酸性之環境中來進行切割，如此會導致接腳墊 片202再次被電解。 請參閱第六圖所示，本發明為了避免接腳墊片2〇2再次被電 解，會於完成點探針之量測後，於接腳墊片2〇2與保護層1222188 V. Description of the invention (3) After the spirit of the Ming, the protection method of the pin pad of the present invention can be applied in various packaging processes. In order to prevent the pin pads from being eroded in the subsequent packaging, the yield of the pin pads is increased, and the contact resistance of the pin pads is not increased. The application of the present invention is not limited to the preferred embodiment described below. Referring to the fourth figure, a metal conductive layer is formed on the semiconductor substrate 2000, which is an aluminum copper alloy (AlCu) as a pin pad. 202. Thereafter, a passivation layer 204 (typically a silicon nitride layer) is deposited on the pin pad 202 by a chemical vapor deposition (CVD) method. << Then cover a photoresist layer (not shown) on the protection layer 204 (Passivation Layer), use lithography etching technology to define a region as a pin pad, and then use the photoresist layer as a cover And a wet or dry etching method is used to etch the protective layer 204 that is not protected by the photoresist layer to form a bond pad 202 (Bond pad). Next, the point probe tests shown in Figures 5A to 5B will be performed to measure electrical properties. A test probe 2 06 directly contacts the pin pad 202 to measure electrical properties. Because the pin gasket 202 is formed of an aluminum-copper alloy, and because the material of the aluminum-copper alloy itself is too soft (Soft), when the test probe 206 directly contacts the pin gasket 202 to measure electrical properties, it is often connected to the connector. The surface of the foot washer 002 left a trace after the test 08. Traditionally, if subsequent cutting is performed with this structure, the cutting pad 202 will be electrolyzed again because it is usually cut in a slightly acidic environment. Please refer to the sixth figure. In order to prevent the pin pad 2 from being electrolyzed again in the present invention, after the point probe measurement is completed, the pin pad 2 and the protective layer are protected.
第6頁 1222188 五、發明說明（4) 204之表面先行成長一層有機保護層210，其中此有機保護 層210可利用旋轉塗佈（Spin )之方式、噴塗（spread )之 方式或印刷（print)之方式來形成，而此有機保護層21〇 之材料為苯並三唑（Benzotriazoles)或苯並味吐 (Benzimidazoles)，且所形成之厚度約為1〇〇〇埃至 m ° 接者再進行後續之晶片切割製成，此時，由於接腳墊片202 之表面具有一層有機保護層210，且此有機保護層21〇對於 為酸性之環境具有良好之抵抗性，因此在晶片之切割製程 中，對於接腳墊片202可提供良好之保護性。換句話^說，接 腳墊片202不會在切割製程中再次電解，因此接腳墊片2〇2 於點探針測試後所遺留之痕跡208不會再次被侵蝕而暴露出 半導體底材200之上表面，增加接腳墊片接觸電阻，而影響 接腳墊片之良率。且另一方面，在完成晶片切割後，會進 行後續之晶片黏接（die mount )製程，而於本製程中，會 使用高溫進行烘烤，此高溫製程會蒸發本發明所形成之有曰 機保護層210 ,換句話說，本發明並不要求另一道額外製程 來移除有機保護層210，因此可節省製程步驟，而不影響 續之製程進行。 ^據上述，由於傳統方法於完成點探針量測後即進行切割 製成，且由於此切割製程係在微酸性之環境中進行，亦^ 成由链銅合金（AlCu)所形成之接腳墊片再行電解，進而暴 露出半導體底材之上表面，而影響電性。但是本發明方法 於兀成點探針量測於即進行切割製成，會先於接腳墊片與Page 6 1222188 V. Description of the invention (4) The surface of 204 is first grown with an organic protective layer 210. The organic protective layer 210 can be spin-coated, spray-coated, or printed. The organic protective layer 21 is made of Benzotriazoles or Benzimidazoles, and the thickness of the formed organic protective layer 21 is about 1000 Angstroms to m °. Subsequent wafer dicing is made. At this time, since the surface of the pin pad 202 has an organic protective layer 210, and the organic protective layer 21 has good resistance to an acidic environment, it is used in the wafer dicing process. It can provide good protection for the pin pad 202. In other words, the pin pad 202 will not be electrolyzed again during the cutting process, so the trace 208 left by the pin pad 202 after the point probe test will not be eroded again to expose the semiconductor substrate. The top surface of 200 increases the contact resistance of the pin pad, which affects the yield of the pin pad. On the other hand, after the wafer is cut, the subsequent die mount process will be performed. In this process, high temperature will be used for baking. This high temperature process will evaporate the organic matter formed by the present invention. In other words, the protective layer 210 does not require another additional process to remove the organic protective layer 210, so the process steps can be saved without affecting the subsequent processes. ^ According to the above, because the traditional method is cut after the point probe measurement is completed, and because this cutting process is performed in a slightly acidic environment, it also becomes a pin formed by a chain copper alloy (AlCu) The gasket is further electrolyzed, thereby exposing the upper surface of the semiconductor substrate and affecting the electrical properties. However, the method of the present invention is cut and measured immediately after the measurement with the Wucheng point probe.
第7頁 1222188 五、發明說明（5) 保護層之表面形成一有機保護層，作為阻擋層，因此可降 低切割製成對接腳墊片之影響。此外在本發明之製程中，. 由於所形成之有機保護層，於後續之封裝過程或晶片黏接 (dje mount)過程中，會因所加之高溫而蒸發散逸，因此 不目對後續製程造成任何影響。 月佳實施例揭露如上、然其並非用以限 範圍内，此技藝者’在不脫離本發明之精神和 圍當視後二二由咬ί之更動與潤飾，因此本發明之保護範 设附之申請專利範圍所界定者為 1222188 圖式簡單說明 為讓本發明之上述和其他目的、特 懂，下女蛀與 於从與说九丨^ 和優點能更明顯易 1里 卜文特舉一較佳實施例，並配人斯似, 明如下： 此σ所附圖式，作詳細說 第一圖繪示一傳統的接腳墊片結構。 至第二Β圖所示為以點探針測試電性之流程。 圖所示為於切割後部分之半導體底材被暴露出來之情 第四圖所示為接腳墊片結構。 第五Α圖至第五β圖所示為以點摈 批μ φ 性之流程。 探針測試本發明接腳塾片電 第六圖所示為本發明於完成點探 ^拉咖轨Η 豳仅冰a > * 休針之量測後，於接腳整月 與保護層之表面成長一層有機保 篁、』傻 籩層之概略圖。 【元件代表符號簡單說明】Page 7 1222188 V. Description of the invention (5) An organic protective layer is formed on the surface of the protective layer as a barrier layer, so the effect of cutting on the pin gasket can be reduced. In addition, in the process of the present invention, due to the formed organic protective layer, during the subsequent packaging process or dje mount process, it will evaporate due to the added high temperature, so it does not cause any damage to the subsequent process. influences. The embodiment of Yuejia is disclosed as above, but it is not intended to be used within a limited scope. This artist can be changed and retouched without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is attached The scope of the patent application is defined as 1222188. The diagram simply explains that in order to make the above and other purposes and special understanding of the present invention, the next son-in-law and Yu Conghe said that the advantages can be made easier. The preferred embodiment is similar to the following, and is as follows: The figure shown in the figure σ is described in detail. The first figure shows a conventional pin pad structure. Figure 2 through Figure 2 show the flow of testing electrical properties with a point probe. The figure shows the exposed part of the semiconductor substrate after cutting. The fourth figure shows the pin pad structure. Figures 5A to 5B show the flow of batching μ φ with dots. Probe test of the pin of the present invention. The sixth figure shows the probe at the completion point of the present invention. 拉 Caffe track Η only ice a > * After the measurement of the pin, the pin and the protective layer A schematic diagram of a layer of organic protection and a silly layer growing on the surface. [Simple description of component representative symbols]
100和200半導體底材 102和202接腳墊片 104和204保護層 1 0 6和2 0 6測試探針 1 0 8和2 0 8痕跡 21 0有機保護層100 and 200 semiconductor substrates 102 and 202 pin pads 104 and 204 protective layer 1 0 6 and 2 0 6 test probe 1 0 8 and 2 0 8 traces 21 0 organic protective layer