TWI220757B - NAND flash memory transformation circuit - Google Patents

Abstract

An NAND flash memory transformation circuit is suitable for a circuit with NOR-gate interface. The major feature is the NAND flash memory can be compatible to NOR-gate memory interface by coupling the NAND flash memory a transformation circuit. The purpose of using the NAND flash memory to replace the NOR flash memory is achieved.

Description

1220757 V. Description of the invention (l) 1. Technical field to which the invention belongs: The present invention relates to flash memory circuit technology, and more particularly to a conversion circuit of a reverse flash memory (N A N D f 1 a s h). 2. Prior technology:

Flash memory (F 1 ash M em ry) is currently widely used due to its lightness, thinness, shortness, smallness, and non-volatile characteristics, coupled with its fast access speed and increasingly reasonable ^ cells. It is used in various fields, such as mobile computers, embedded systems, and various consumer electronics products such as: digital cameras, MP3 PUyer, Set_Top, Boxes, mobile phones, personal digital assistants, and so on. The flash memory can be divided into NOR flash memory (NOR flash memory) and NAND flash memory (nand fiash memory) in application. Among them, the characteristics of inverse or idle flash memory are XIP (execute In Place), so that the application can run directly in the flash memory 'without having to read the code into the system. The transfer efficiency of the anti-or flash memory is very high, which is very cost-effective in the small capacity of ^ ^ ~ 4Mβ, but it is very low. Λ 4 ^ + 疋The erasing speed greatly affects the performance, but in contrast to the flash flash fp 彳 咅 』one-the characteristics of the n ° body can provide a very high single

Yuan, &, degree ’can reach the South storage poor Wy ^ 砵 砵 in the degree, and the speed of writing and erasing is also very fast. The difficulty of applying the anti-flash flash I # Μ | "7 fe system is the management of f ash and the need for a special system interface. ^ ^ ^ The size of the beans is almost half of the size of the anti-OR gate. The production process f_π and the scripture are early, so the cost is relatively small.

0706-10225TWF (N1); chent f.ptd p. 4 1220757

Low 'and exist in the memory but because of the anti-gate, especially the designed crystal plane, but in the current market, the memory capacity of many people's access interface memory is also flash memory. Considering that you want to go back to the brake fast, and learn to use the required flash or brake flash in the performance is not good or the brake is not complete, and hope to reflect the flash memory. Memory also replaces anti-OR gate memory. OR memory (NOR f flash memory used in anti-OR software to achieve a competitive, flash memory is a company 1 ash). Therefore, flash memory is anti-flash. III. Summary of the Invention:

In view of this, an object of the present invention is to provide an inverse gate flash memory (NAND fUsh) conversion circuit. By coupling an inverse gate memory to a conversion unit, it can be connected to an inverse gate memory. The interface is compatible to achieve the purpose of replacing the anti-or flash memory with the anti-flash memory.

In order to achieve the above object, the present invention provides a NAND flash memory (NAND flash) conversion circuit, which includes a NAND flash memory (NAND f 1 ash) conversion circuit. The system includes: a memory controller A transmission interface 'includes a transmission unit and a second transmission unit, the first transmission unit is used to transmit the anti-OR gate memory interface signal and the anti-OR gate memory interface output by the memory controller; A signal to the memory controller; a second transmission unit transmits a waiting control signal to the memory controller; a conversion unit receives the anti-OR memory interface signal and translates it into an anti-NOR gate 5 Ji Yi body interface signal output; and an anti-gate recorder, the body, is to receive the anti-gate control signal for corresponding processing operations.

0706-10225TWF (Nl); rentf-ptd

1220757 V. Description of the invention (3) ^ --- In order to make the present invention clearly understandable, the following special mentions-ΐ and other purposes, ㈣, and advantages can be described in more detail as follows: The drawing shows the method of “four consecutive implementations”: The first figure is based on the memo ^ conversion circuit} — 2 months and the flash memory (NAND nash-memory controller 10 ::; Schematic diagram of the circuit block, including the inverse and gate memory 13. Transmission interface 11 Conversion unit 12 and-Memory controller 1 〇, 仫 m,

End-of-life; 1!. Is used to control the order of data access. The unit 'a frame includes a first transmission unit 110 and a second transmission, and the first transmission unit 110 is used for bidirectional transmission of the anti or false signal; I surface signals' These signals include instructions (for example: Read / write / clear / reset instructions) and data; the second transmission unit 111 is used to unidirectionally transmit a waiting control signal (Wa it-η) to the memory controller 10. The conversion unit 12 is implemented in this embodiment by a complex programmable logic element: Complex Programmable Logic Device (CPLD)

Achieved, it can receive the anti-gate memory interface control command transmitted by the first transmission unit 110 and translate it into the anti-gate memory interface command; or translate the received anti-gate memory interface command to translate After being inverted or gated, a memory interface command is output to the first transmission unit 110. In addition, when the conversion unit 12 receives the inverse OR gate transmitted by the first transmission unit 110, the interface will provide the above-mentioned waiting control signal (Wa it _n) and pass the second transmission order. Wu 1 1 1 Output to memory control

〇706-l〇225TWF (Nl); centf.ptd p. 6 1220757

In the device 10, the memory control and the memory 13 are coupled to the conversion unit 12 and the memory interface command is output after the memory interface command is ready (for actual operation, for example, the After inputting the address of the item to the read address, it will wait for it to enter the waiting state; and then return to the gate memory 1 3, this (Column address), the row and gate memory 1 3 are processed to the conversion unit. In 1 2, then when the conversion unit 12 receives (Wait-η) and pulls it to the high level, the memory controller 10 completes the controller 10 and enters the waiting state. It is transmitted through a reverse and gate memory. The interface 1 4 is used to receive a counter-corresponding action transmitted by the conversion unit 丨 2 and a signal is completed to the conversion unit 12.

Perform a reading operation in the memory controller ^ 〇 In the conversion unit 12, when the conversion unit 12 receives the to-be-controlled §fL number (W ait — η) and pulls it to a low potential, the memory controller 12 inputs a plurality of pen commands to some The instruction includes data such as read instruction, row address, etc .; after reverse, the above-mentioned ready (n) message is returned and the data to be read is transmitted to the conversion unit! 2 After reading the data, it is about to wait for the control signal. Cancel its special waiting evil ’and turn the lean material out to record a single reading action. Figure 2 is a schematic block diagram related to the processing of translation actions in the conversion unit 12 in Figure 1, which includes a reverse or gate interface processing block 丨 2 0 and a reverse and gate interface processing block 1 2 1.

The anti-gate interface processing block 1 2 0 receives the anti-gate memory interface signal transmitted by the first transmission unit 1 10, and after processing, converts and outputs the corresponding anti-gate signal to the anti-gate interface processing area. Block 1 2 1 is used to instruct the anti-gate memory 1 3 to perform corresponding actions (for example: read or write), and the anti-gate interface handles block 1 2 1 to prepare a ready signal before completing the action.

0706-10225TWF (N1); rent f.ptd page 7 1220757 V. Description of the invention (5) (NAND READY) potential branch 5 ~ # 士 — Electricity to low potential measures to indicate anti-gate memory 1 3 Processing Before the ready signal (NAND — READY) becomes high, the OR gate interface processing block 120 will pull the waiting control signal (Wai t — n) to a low potential. The anti-gate interface processing block 121 is to output the corresponding anti-gate signal to the anti-gate threshold according to the anti-gate signal. 〇 ## Jiuhe gate memory 13 to control the anti-gate memory 13 Complete the corresponding action. Before the action is completed, the potential of the ready signal (NAND — READY) is 57 — & w The current level of the claw is pulled to a low level to inform the anti-or gate interface. The block 12G is currently being processed, waiting for After the gate interface processing block i2i has completed the action, the potential of the ready signal (NAND — READY) will be pulled to a high level to wait for the next input command. —The third diagram is the timing sequence of the reading operation in the conversion unit of the present invention. The figure 5 shows that the memory chip signal (norf sh_cs_n) is pulled to a low potential to enable the address (Add — 丨) Turn on via the memory address pin of the NOR gate (norfsh — addr), and then wait for the control signal (Wait — pull from high to low for 4 volts to notify the memory controller to enter the wait state; at this time The memory controller inputs a plurality of instructions (CMD〇CMD3) into the inverse gate memory output / in terminal (nandfsh_i〇). When the inverse gate memory processes these instructions and obtains the data (Data_n, it will The counter-ready signal Uandfsh-rdy —n) is pulled from a low potential to a high potential 'to inform that the data to be read has been obtained. Next, the data (Data-I) is sent to the anti-OR gate data bus Uandfsh — data ), Wait for the control signal (Wait n) to be pulled from low to high, and notify the memory controller to end the waiting state.

1220757 Fifth, the invention description (6) (Data-1) is sent, that is, the action of reading data is completed. With the above, the present invention can indeed connect the inverse gate flash memory to the interface of the inverse or gate flash memory through a conversion unit, thereby achieving the effect of reducing the system cost. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. _

0706-10225TWF (Nl); chentf.ptd Page 9 1220757 Brief description of the diagram Figure 1 shows the circuit of a preferred embodiment of the NAND f 1 sh conversion circuit of the present invention Block diagram; Figure 2 is a block diagram of the internal components of the conversion unit in Figure 1; and Figure 3 is a timing diagram of the read operation in the conversion unit of the present invention. Explanation of related symbols: 1 0 ~ memory controller; 11 ~ transmission interface; 1 1 0 ~ first transmission unit; 1 1 1 ~ 2 second transmission unit; 1 2 ~ conversion unit; 1 3 ~ anti-gate memory; 1 4 ~ reverse and gate memory transmission interface; 1 2 0 ~ reverse or gate interface processing block; 1 2 1 ~ reverse and gate interface processing block.

0706-10225TWF (N1); chent f.ptd p. 10

Claims (1)

1220757 VI. Scope of patent application 1. A reverse flash memory (NAND f 1 ashmem 0ry) conversion circuit, including: a memory controller; a transmission interface, including a first transmission unit and a second A transmission unit, the first transmission unit is configured to transmit an anti-OR gate memory interface signal output from the memory controller and return an anti-OR gate memory interface signal to the memory controller; the second transmission unit is A waiting control signal to be transmitted to the memory controller; a conversion unit for receiving the inverse OR gate memory interface signal and translating it into an inverse OR gate memory interface signal output; and an inverse OR gate memory interface Receive the inverse gate signal for corresponding processing operations. 2. The inverse gate flash memory conversion circuit as described in item 1 of the scope of the patent application, wherein the inverse gate memory system is coupled to the conversion unit through an inverse gate memory transmission interface. 3. As described in the patent application scope of the inverse gate flash memory conversion circuit, when the inverse gate circuit has processed the instruction of the inverse gate control signal, it will return a ready (ready) Signal to the conversion unit. 4. The NAND flash memory conversion circuit described in item 1 of the scope of patent application, wherein the conversion unit further includes: a NAND flash interface processing block, which processes and converts all NAND flash memory interface signals. Output a corresponding anti-gate signal output; and the anti-gate interface processing block, which receives the anti-gate signal and outputs the corresponding anti-gate command to the anti-gate memory, thereby controlling the anti-gate memory 0706-10225TWF (N1); chent f.ptd page 11 1220757 t. The scope of patent application is to complete the corresponding action. 5 · — NAND flash memory (N A N D f 1 a s h me in 〇 r y) conversion circuit, including: a conversion unit, is a signal and translates it into NAND memory operation. Receive the input of the anti-NOR gate memory interface and the gate memory interface signal output from the external input; and, receive the anti-gate gate interface signal for corresponding processing 6 · The anti-gate circuit as described in the first scope of the patent application The flash memory conversion circuit further includes: a first memory and a transmission of the first OR gate memory memory controller waiting for a control signal 7. If a circuit is applied for replacement, its interface is coupled to 8. If a circuit is applied for replacement, ， Return to 9 · If you apply for a circuit replacement, the inverse OR gate controller interface, including the signal of the transmission unit interface; the number is transmitted to the patent application, the conversion and the conversion form, please the patent application, the conversion and the transmission. A ready to request the conversion interface processing in the patent: and includes a first transmission unit and a second transmission order to transmit the reverse and return reverse OR gate memory interface signals output by the memory controller to the record The two transmission units are controlled by the memory output by the conversion unit. The flip-flop flash memory memory system described in item 6 transfers elements via a flip-flop memory. The flash memory transfer of the inverse gate described in item 6 above refers to the ready signal of the inverse gate control signal to the conversion unit. The NAND flash memory transfer unit described in item 6 further includes: a block that transfers all the information of the NAND flash memory interface. 0706-10225TWF (Nl); entf.ptd Page 12 1220757 VI. The patent application scope number is processed and converted to output a corresponding anti-gate signal output; and the anti-gate interface processing block is to receive the anti-gate signal The corresponding inverse gate signal is output to the inverse gate circuit to control the inverse gate circuit to complete the corresponding action. 0706-10225TWF (Nl); chentf.ptd p. 13