594027 五、發明說明（l) 【發明所屬之技術領域】 法，本發明係有關於一種探觸積體電路之探測頭製造方 ’ 別係有關於一種可變化探測單元數量之探測頭製造 万法。 【先前技術】 I知探測卡〔probe card〕係供組配於一積體電路測 古=備，探測卡係包含有一探測頭〔pr〇be 〕，其具 夕排精密微小之探針，用以探觸待測積體電路之接觸 /如半導體晶圓之銲墊、凸塊或捲帶封裝之引腳，因此 木測頭係為探測卡之重要關鍵零配件。 習知探測頭之製造方法係在一矽基板上形成各種形狀 2針或凸出導點’當不同探測卡尺寸或是需要待測積體 路之疋件數量不同，探測頭均應個別製造設計適當之線 :ί相同尺寸之探測頭需要在不相同之矽基板上分別製 ί二俨=5變化’特別在小樣探測•，可能無法製作出 僅心探觸小量待測積體電路之元件數量之探測頭❹ 古$美ΐ專利第5,689,1 93號係揭示出一種探測頭之製造 =Ϊ叙X探針之製造方法係以打線方式〔wire-bonding〕 將複數個銲線連接於一絕緣基板與一虛基板〔dummy :二’、利用一夾合治具調整該銲線之形狀，並裁 A絡^靠近在該虛基板之—端，以構成探針，但未述 ”緣基板用以連接該些探針之線路配置，且未揭示如 何大賣而彈性地製造探測頭之方法。 【發明内容】 594027 五、發明說明（2) 本發明之主要目的係在於提供一種探觸積體電路之探 測頭製造方法，利用選擇性切割一接合有探針之矽基板， 該些擇性切割道係形成於該矽基板之探觸單元，以供選 擇性切割成適當尺寸之探測頭，以供各式尺，寸之探測卡袓 合，具有製作多種探觸單元數量變化之探測頭功效。、 本發明之次一目的係在於提供一種探觸積體電路之探 測頭製造方法，利用一矽基板之探觸單元與外導接區之配 置，並以線路連接該探觸單元之探針接墊與外導接區之 接墊，而形成複數個可選擇切割道於該些探觸單元之間連 該些可選擇切割道係不具有該些線路導通通過，以達到. 擇性切割成不同尺寸探測頭之功效。 依本發明之探觸積體電路之探測頭製 法，其 之步驟有： 六匕3 “I J ί供：矽基板」’所提供之矽基板係包含有至少- 之外導接區，每一探觸單元係對應於一 有複數個探針接墊，該外導接Fθ 士: j積體電路並具 接㈣U 係具有複數個與對應探針 接墊線路連接之連接墊，其中在該些探觸 門 有複數個可選擇切割道，較佳地 二 該些外導接區相垂直； 肖些可選擇切割道係與 「形成探針於石夕基板装彳▲玄 石夕基板之該些探針接墊，該個探針接合於該 導線架或捲帶之探針載體承載傳送；及〇之前係利用一如 「選擇性切割矽基板」，其係分斷至少-可選擇切割 594027 五、發明說明（3) 道，由該陣列區塊構成至少一具有預定數量探觸單元之探 測頭。 【實岭方式】 參閱所附圖式，本發明將列舉以下之實:施例說明。 請參閱第1圖，依本發明之一具體實施例所例舉之探 觸積體電路之探測頭製造方法係主要包含有「提供一石夕基 -板」11、「形成探針於矽基板」1 2及「選擇性切割梦基 板」1 3等步驟。594027 V. Description of the invention (l) [Technical field to which the invention belongs] method, the present invention relates to a probe manufacturing method for a probe integrated circuit ', and also relates to a method for manufacturing a probe with a variable number of detection units. . [Previous technology] I know that the probe card is for use in an integrated circuit to measure the temperature of the device. The probe card contains a probe head [pr〇be], which has a precision probe with a small row. To probe the contact of the integrated circuit to be tested / such as the pads, bumps or taped pins of a semiconductor wafer, the wooden probe is an important key component of the probe card. The manufacturing method of the conventional probe head is to form 2 pins or protruding guide points of various shapes on a silicon substrate. When the size of the probe card or the number of pieces that need to be measured is different, the probe head should be individually manufactured and designed. Appropriate line: Probes of the same size need to be made separately on different silicon substrates. 俨 = 5 changes', especially in small sample detection. • It may not be possible to make a component that only touches a small amount of integrated circuit under test. The number of probe heads ❹ US $ 5,689,193 discloses a method of manufacturing a probe head: the method of manufacturing X probes is to wire-bonding a plurality of bonding wires to one Insulating substrate and a dummy substrate [dummy: two ', use a clamping fixture to adjust the shape of the bonding wire, and cut A network ^ close to the-end of the dummy substrate to form a probe, but the edge substrate is not described The line configuration used to connect these probes does not disclose how to sell the probe head flexibly. [Summary of the Invention] 594027 V. Description of the Invention (2) The main purpose of the present invention is to provide a probe product. Manufacturing of probes for body circuits A method is to selectively cut a silicon substrate bonded with a probe, and the selective cutting lines are formed on a touch unit of the silicon substrate for selective cutting into a probe with an appropriate size for various rulers. -Inch detection cards are combined, which has the effect of making a variety of detection heads with varying numbers of detection units. A second object of the present invention is to provide a method for manufacturing a detection head for a contact integration circuit, which uses a silicon-based detection unit The configuration is connected to the outer conducting area, and the probe pads of the probing unit and the pads of the outer conducting area are connected by lines, so as to form a plurality of selectable cutting paths between the probing units to connect the Selecting the cutting line does not have the continuity of these lines to achieve the effect of selective cutting into probes of different sizes. According to the probe head manufacturing method of the probe integrated circuit of the present invention, the steps are: six daggers 3 "IJ For: "Silicon Substrate" The provided silicon substrate system includes at least-outer conductive areas. Each probe unit corresponds to a plurality of probe pads. The external leads are Fθ. The circuit is connected with A plurality of connection pads connected to the corresponding probe pad circuit, among which there are a plurality of selectable cutting paths in the touch doors, preferably the two outer guide areas are perpendicular to each other; "The probes are formed on the Shixi substrate and the probe pads on the Xuanshixi substrate are formed. The probe is bonded to the probe carrier of the lead frame or tape. "Selective cutting of silicon substrates" is to cut at least-optional cutting 594027. 5. Description of the invention (3). The array block constitutes at least one probe with a predetermined number of probe units. [Solid Ridge Mode] With reference to the attached drawings, the present invention will enumerate the following facts: Example description. Please refer to FIG. 1. A method for manufacturing a probe head for a touch sensor circuit according to a specific embodiment of the present invention mainly includes “providing a stone substrate-board” 11, and “forming a probe on a silicon substrate”. 1 2 and "selective cutting of the dream substrate" 1 3 and other steps.
於「提供一矽基板」11步驟中，請參閱第2及3圖，所 提供之石夕基板20係包含有至少一陣列區塊21〔array area〕，較佳地，該矽基板2〇係為一半導體晶圓，請參閱 第3圖，每一陣列區塊21係具有複數個探觸單元22、23In the 11 steps of "providing a silicon substrate", please refer to Figs. 2 and 3. The provided Shixi substrate 20 includes at least an array area 21, preferably, the silicon substrate 20 is It is a semiconductor wafer. Please refer to FIG. 3. Each array block 21 has a plurality of probe units 22 and 23.
〔probing unit〕以及在兩側之外導接區24 ,在本實施例 中，《亥些彳未觸單元係區分為複數個第一探觸單元22與複數 個第二探觸單元23，其中第一探觸單元22係比第二探觸單 元23更加遠離對應之外導接區24，每一第一探觸單元“或 第二探觸單元23係各對應於一待測積體電路〔如待測晶圓 之晶片〕，第一探觸單元22係具有複數個第一探針接墊 221，第二探觸單元23亦具有複數個第二探針接墊，而 該外導接區24係具有複數個導接上述第一探針接墊221與 ^二探針接墊231之連接墊241，係以積體電路製程形成之 第一線路222連接該些第一探針接墊221至對應之連接墊 241，而第二線路232係連接該些第二探針接墊231至對應 之連接塾241，其中該第二線路232係具有適當之繞線路 594027 五、發明說明（4) ί長使：ΪΠ之線長相等或接近於第-線_之 線，以達到均等之電阻與訊號傳遞速度，供高頻极制， 2該51\區在塊^在該些外導接區24侧邊係形成有切割道' 』切：4,觸單元22、23之間係形成，複數個可選 擇切。】道252，即該些可選擇切割道25 行選擇性切割，該此可選擇切、#9„怂b潺承次°又彳進 忑二』選擇切割道252係與該些外導接區 •24〔側邊之切割道251〕相垂直，且較佳地，上述第一線 路222與第二線路232係不通過該些可選擇切割道252。 =:形成探針於矽基板」丨2步驟中，請參閱第4圖， 4矽基板20上提供一承載有金屬探針w之探針載體 30〔 pin carrier〕，該探針載體3〇係可為一導線架 〔lead frame〕或可撓性捲帶〔flexiMe tape〕，如 Kapton tape，較佳地，該探針載體3〇係為感光性軟膜 〔P^〇t〇Sensitive film〕之捲帶，之後，請參閱第5圖， 在該探針載體30移動定位後，利用熱壓合技術將該些探針 31之結合端以銲料4〇接合於對應之第一探針接墊221與第 二探，接墊231，爾後，請參閱第6圖，利用剪切、照射或 清洗等移除方式移除該探針載體3〇，使得該矽基板2〇上第 一探針接墊221與第二探針接墊231結合有一致高度之探針 31 〇 於「選擇性切割矽基板」1 3步驟十，利用機械刀具或 雷射切割完全分斷該矽基板2〇之切割道251，而選擇性切 割道251則可依預定所需探測頭之尺寸進行選擇性切割 〔請參閱第2圖〕，即可不分斷或加以分斷之，使得至少 594027 五、發明說明（5) —----— 一該些選擇性切割道251係被分斷，故在「選擇性切割石夕 基板j 1 3步驟之後，每一陣列區塊21可形成至少一適當尺 寸之赛測頭〔probe head〕，請參閱第7圖，依本發明製 成之探測頭係包含有一體成型複數個已接令有探針31且具 數量彈性變化之探觸單元22、23，如包含有4x2、4x4、- 4χ8或4χΐ6探觸單元，以適用於不同尺寸之探測卡組 . 合。 ' ^外’本發明並不局限「形成探針於矽基板」1 2步驟 、 選擇性切割矽基板」1 3步驟之順序，在等效性變化 :’亦能先執行「選擇性切割矽基板」13，再執行「形成Φ 衣針於石夕基板」1 2之步驟。 、本發明之保護範圍當視後附之申請專利範圍所界定者 图準’任何熟知此項技藝者，在不脫離本發明之精神和範 内所作之任何變化與修改，均屬於本發明之保護範圍。[Probing unit] and the lead-in area 24 on both sides. In this embodiment, the "untouched units" are divided into a plurality of first probe units 22 and a plurality of second probe units 23, where The first probing unit 22 is farther away from the corresponding outer contact area 24 than the second probing unit 23, and each of the first probing units "or the second probing unit 23 corresponds to a circuit under test [ (Such as the wafer to be tested), the first probe unit 22 has a plurality of first probe pads 221, the second probe unit 23 also has a plurality of second probe pads, and the outer conductive area 24 is provided with a plurality of connection pads 241 for connecting the first probe pad 221 and the second probe pad 231, and is connected to the first probe pads 221 by a first line 222 formed by an integrated circuit process. To the corresponding connection pad 241, and the second line 232 is to connect the second probe pads 231 to the corresponding connection 塾 241, wherein the second line 232 has a proper winding line 594027. 5. Description of the invention (4) ί length makes: the line length of ΪΠ is equal to or close to the line of line-to achieve equal resistance and signal transmission speed ， For high-frequency polar system, 2 The 51 \ area is formed in the block ^ Cutting lines are formed on the side of the outer conductive areas 24 ′ ”Cut: 4, formed between the contact units 22 and 23, a plurality of optional Cut.] Road 252, that is, these optional cutting lines are 25 lines of selective cutting. This optional cutting, # 9 „怂 b 潺 承 次 ° and 彳 进 忑』 Select cutting line 252 and these external guides. The junction area 24 (the cutting line 251 on the side) is perpendicular, and preferably, the above-mentioned first line 222 and the second line 232 do not pass through these optional cutting lines 252. =: Forming a probe on a silicon substrate ”In the 2 steps, please refer to FIG. 4, a silicon probe 20 is provided on the silicon substrate 20 with a probe carrier 30 (pin carrier) carrying a metal probe w. The probe carrier 30 It can be a lead frame or a flexible tape, such as Kapton tape. Preferably, the probe carrier 30 is a roll of photosensitive soft film [P ^ 〇t〇Sensitive film]. After that, please refer to FIG. 5. After the probe carrier 30 is moved and positioned, the bonding ends of the probes 31 are soldered to the corresponding first probe pads 221 and 40 by using a thermocompression bonding technique. The second probe, the pad 231, and then referring to FIG. 6, the probe carrier 30 is removed by cutting, irradiating or cleaning, so that the first probe pad 221 on the silicon substrate 20 is removed. A probe 31 with a uniform height is combined with the second probe pad 231. In the "selective cutting of the silicon substrate", step 13 and ten, the cutting path 251 of the silicon substrate 20 is completely broken by using a mechanical cutter or laser cutting. The selective cutting path 251 can be selectively cut according to the size of the predetermined probe (see Figure 2). ], You can not break or break it, so that at least 594027 V. Description of the invention (5) ---------- These selective cutting lines 251 are broken, so in the "selective cutting Shixi substrate" After j 1 3 steps, each array block 21 can form at least one probe head of an appropriate size. Please refer to FIG. 7. The probe head made according to the present invention includes an integrally formed plurality of connected probe heads. The probe units 22 and 23 with probes 31 and having a quantity elasticity change, such as a 4x2, 4x4, -4χ8 or 4χΐ6 probe unit, are applicable to probe cards of different sizes. Combination. '^ 外' 本The invention does not limit the order of "forming the probe on the silicon substrate" 12 steps, selectively cutting the silicon substrate "1 to 3 steps, and the equivalent changes: 'You can also execute the" selective cutting silicon substrate "13 before executing The steps of "forming Φ needles on Shixi substrate" 12 2. The scope of protection of the present invention shall be determined by those who are defined by the scope of the patent application attached below. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .
第10頁 594027 圖式簡單說明 ^ 【圖式簡單說明】 第1圖··依據本發明之探觸積體電路之探測頭製造流程 “ 圖； 第2圖··依據本發明之探觸積體電路之探測:頭製造方法， 所提供之矽基板示意圖； 第3圖：依據本發明之探觸積體電路之探測頭製造方法， 所提供之矽基板局部放大示意圖； 第4圖··依據本發明之探觸積體電路之探測頭製造方法， 在矽基板上提供一探針載件之截面示意圖； 第5圖：依據本發明之探觸積體電路之探測頭製造方法，，灸 在石夕基板結合該探針載件之探針截面示意圖； 第6圖：依據本發明之探觸積體電路之探測頭製造方法， 在移除該探針載件之後具有探針之矽基板截面示 意圖；及 第7圖·依據本發明之探觸積體電路之探測頭製造方法， 在選擇性切割步驟之後形成探測頭之正面示 圖0 元件符號簡單說明： 11 提供一矽 基 板 12 形 成 探 13 選擇性切 割 矽 基板 20 碎基板 21 陣 列 區 22 第一探觸 單 元 221 第一探針 接 墊 222 第 線Page 594027 Brief description of the diagram ^ [Simplified description of the diagram] Fig. 1 · Manufacturing process of the probe according to the invention of the probe integrated circuit "Figure; Figure 2 ·· The probe integrated product according to the present invention Detection of the circuit: head manufacturing method, schematic diagram of the provided silicon substrate; Fig. 3: Schematic diagram of a partial enlargement of the provided silicon substrate according to the probe head manufacturing method of the probe integrated circuit according to the present invention; The invention provides a probe head manufacturing method for a probe integrated circuit, which provides a schematic cross-sectional view of a probe carrier on a silicon substrate. FIG. 5: A probe manufacturing method for a probe integrated circuit according to the present invention. Sectional schematic diagram of a probe with a substrate and the probe carrier; Figure 6: A schematic diagram of a cross section of a silicon substrate with a probe after the probe carrier is removed according to the method for manufacturing a probe of a probe integrated circuit of the present invention And FIG. 7 · A method for manufacturing a probe head of a touch sensor circuit according to the present invention, forming a front view of the probe head after a selective cutting step. 0 Brief description of component symbols: 11 Provide a silicon substrate 12 shape Probe 13 silicon substrate 20 is selectively cut pieces array substrate 21 of the first region 22 the scanning unit 221 of the first line probe pads 222
針於矽基板 II 塊 路Pin to Silicon Substrate II Block
第11頁 594027 圖式簡單說明 23 第二探 231第二探 24 . *卜導接 251 切割道 30 探針載 觸單元 針接墊 232 區 241 252 件 31 第二線路 連接墊 可選擇切割 探針 道 40 銲料Page 11 594027 Brief description of the diagram 23 Second probe 231 Second probe 24. * Buddy lead 251 cutting path 30 probe contact unit pin pad 232 area 241 252 pieces 31 second line connection pad optional cutting probe Lane 40 solder