TW591726B - A method for manufacturing a chip package - Google Patents

A method for manufacturing a chip package Download PDF

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Publication number
TW591726B
TW591726B TW091134718A TW91134718A TW591726B TW 591726 B TW591726 B TW 591726B TW 091134718 A TW091134718 A TW 091134718A TW 91134718 A TW91134718 A TW 91134718A TW 591726 B TW591726 B TW 591726B
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TW
Taiwan
Prior art keywords
substrate
wafer
scope
carrier board
mold
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TW091134718A
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Chinese (zh)
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TW200409251A (en
Inventor
Gwo-Liang Weng
Shih-Chang Lee
Chun-Chi Lee
Shu-Jung Ma
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Advanced Semiconductor Eng
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Priority to TW091134718A priority Critical patent/TW591726B/en
Publication of TW200409251A publication Critical patent/TW200409251A/en
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Publication of TW591726B publication Critical patent/TW591726B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A method for manufacturing a chip package. Firstly, providing a carrier with a first substrate, a second substrate and at least a support unit wherein the support unit is coupled to the first side of the first substrate and the second side of the second substrate. Chips are established on the first and second substrates. Put a mold on the support unit, wherein the compressed portion of the mold fits the first side of the first substrate and the second side of the second substrate. Infuse a compound into the cavity of the mold, then remove the mold as to expose the compound outside. Finally, divide the support unit to separate the first substrate and the second substrate. That is, the area of the substrates can improve usefully and damage the substrates hardly.

Description

591726 ^ 91134718 年月日 修正 五、發明說明（1) " 一 ---- 發明所屬> & 叮屬之技術領域 一 本發明是有關於一種晶片封裝結構，且特別是有關於 封裝特料之側邊貼近於基板之側邊的晶片封裝結構。 先前技術591726 ^ 91134718 Rev. V. Description of the invention (1) " I ---- The invention belongs > & The technical field of Dingyi-The present invention relates to a chip packaging structure, and in particular, to packaging characteristics A chip package structure in which the side of the material is close to the side of the substrate. Prior art

近年來，隨著電子技術的日新月異，高科技電子產業 的相繼問世，使得更人性化、功能更佳的電子產品不斷地 推陳出新，並朝向輕、薄、短、小的趨勢設計。目前在半 導體製程當中，基板型承載器（substrate type carrier) 是經常使用的構裝元件，其主要分為堆疊壓合式 (laminate)及積層式（build up)二大類型之基板。其中， 基板（substrate)主要由多個圖案化線路層及多個絕緣層 交替疊合所構成，且基板之表面具有多個接點，作為連接 晶片或外部電路之輸出入媒介。由於基板具有佈線細密、 組裝緊湊以及性能良好等優點，已成為晶片封裝（ch i p Package)結構中不可或缺的構裝元件之一。In recent years, with the rapid development of electronic technology, the high-tech electronic industry has come out one after another, making more humanized and better-functioning electronic products continue to be introduced, and they are designed to be light, thin, short, and small. At present, in the semiconductor manufacturing process, the substrate type carrier (substrate type carrier) is a frequently used structural component, which is mainly divided into two types of substrates: laminated and build up. Among them, a substrate is mainly composed of a plurality of patterned circuit layers and a plurality of insulating layers alternately stacked, and the surface of the substrate has a plurality of contacts, which serve as an input / output medium for connecting a chip or an external circuit. Because the substrate has the advantages of fine wiring, compact assembly, and good performance, it has become one of the indispensable components in a chip package structure.

此外，每一顆由晶圓（wafer)切割所形成的裸晶片 (d 1 e )，經由黏晶（d i e b ο n d )的步驟，將裸晶片黏著在上 述的基板上，接著裸晶片上所形成之焊，（B〇nding Pad) ’藉由導線（Wire)及/或焊球（Bump)之接合，將裸晶 片之焊墊與基板之接點電性連接，之後再進行封膠的步 驟’以一封裝材料將裸晶片包覆著，而晶片封膠之目的在 於防止裸晶片受到濕氣、熱量、雜訊的影響，並保護裸晶 片’如此即完成晶片封裝之製程。In addition, each bare wafer (d 1 e) formed by wafer dicing is adhered to the above-mentioned substrate through a dieb step, and then formed on the bare wafer. Bonding Pad (Bonding Pad) 'By bonding the wires (Wire) and / or solder balls (Bump), the pads of the bare chip are electrically connected to the contacts of the substrate, and then the step of sealing is performed.' The bare wafer is covered with a packaging material, and the purpose of the wafer sealing is to prevent the bare wafer from being affected by moisture, heat, and noise, and to protect the bare wafer, thus completing the wafer packaging process.

10036twfl.ptc 第8頁 591726 ----一案號 91134718___年 月_g_修正__ 五、發明說明（2) ^ 第1圖繪示習知的基板型承載器（以下稱為載板）之示 意圖。請參照第1圖，先提供一載板丨〇 〇，而載板丨〇 〇係由 多個基板1 0 2所構成，相鄰二基板1 〇 2之側壁部份1 〇 4之間 具有一槽孔1 0 3，以分隔兩相鄰之基板丨〇 2。此外，每一基 板1 0 2之表面具有多個接點丨〇 6，排列於基板丨〇 2之表面 上’作為連接晶片或外部電路之輸出入媒介。 請參考第2A〜2C圖，其中第2A〜2B圖繪示第1圖之載板 應用於一晶片封裝製程的剖面示意圖，第2 C圖繪示晶片封 裝結構的俯視圖。10036twfl.ptc Page 8 591726 ---- Case No. 91134718 _ month_g_correction__ V. Description of the invention (2) ^ Figure 1 shows a conventional substrate-type carrier (hereinafter referred to as a carrier board) ). Please refer to FIG. 1. A carrier board is provided first, and the carrier board is composed of a plurality of substrates 102. A side wall portion 104 of two adjacent substrates 10 is provided with a substrate. The slot 10 is used to separate two adjacent substrates. In addition, the surface of each of the substrates 102 has a plurality of contacts, arranged on the surface of the substrate, as an input / output medium for connecting a chip or an external circuit. Please refer to Figs. 2A to 2C, where Figs. 2A to 2B are schematic cross-sectional views of the carrier plate of Fig. 1 applied to a chip packaging process, and Fig. 2C is a top view of the chip packaging structure.

習知的晶片封裝之製程係先將晶片i J 〇分別黏著在載 板100之每一基板102上，而晶片no上所形成之焊墊 112(Bonding Pad)藉由導線114之接合，使得晶片11〇之焊The conventional wafer packaging process is to first adhere the wafer i J 〇 to each substrate 102 of the carrier board 100, and the bonding pad 112 (bonding pad) formed on the wafer no is bonded by the wire 114, so that the wafer 11 o welding

墊1 1 2與基板1 〇 2之接點1 〇 6電性連接。之後，將欲封膠之 晶片1 1 0以及載板1 〇 〇的成品一起放置於壓模機之封膠模具 1 0中，以進行封膠的步驟，此時，先將預熱好之熔融的封 裝材料1 2 0比如為樹脂，經由壓模機的膠道（未繪示）灌入 封膠模具1 0之模穴1 2中，等到樹脂充填而冷卻硬化於每一 基板102上，並包覆著晶片11〇之後，再脫模取出已封膠之 晶片1 1 0以及載板1 〇 〇的成品，即完成第2 b圖所示之結構。 此外’已封膠之成品經由切單（S i n g u 1 a t i 〇 n )的步驟，將 載板1 0 0以衝壓（P U n c h )或切割的方式切成多個單一結構， 如此即得到第2 C圖所示之晶片封裝結構。 如第2A〜2C圖所示，值得注意的是，在進行封膠之步 驟時，習知的封膠模具1 〇之壓合部丨4係壓住相鄰二基板The pads 1 12 are electrically connected to the contacts 106 of the substrate 102. After that, the wafer 110 to be sealed and the finished product of the carrier board 100 are placed together in the sealing mold 10 of the compression molding machine to perform the sealing step. At this time, the preheated melt is first melted. The packaging material 1 2 0 is, for example, resin, which is poured into the cavity 12 of the sealing mold 10 through the glue channel (not shown) of the compression molding machine, and is cooled and hardened on each substrate 102 until the resin is filled, and After the wafer 110 is covered, the finished wafer 110 and the carrier 100 are removed from the mold to complete the structure shown in Fig. 2b. In addition, the sealed product is cut through a single step (Singu 1 ati 〇n), and the carrier board 100 is cut into a plurality of single structures by means of stamping (PU nch) or cutting, so as to obtain the second C The chip package structure shown in the figure. As shown in Figures 2A to 2C, it is worth noting that, during the sealing step, the conventional sealing portion of the sealing mold 10 is pressed against the adjacent two substrates.

10036twf1.ptc 第9頁 59172610036twf1.ptc Page 9 591726

102之側邊102a的邊緣上，並分隔相鄰二模穴12，而熔融 之封襄材料1 2 0經由膠道而充填於模穴丨2中，且封裝材料 2 〇冷卻硬化之後會在基板1 〇 2上形成一封膠區域c (Mo 1 d ^ 。此外，由於壓合部14壓在基板1〇2的邊緣，會在封 人料1 2 〇之側邊1 2 0 a與基板1 0 2之側邊1 〇 2 a之間形成寬度 e模區域（Mold Clamp)。由此可知，習知的晶片封裝 肉ί縮小基板102的可利用面積，且侷限了基板1〇2 衣面及内部的佈線空間。 ϋ Ail外，若是為提高封裝材料120表面的平整度而楛* 模穴12内的注模壓力時m十登巧而“ 再者，】i:二if的現象’但卻會損傷基板m。 模組1〇壓在基板102上的面積，合=藉=減封裂 溢膠的情形，且溢膠（未緣 a 〇i面積不足，而有 103中，導致已封膠的成品在>進^切曰粟一/牛塊^殘留在槽孔 大的衝壓才能衝斷。此時若是η、'的步驟時，需要更 反而會損害基板1〇2。 θ 0堊在基板102的力量， 發明内容 因此，本發明的目的就杲 其中封膠模具之壓合部係壓^ ^ f出一種晶片封裝製程， 合部靠近模穴之開口處=構件i，以使壓 本發明的另一目的在提齊基板之側邊。 件接合於相鄰二基板的側邊 ：J J描其中多個支撐構 J便封膠模具之壓合部壓在On the edge of the side 102a of 102, the adjacent two mold cavities 12 are separated, and the molten sealing material 1 2 0 is filled in the mold cavities 2 through the glue channel, and the packaging material 2 is cooled and hardened on the substrate. A glue region c (Mo 1 d ^) is formed on 1 0 2. In addition, since the pressing portion 14 is pressed against the edge of the substrate 10 2, it will be on the side 1 2 0 a of the sealing material 1 2 0 and the substrate 1 A width e-mold region (Mold Clamp) is formed between the sides of 0 2 and 0 2 a. From this, it is known that the conventional chip package meat reduces the available area of the substrate 102 and limits the surface of the substrate 102 and the surface Internal wiring space. 外 Outside Ail, if it is to improve the flatness of the surface of the encapsulation material 120, the injection pressure in the cavity 12 is m, and "moreover," i: the phenomenon of two if ', but Will damage the substrate m. The area where the module 10 is pressed on the substrate 102, the total = borrowing = reduced sealing and overflow of glue, and the overflow of glue (the area of the edge a 0i is insufficient, and there are 103, resulting in sealed glue The finished product can be punched out after being punched in the > cutting millet / nuggets ^ remaining in the slot with a large punch. At this time, if the steps of η and 'are needed, the substrate will be damaged instead. 〇2. The power of θ0 chalk on the substrate 102. SUMMARY OF THE INVENTION Therefore, the purpose of the present invention is to compress the bonding part of the sealing mold ^ ^ f to produce a chip packaging process, and the bonding part is near the opening of the cavity. = Component i, so that another object of the present invention is to align the sides of the substrate. The components are joined to the sides of two adjacent substrates: JJ depicts a plurality of supporting structures J, and the pressing portion of the sealing mold is pressed on

591726 案號 91134718 、發明說明（4) 支撐構件上，以使壓合部 齊基板之側邊，進而增加 為達本發明之上述目 提供一載板，載板具有_ 支撐構件，而第一基板具 有至少一第二側邊，而支 邊 五591726 Case No. 91134718, description of the invention (4) The support member is provided so that the pressing portion is aligned with the side of the substrate, and then a carrier board is provided to achieve the above purpose of the present invention. The carrier board has a support member, and the first substrate Has at least one second side edge and five side edges

修正 之開 利用 靠近模穴 基板之可 的，提出 第一基板 有至少一 撐構件接 將一第一晶片及一第二晶片分 第二基板上；接著將一封 ^模具之壓合部大致上切 模具之壓合部大致上切齊 一封裝材料到封膠模具之 開載板，使得封裝材料暴 使第一基板與第二基板分 ^本發明之上述目的，提出 ，第一基板、多個第二基板以及多 ，第一基板具有_第一側邊， ，二且該第二側邊係相鄰於ί 一側 膠模具壓 齊第一基 第二基板 模穴中； 露於外； 離 一種 、一《. 第一 合於 別配 在支 板之 之第 接著 最後 口處的區域係可切 面積。 晶片 第二 側邊 第一 置到 撐構 二側 移動 去除 封裝 基板 ，第 側邊 第一 件上 側邊 邊； 封膠 支撐 製程 及至 二基 及第 基板 ，其 ，且 接著 模具 構件 先 少一 板具 二側 上及 中封 封膠 灌入 以離 ， 以 種載板，主要係由多 撐構件所構成。其 基板具有一第二側 於第一側邊以及第二側邊之間 個支 第二 邊，而支撐構件係接合 為讓本發明之上述目的 懂，下文特舉一較佳實施例 明如下： 實施方式 請參照第3圖至第6圖 特徵、和優點能更明顯易 並配合所附圖式，作詳細說 的 種晶片封裝結構的製程剖面圖 其繪示依照本發明較佳實施例The opening of the correction can be used near the cavity substrate, and it is proposed that the first substrate has at least one supporting member connected to a first wafer and a second wafer on the second substrate; then the pressing part of a mold is roughly The pressing portion of the cutting mold roughly cuts a packaging material to the opening plate of the sealing mold, so that the packaging material causes the first substrate to be separated from the second substrate. A second substrate and a plurality of, the first substrate has a first side edge, and the second side edge is adjacent to the one side rubber mold to align the first base and the second substrate mold cavity; exposed to the outside; One type, one ". The first area is the cuttable area that is allocated to the second and last mouth of the support plate. The second side of the wafer is first moved to the two sides of the supporting structure to remove the package substrate, and the first side is the upper side of the first piece; the sealing support process and the second base and the second substrate are removed, and then the mold member is removed by one plate. It has two upper and middle sealing sealants to inject and separate, and a kind of carrier board, which is mainly composed of multi-support members. The substrate has a second side with a second side between the first side and the second side, and the supporting member is joined to make the above object of the present invention understood. A preferred embodiment is described below as follows: For the implementation, please refer to FIGS. 3 to 6, and the features and advantages can be more obvious and easily combined with the drawings to make a detailed process cross-sectional view of a chip packaging structure, which illustrates a preferred embodiment according to the present invention.

10036twfl.ptc 第11頁 591726 _案號91134718_I 月日 條正 五、發明說明（5) 請先參照第3圖，並同時參照第3 A圖，其中第3 A圖繪 示對應於第3圖之載板的俯視圖。 如第3A圖所示，首先提供一載板2〇〇，而載板2〇〇具有 多個基板2 0 2、2 04以及多個支撐構件2 0 6，其中相鄰二基 板2 0 2、2 0 4之側邊2 0 2a、2 0 4a係藉由支撐構件2〇6連接。 另外’支撐構件2 0 6比如為條狀的樣式，其中支撑構件2 〇 β 之一端係接合於基板2 0 2之側邊2〇2a，而支撐構件2 0 6之另 一端係接合於基板204之侧邊204a。再者，基板2〇2、204 還具有多個接點203 ’排列於基板202、204之上表面208 上’作為連接晶片或外部電路之輸出入媒介。10036twfl.ptc Page 11 591726 _Case No. 91134718_I The fifth day of the month, the description of the invention (5) Please refer to Figure 3 first, and also to Figure 3 A, where Figure 3 A shows the one corresponding to Figure 3. Top view of the carrier board. As shown in FIG. 3A, a carrier board 200 is first provided, and the carrier board 2000 has a plurality of substrates 2 0 2, 2 04 and a plurality of supporting members 2 06, wherein two adjacent substrates 2 0 2 The sides 2 0 2a, 2 4a of 2 0 4 are connected by a supporting member 206. In addition, the 'support member 2 06' is, for example, a strip-shaped pattern, in which one end of the support member 2 0β is bonded to the side 202a of the substrate 202, and the other end of the support member 2 06 is bonded to the substrate 204.的 边边 204a。 The side 204a. In addition, the substrates 202 and 204 also have a plurality of contacts 203 'arranged on the upper surface 208 of the substrates 202 and 204 as an input / output medium for connecting a chip or an external circuit.

如第3圖所示，還要提供一晶片2丨〇，配置於基板2 〇 2 之上表面208。晶片210具有一主動表面212及對應之一背 面214 ’其中在晶片21〇之主動表面212具有多個焊墊216。 晶片210之背面214可貼附於基板2 〇2之上表面2 〇8上，之後 進行打線之製程，打上導線218，透過導線218使焊墊216 與基板2 0 2之接點2 〇 3電性連接。 a如第4圖所示，接下來進行封膠的步驟，首先提供一 =膠模具20，而封膠模具2〇具有多個模穴22，而相鄰二模 m具有一壓合部24，接下來將欲封膠之晶片21〇以、 及載板2 0 0的成品放置於封膠模具2〇中，而模穴“ 晶片210、導線218以及基板2〇2之接點2〇3，並且壓合部24As shown in FIG. 3, a wafer 210 is also provided, which is arranged on the upper surface 208 of the substrate 200. The wafer 210 has an active surface 212 and a corresponding one of the back surfaces 214 ', wherein the active surface 212 of the wafer 210 has a plurality of pads 216. The back surface 214 of the chip 210 can be attached to the upper surface 2 08 of the substrate 2 0, and then a wire bonding process is performed, and a wire 218 is applied, and the bonding pad 216 and the contact 2 2 of the substrate 2 0 3 are electrically connected through the wire 218. Sexual connection. a As shown in FIG. 4, the sealing step is performed next. First, a sealing mold 20 is provided, and the sealing mold 20 has a plurality of cavities 22, and the adjacent two molds m have a pressing portion 24. Next, the wafer 21 to be sealed, and the finished product of the carrier board 2000 are placed in the sealing mold 20, and the cavity "wafer 210, the wire 218, and the contact point 203 of the substrate 200 are Also the crimping section 24

可壓在相=二基板2〇2、2〇4之間的支撐構件2〇6上，其中 H部24 ϊ ί模穴22之開口處人的區域可切齊基板2 0 2’之側 a 聖合部24靠近模穴22之開口處β的區域可切齊It can be pressed on the supporting member 20 between the two substrates 202 and 204, and the area of the person at the opening of the H part 24 ϊ mold cavity 22 can be cut to the side of the substrate 2 0 2 ' The area β of the holy joint 24 near the opening of the mold cavity 22 can be aligned

591726 年 Μ 曰 修正 案號 91134718 五、發明說明（6) 基板204之側邊2 04a。由第3Α圖可知，由於支撐構件2〇6可 等分地配置在基板2 0 2、2 04的側邊2〇2a、2〇“之間，以 高載板2 0 0之耐壓性，因此在較高之注模壓力情形下， 板2 0 0可承受封膠模具2〇較大的注模壓力。 2。4二樣//Λ第：圖’在較佳的情況下，整個基板2 0 2、 上的空，並且藉由支撐構件2 0 6以支撐 21另夕二/、九2〇〇上的力量’故不會損傷基板2 0 2、 Ρ使/Jd出的封裝材料2 2 0會流入到支撐構件 m合但由於支揮構件2〇4會將溢出的封裝材 a大，壓即可衝斷支樓構件m。 0 ^ ^ ^ 9 9 nr接^進行填膠的動作，將熔融的封裝材料 S K卻1ϊ化comprnd)充填於模穴22之中，等到封裝材 Π W封裝，再進行脫模’而得到如第5圖之已封 支撑^二2^?6仃#切單的步驟，將接合相鄰二基板2 0 2、2〇4的 基板2 0 2之側H衝壓或切割的方式，使得切構件2〇6與 構。 〇2a $離，而得到如第6圖之晶片封裝結 將晶片與基ί ::::曰片：:#限定以打線的方式 及切單的步’接著再進行上述之封裝步驟以 W元成晶片封裝之製程。591726 M said amendment number 91134718 V. Description of invention (6) Side 204a of base plate 204. As can be seen from FIG. 3A, since the support member 206 can be equally divided between the sides 202a, 20 "of the substrates 20, 2, 04, and the high pressure resistance of the carrier plate 200, Therefore, in the case of a higher injection molding pressure, the plate 2000 can withstand the larger injection molding pressure of the sealing mold 20. 2.4 Second sample /// Λ 第: In the best case, the entire substrate 2 0 2, the space above, and the support member 2 0 6 to support the force of 21, 2, 9, 200, 'so it will not damage the substrate 2 0, 普 使 / Jd 出 的 包装 材料 2 2 0 will flow into the supporting member m but the supporting package member 204 will make the overflowing packaging material a larger, and the supporting member m can be broken by pressing. 0 ^ ^ ^ 9 9 nr Fill the molten packaging material SK1 (comprnd) into the mold cavity 22, wait until the packaging material ΠW is packaged, and then demold 'to get the sealed support as shown in Figure 5 ^ 二 2 ^? 6 仃 # The step of singulating will be to punch or cut the side H of the substrate 202 which is adjacent to the two substrates 20, 2 and 20, so that the member 20 and the structure are cut. 〇2a $ 离, and get as Figure 6 shows the chip package structure. Basic: :::: 片 :: # Limit the wire bonding method and the step of singulation 'followed by the above-mentioned packaging steps to form a wafer packaging process.

591726 案號 91134718 曰 修正 封裝製程， 鄰二基板之 高，如此基 的利用。 封裝製程， 板之側邊， 封膠模具之 ，並且可提 一較佳實施 熟習此技藝 各種之更動 請專利範圍 明之晶片封裝製程至少具有下列優 五、發明說明（7) 綜上所述，本發 點： 1. 本發明之晶片 具之壓合部可壓在相 板之可利用面積可提 空間，可以作更有效 2. 本發明之晶片 構件接合於相鄰二基 得在封膠的步驟中， 上，故不會損傷基板 雖然本發明已以 以限定本發明，任何 神和範圍内，當可作 護範圍當視後附之申 在封膠的步驟中，封膠模 間的支撐構件上，因此基 板之表面以及内部的佈線 提供一載板，其藉由支撐 以提高載板之耐壓性，使 壓合部可壓在支撐構件 高基板之可利用面積。 例揭露如上，然其並非用 者，在不脫離本發明之精 與潤飾，因此本發明之保 所界定者為準。591726 Case No. 91134718 said to modify the packaging process, the height of the next two substrates, such a use. The packaging process, the side of the board, the sealing mold, and can be implemented better. Familiar with this technology and various changes. The patented package packaging process has at least the following advantages. 5. Description of the invention (7) In summary, this Starting point: 1. The pressing part of the wafer of the present invention can be pressed against the available area and space of the phase plate, which can be made more effective. 2. The wafer component of the present invention is bonded to the adjacent two bases in the step of sealing. Medium, upper, so it will not damage the substrate. Although the present invention has been defined to limit the present invention, within any scope and scope, when it can be used as a protective range, it is attached to the sealing step in the sealing step. Therefore, the surface of the substrate and the internal wiring provide a carrier board, which is supported to improve the pressure resistance of the carrier board, so that the crimping portion can be pressed against the available area of the high substrate of the supporting member. The example is disclosed as above, but it is not the user, and it does not depart from the essence and retouching of the present invention, so what is guaranteed by the present invention shall prevail.

Μ 10036twf1.ptc 第14頁 591726 案號 91134718 Λ_ 曰 修正 圖式簡單說明 第1圖繪示習知的基板型承載器之示意圖； 第2 A〜2 B圖繪示第1圖之載板應用於一晶片封裝結構的 剖面示意圖； 第2 C圖繪示晶片封裝結構的俯視圖； 第3、4、5及6圖繪示本發明一較佳實施例之一種晶片 封裝結構的製程剖面圖；以及 第3 A圖繪示對應於第3圖之載板的俯視圖。 圖式之標示說明：Μ 10036twf1.ptc Page 14 591726 Case No. 91134718 Λ_ Brief description of the correction diagram Figure 1 shows a schematic diagram of a conventional substrate-type carrier; Figures 2 A to 2 B show the carrier plate of Figure 1 applied to A schematic cross-sectional view of a chip packaging structure; FIG. 2C is a top view of the chip packaging structure; FIGS. 3, 4, 5, and 6 are cross-sectional views illustrating a manufacturing process of a chip packaging structure according to a preferred embodiment of the present invention; Figure 3A shows a top view of the carrier board corresponding to Figure 3. Graphical labeling instructions:

10 12 14 100、 102 、 102a 103 ： 106， 110, 112、 114, 120， 2 0 6 ： 2 0 8， 214 ： A 、B 20 22 24 、200 封膠模具 模穴 壓合部 :載板 2 0 2、2 0 4 :基板 、120a 、202a > 204a 槽孔 2 0 3 :接點 2 1 0 :晶片 216 :焊墊 2 1 8 :導線 2 2 0 :封裝材料 支撐構件 2 1 2 :表面 背面 :開口處 2 2 0 a :側邊10 12 14 100, 102, 102a 103: 106, 110, 112, 114, 120, 2 0 6: 2 0 8, 214: A, B 20 22 24, 200 Sealing mold cavity pressing part: carrier plate 2 0 2, 2 0 4: substrate, 120a, 202a & 204a slot 2 0 3: contact 2 1 0: wafer 216: pad 2 1 8: lead 2 2 0: packaging material support member 2 1 2: surface Back: Opening 2 2 0 a: Side

10036twf1.ptc 第15頁 591726 案號 91134718 年月日 修正10036twf1.ptc Page 15 591726 Case No. 91134718 Revised

10036twf1.ptc 第16頁10036twf1.ptc Page 16

Claims (1)

591726 千 案號 91134718 一^正 \、申請專利範圍 在該第一側邊與該第二側邊之間。 3.如申請專利範圍第丨項所述之晶片封 該支撐構件係為桿狀的樣式，該支撐構件的$二二乂 合於該第一側邊及該第二側邊。 兩碥係刀別接 4·如申請專利範圍第丨項所述之晶片封 該第一基板具有一第一表面，該第一晶片係配亥第、! 基板之该第一表面上，該第二基板具有一第二 / 二晶片係配置在該第二基板之該第二表面 ^ 口乂 參 件具有：表面，而該封膠模具係壓在該支樓構= 上，該第-基板之該第一表面、該第二基板2 與該支撐構件之該表面係為共平面地配置。β 5 · —種晶片封裝製程，至少包括： 提仏載板，具有一基板以及至少一構件，該美柄 具有:f 一側邊，該構件與該基板之該側邊接合，°並、出 於該基板之該側邊； 工大出 將一晶片配置到該基板上； 人# θ將一膠模具壓在該構件上，該封膠模具具有一壓 丄該壓合部係位在該模穴的周圍，該封膠模 = = 壓在該構件上，並且該壓合部靠近該ί 穴容納該晶片； 大致上切齊該基板之該侧4，而該模 灌入一封裝材料到該模穴中，以包覆該晶片及該基 板， 移動邊封膠模具以離開該載板，使得該封裝材料暴591726 Thousand case number 91134718 A positive application, the scope of patent application is between the first side and the second side. 3. The wafer encapsulation according to item 丨 of the scope of the patent application. The support member is a rod-shaped pattern, and $ 22 of the support member is combined with the first side and the second side. The two wafers are connected together. The first substrate has a first surface as described in the wafer seal described in item 丨 of the patent application scope. The first wafer is configured on the first surface of the substrate. The two substrates have a second / second wafer disposed on the second surface of the second substrate. The mouthpiece has: a surface, and the sealing mold is pressed on the supporting structure =, the first substrate The first surface, the second substrate 2 and the surface of the support member are arranged in a coplanar manner. β 5 · A chip packaging process, including at least: a carrier board having a substrate and at least one member, the handle has: f one side, the member is joined to the side of the substrate, and On the side of the substrate; the University of Technology places a wafer on the substrate; the person # θ presses a plastic mold on the component, and the plastic sealing mold has a pressure that the crimping part is located in the cavity Around, the sealing mold is pressed on the component, and the pressing portion is close to the hole to accommodate the wafer; the side 4 of the substrate is roughly cut, and the mold is filled with a packaging material into the mold. In the cavity, the wafer and the substrate are covered, and an edge-sealing mold is moved to leave the carrier board, so that the packaging material is exposed. 第18頁 591726Page 591 726 今載板6且如/Λ專利範圍第5項所述之晶片封裝製程，其中 邊：個構件，該些構件係等分地配置在該基板 之該側邊。 式而该構件的一端係接合於該基板 „ ^ M K t „ t 而該構件具有一表㊉，：，射！在该基板之5亥表面上’ 面上，該基板之該表面“ 之該表 置。 彳再1干之5亥表面係為共平面地配 9 ·如申睛專利筋图楚 該載板具有複數個構件，、’L之晶片封裝製程，其中 件分別與該基板之該4b j 5，具有四個側邊，該些構 該些四個侧邊，當該 ^ 、接，並突出於該基板之 時，該壓合部靠近:具之該壓合部壓在該些構件上 齊該基板之該些四^ ^ ^模穴之開口處的區域係大致上切 1 0.如申請專刹# m » 中該些構件係等*地配 1項所述之晶片封裝製程，其 η· -種晶片該基板之該些四個側邊上。 -第-基板封/有載V至丄包括： -第二基板，具:. 一有第一側邊，且该第二側邊與該The carrier board 6 and the wafer packaging process as described in item 5 of the / Λ patent range, wherein the edge is a component, and the components are equally arranged on the side of the substrate. And one end of the component is connected to the substrate „^ M K t„ t and the component has a surface ㊉ :, shoot! On the surface of the substrate, the surface is placed on the surface of the substrate. The surface of the substrate is co-planar with the surface of the substrate. A plurality of components, a wafer packaging process of 'L, wherein each of the components and the 4b j 5 of the substrate have four sides, the structures constitute the four sides, and when the ^, are connected, and protrude from the At the time of the substrate, the pressing portion is close to: the area where the pressing portion is pressed on the components to align the openings of the four ^ ^ mold cavities of the substrate is roughly cut 10. If applying for special brakes # m »These components are equipped with the wafer packaging process described in item 1, and η ·-the wafer is on the four sides of the substrate.-Substrate sealing / on-load V to 丄 include :-A second substrate, with:-a first side, and the second side and the 591726 1號 9113471只 六、申請專利範圍 曰 修正 第一側邊相鄰；以及 至少一支撐構件，該支 該第二側邊，以使-封膠模具m接合於該第-側邊及 上。 Μ σ σ卩壓在該支撐構件 1 2 ·如申請專利範圍第1 1項所述之曰Η 中該載板具有複數個支撐構件，、，曰曰片封裝載板，其 置在該第一側邊與該第二側邊之^ 了支撐構件係等分地配、 1 3·如申請專利範圍第1 i a °、 中該支樓構件係為桿狀的樣式，、5 曰片封裝載板，其 接合於該第一側邊及該第二側邊了 牙構件的兩端係分別 1 4 ·如申請專利範圍第i i 中該第一基板之一表面、該第二美a之晶片封裝載板，其 件之一表面係為共平面地^置了土反之―表面與該支撐構 15某：種晶Λ封裝載板，至少包括： 一基板，具有一側邊；以及 至 >、構件，與該基板之該側邊接人 ^ 基板=使—封膠模具之-。，、二出於該 1 6.如申请專利範圍第! 5項所述之 t 2 :上。 中該載板具有複數個構件，該些構 ^ /裝載板，其 板之該側邊上。 係孝刀地配置在該基 1 7.如申請專利範圍第丨5項所 中該構件係為桿狀的樣式，而該構的二J 板，其 板之該側邊。 旧知係接合於該基 1 8 ·如申請專利範圍第丨5項所 〜〜曰曰片封裝載板，其 10036twfl-l.ptc 第20頁 591726 _案號 91134718_年月日__ 六、申請專利範圍 中該基板 之一表面與該構件之一表面係為共平面地配置。 1 9 .如申請專利範圍第1 5項所述之晶片封裝載板，其 中該載板具有複數個構件，而該基板具有四個側邊，該些 構件分別與該基板之該些四個側邊連接，並突出於該基板 之該些四個側邊。 2 0 .如申請專利範圍第1 9項所述之晶片封裝載板，其 中該些構件係等分地配置在該基板之該些四個側邊上。591726 No. 1 9113471 only 6. Scope of patent application: Amendment The first side is adjacent; and at least one supporting member supporting the second side so that the -sealing mold m is joined to the first side and above. Μ σ σ 卩 is pressed on the supporting member 1 2 · As described in Item 11 of the scope of the patent application, the carrier board has a plurality of supporting members, ie, a chip package carrier board, which is placed on the first The side and the second side are divided equally between the supporting member system, 1 3 · If the scope of the patent application is 1 ia °, the component of the branch building is a rod-shaped style, and the 5 package carrier board The two ends bonded to the first side and the second side of the dental member are respectively 1 4 · As a surface of the first substrate in the patent application scope ii, the chip package of the second beauty a Board, one of its surfaces is coplanar and the soil is reversed-the surface and the support structure 15: seed crystal Λ package carrier board, at least including: a base plate with one side; and > , And the side of the substrate is connected ^ substrate = make-of the sealing mold. The second and the second out of this 16. As described in the scope of application for patent! Item t 2: on. The carrier board has a plurality of components, and the structures are loaded on the side of the board. The structure is arranged on the base 1 7. As described in Item 5 of the scope of the patent application, the component is a rod-shaped style, and the two J-plates of the structure are on the side of the plate. The old knowledge is connected to the base 1 8 · As described in the scope of the application for patent No. 丨 5 ~ ~ chip package carrier board, its 10036twfl-l.ptc page 20591726 _ case number 91134718 _ month month day __ VI In the scope of the patent, one surface of the substrate and one surface of the component are arranged in a coplanar manner. 19. The chip package carrier board according to item 15 of the scope of patent application, wherein the carrier board has a plurality of members, and the substrate has four sides, and the members are respectively connected to the four sides of the substrate. The edges are connected and protrude from the four sides of the substrate. 20. The chip package carrier according to item 19 of the scope of patent application, wherein the components are equally arranged on the four sides of the substrate. 10036twf1 -1.ptc 第21頁10036twf1 -1.ptc Page 21
TW091134718A 2002-11-29 2002-11-29 A method for manufacturing a chip package TW591726B (en)

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