TW589727B - Bumping structure and fabrication process thereof - Google Patents

Bumping structure and fabrication process thereof Download PDF

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Publication number
TW589727B
TW589727B TW092117874A TW92117874A TW589727B TW 589727 B TW589727 B TW 589727B TW 092117874 A TW092117874 A TW 092117874A TW 92117874 A TW92117874 A TW 92117874A TW 589727 B TW589727 B TW 589727B
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Taiwan
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bump
patent application
scope
item
layer
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TW092117874A
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English (en)
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Tong Hong Wang
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Advanced Semiconductor Eng
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Priority to TW092117874A priority Critical patent/TW589727B/zh
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Publication of TW589727B publication Critical patent/TW589727B/zh
Priority to US10/874,239 priority patent/US20040266066A1/en

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Description

589727
、一）、【發明所屬之技術領域】 增加 之凸 =明係關於一種凸塊結構，且特別是有關於能 〇塊问度且防止凸塊迴銲與基板接合時產 塊結構及其製程。 王嚴重朋知 (二）、【先前技術】 =高度資訊化社會的今日，多媒體應用市場不斷地各 積體電路封裝技術也隨之朝電子裝置的數位化: 、，同路化、區域連接化以及使用人性化的趨勢 上述的要求，電子元件必須配合高速處理& 成 ^集化、小型輕量化及低價化等多方面之要求，也因b籍 體電路封裝技術也跟著朝向微型化、高密度'
Ban 〇ridArray，Β0Λ^：；：4； 衣（Chip-Scale Package, CSP )，覆晶構裝（FHp fh^p， F/C )，多晶片模組（Multi-Chip Module， MCM ) 等高密度積體電路封裝技術也因應而生。 其中覆晶構裝技術（F 1 i p C h i p P a c k a g i n g Techno logy)主要是利用面陣列（area array)的排列方 式，將多個晶片銲墊（bond i ng pad )配置於晶片（d i e )之主 動表面（act ive surf ace)，並在各個晶片銲墊上形成凸塊 (b u m p) ’接著再將晶片翻面（f η p )之後，利用晶片銲墊上^ 的凸塊分別電性（electrical ly)及機械（mechanical ly)連 接至基板（substrate)或印刷電路板（pCB)之表面所對應的 接合墊（mount ing pad)。再者，由於覆晶接合技術係可應
589727 — ___案號 92117874___年 月_g_修正____ 五、發明說明（2) 用於高接腳數（High Pin Count)之晶片封裝結構，並同時 具有縮小封裝面積及縮短訊號傳輸路徑等多項優點，所以 覆晶接合技術目前已經廣泛地應用在晶片封裝領域。 而所謂的晶圓凸塊製程，則常見於覆晶技術（f丨i p ch i p )中’主要係在形成有多個晶片的晶圓上對外的接點 (通常是金屬銲墊）上形成球底金屬層（UBM， Under Bump Metallurgy)，接著於球底金屬層之上形成凸塊或植入銲 球以作為後續晶片與基板（s u b s t r a t e )電性導通之連接介 面。 請參照圖1，係為習知之晶圓凸塊結構。晶圓1 〇 〇係具 有保護層1 0 2及複數個晶圓銲墊i 〇 4暴露出保護層1 〇 2，另 外於晶圓銲墊1 0 4上形成一球底金屬層1 〇 6，且球底金屬層 1 0 6上形成有一由銲料凸塊經迴銲後而形成之銲球結構 1 0 8。之後，再分割具有凸塊之晶圓以形成具有凸塊之晶 片結構（未標示於圖中）。一般而言，球底金屬層可為鈦/ 鎳-釩合金/銅三層金屬結構（適用於晶圓之銅製程）或為 鋁/鎳-釩合金/銅三層金屬結構（適用於晶圓之鋁製程）， 其係利用電鍍或錢鑛等方式形成於晶圓表面’再接續利用 光阻覆蓋於球底金屬層上並利用顯影及餘刻等方式圖案化 光阻層及球底金屬層以疋義出所需之球底金屬層結構。另 外，銲料凸塊係由電鐘之方法或網版印刷之方式將銲料填 入由光阻層所定義之對應晶圓輝塾及圖案化後之球底金屬 層結構之開口中而形成之。 承上所述，將具有凸塊之晶片翻覆對準基板之接墊與
第7頁 589727 _案號92117874_年月日 修正_ 五、發明說明（3) 基板接合時，當進行迴銲過程時，該凸塊之高度會因晶片 本身之重量，而由原高度Η減少到高度h ( h / Η之比值通常係 介於0 · 7至0. 7 5之間）。再者，由於（矽）晶片與基板的熱 膨脹係數不同，故接點數目增加時，該半導體元件之金屬 凸塊之節距W ( p i t ch)係會越小且金屬凸塊之球徑係會愈 小，如此將會使得凸塊所承受的剪應力增加，而降低凸塊 之機械可靠度。 故針對上述問題點，需設法形成較高的凸塊，以增大 基板與晶片之間隙。藉此，能防止凸塊迴銲後之崩塌現 象，以進一步改善其機械可靠度。因此，提供解決上述習 知凸塊結構之缺點及其相關製程之方法，實為本發明之重 要課題。
589727 _案號92117874_年月日__ 五、發明說明（4) 合時之迴銲溫度亦低於高熔點凸塊之融熔溫度。 再者，本發明另提出一種形成上述凸塊結構之凸塊製 程，其係包含下列步驟。提供一晶圓，該晶圓上具有一保 護層及暴露出保護層之複數個晶圓銲墊，且晶圓銲墊上形 成有球底金屬層。接著，先於晶圓銲墊上方之球底金屬層 上形成高熔點凸塊，再接續形成低熔點凸塊以包覆高熔點 凸塊。最後，進行一低熔點凸塊迴銲步驟以使低熔點凸塊 球化。 综前所述，由於凸塊結構迴銲或晶片與基板覆晶接合 時之迴銲溫度係低於高熔點凸塊之融熔溫度，且高於低熔 點凸塊之融熔溫度，故當凸塊結構迴銲時或晶片與基板覆 晶接合時，高熔點凸塊可保持原有之形狀及高度，所以能 防止凸塊結構迴銲後之崩塌現象，維持基板與晶片之原設 計間隙以避免基板與晶片間之空隙變小，而影響其機械可 靠度。此外，一般而言，高熔點凸塊與低熔點凸塊主要皆 由錫錯所組成，其熱膨脹係數相當接近，故可防止其加熱 迴銲時，因溫度之變化而影響凸塊間之接合強度。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之凸 塊結構及其製程。 請參考圖2，其顯示根據本發明之較佳實施例之凸塊 結構的剖面示意圖。 請參考圖2，係表示晶圓2 0 0之部分結構示意圖。晶圓
589727 案號 92117874 年月曰 五、發明說明（5) 2 0 0係具有保護層2 0 2及至少一暴露出保護層2 〇 2之晶圓銲 墊2 0 4。晶圓銲塾2 0 4上係形成有球底金屬層2 〇 6，且球底 金屬層2 0 6上形成有一凸塊結構2 0 8。其中，保護層2 〇 2係 配置於晶圓表面上，用以保護晶圓2 0 0表面並暴露出晶圓 鮮塾2 0 4 ’而凸塊結構2 0 8係由第一銲·料凸塊2 〇 8 a及第二鲜 料凸塊2 0 8 b所組成’且弟 >一鮮料凸塊2 0 8 b係包覆第一銲料 凸塊2 0 8 a。另外，第一鍀料凸塊2 0 8 a之、熔點係大於第二銲 料凸塊2 0 8 b之熔點及凸塊結構2 0 8迴銲時之溫度，且第二 銲料凸塊2 0 8 b之熔點係小於凸塊結構2 〇 8迴銲時之溫度， 故凸塊結構2 0 8迴銲·時’弟一鮮料凸塊2 〇 8 a可保持原有之 形狀及咼度’而第二銲料凸塊2 0 8 b則因溶化及銲料溶融後 之内聚力作用而球化。 承上所述’一般而言，咼錯銲料（如錫與錯之重量比 為5 : 95)具有較高之熔點（high melting p〇int)，約為攝 氏3 2 0度，故第一銲料凸塊2 0 8a可為高鉛銲料凸塊。再 者，由於一般之錫錯銲料（錫與錯重量比為6 3 : 3 7)具有較 低之熔點（1 〇 w m e 11 i n g ρ 〇 i n t)，約為攝氏1 8 5度，故第二 銲料凸塊2 0 8 b可為較低溶點之一般錫錯銲料凸塊。 潤濕層，以作為凸 layer)，如為鈦金 選自於鈦、鈦鎢合金、& 金、銅及鎳鈦合金等材質 護層2 0 2上延伸以作為線'路
…訊合金/銅金屬三層結構，或為 ，、鋁、鉻、鎳、鎳釩合金、鉻銅合 等材質。再者’當球底金屬層2 〇 6於保 為線路重分佈層2 1 0而提供另一線路重 另外，球底金屬層2 0 6—般可分為黏著層、阻障層及 潤濕層，以作為凸 589727 ---案號 92117874_一年 月 a 你 $_ 五、發明說明（6) 为佈#干墊2 1 0 a於保護層2 0 2上時，上述由第一銲料凸塊 2 1 2 a及第二銲料凸塊2 1 2 b組成之凸塊結構2 1 2亦可設置於 線路重分佈銲墊2 1 0 a上（如圖3所示）。此外，另有一介電 層（介電保護層）2 1 4覆蓋線路重分佈層2 1 〇而暴露出線路重 分佈銲墊2 1 0 a及凸塊結構2 1 2。其中，介電保護層 (dielectric layer)可由聚亞醯胺（p〇iyimide)或由苯併 環丁稀（Benzocyclobutene，BCB)等高分子聚合物所組成， 用以防止線路重分佈層2 1 0之表面氧化及提供一應力緩衝 之介面。 接著，請參考圖4至圖7，其顯示根據本發明之較佳實 施例之凸塊製程的剖面示意圖。 首先’請參照圖4，提供一晶圓3 0 0，晶圓3 〇 〇上形成 有一保護層3 0 2並配置有複數個晶圓銲墊3 〇 4。其中，保護 層3 0 2係配置於晶圓3 0 0表面上，用以保護晶圓3 〇 〇表面並 暴露出晶圓銲墊3 0 4。 接著’再請參照圖4，形成球底金屬層3 〇 6於該晶圓上 並覆蓋晶圓銲墊304。再者，形成第一光阻層3〇7於球底金 屬層3 0 6上，並形成複數個第一開口 3 〇 7 a以暴露出球底金 屬層3 0 6。其中，第一開口 3 〇 7 a係暴露出晶圓銲墊3 〇 4上方 之球底金屬層3 0 6。之後，填入第一銲料3 〇 8 a於第一開口 3 0 7a中，其可藉由電鍍之方式或網版印刷之方式形成之。 承上所述，請參照圖5，將第一光阻層3 〇 7去除，並接 著形成一第二光阻層3 0 9於球底金屬層3 0 6上並形成複數個 第二開口 309 a以暴露出銲墊30 4上方之球底金屬層30 6及第
第11頁 589727 遠號 92117874 干 五、發明說明（7) 一輝料凸塊。其中，該第二光阻層之厚度H2係大於第一光 阻層之厚度Η 1，且第二開口 D 2係大於第一開口 D卜 接著’請參照圖6，以電鍍方式或網版印刷之方式將 第二鲜料凸塊3 0 8b填入第二開口 3 0 9a中以包覆第一銲料凸 塊>3〇8a。之後，去除第二光阻層3 0 9，並以凸塊結構308 (第一桿料凸塊3 0 8a及第二銲料凸塊3 0 8b)為遮罩以圖案化 球底金屬層3〇6，而形成圖案化球底金屬層306,以完成凸 塊製程（如圖7所示）。 3 0 \請參照圖8 ’進行一迴鲜步驟’以使凸塊結構 /二輝料凸塊3 0 8b受熱球化而與球底金屬層3〇6及 弟一=枓凸塊3〇8a緊密接合。 延伸ϋ Ϊ Ϊ，如圖3所示，當球底金屬層於保護層202上 於保護ΠηίΛ佈層2、10而提供另一線路重分佈輝墊 一銲料凸塊2丨2時，上述之凸塊製程亦可應用於將第 形成於線路重I:!:銲料凸塊212b組成之凸塊結構212 材質覆蓋線路重分佈層該暴露出\路\1之方式將介電 及凸塊結構212’再經過烘烤使盆固化重：佈銲塾21〇a 層2:4。另外亦可將一介電保護膜（ ::-介電保護
Pr〇teCtlon fUm)直接貼附於晶 2 1 〇以作為一緩衝介面。 並覆盍線路重分佈層 在本實施例中，由於凸塊結 與基板覆晶接合時之迴銲C匕之溫度或晶片 溫度，且高於第二銲料凸塊4 ^於弟一銲料凸塊之融炼 塊之…度。故當凸塊結構迴
1^· 589727 _案號92117874_年月日__ 五、發明說明（8) 銲球化時或晶片與基板覆晶接合時，第一銲料凸塊可保持 原有之形狀及高度，所以能防止凸塊迴銲後之崩塌現象， 以增大基板與晶片之間隙，改善其機械可靠度。此外，一 般而言，第一銲料凸塊與第二銲料凸塊主要皆由錫鉛所組 成，其熱膨脹係數相當接近，故可防止第二銲料凸塊加熱 迴銲時，因溫度之變化而影響第一銲料凸塊與第二銲料凸 塊間之接合強度。
於本實施例之詳細說明中所提出之具體的實施例僅為 了易於說明本發明之技術内容，而並非將本發明狹義地限 制於該實施例，因此，在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。
第13頁 589727 _案號92117874_年月日__ 圖式簡單說明 (五）、【圖式之簡單說明】 圖1為一習知之凸塊結構剖面示意圖。 圖2為依照本發明較佳實施例之凸塊結構剖面示意 圖。 圖3為依照本發明另一較佳實施例之凸塊結構剖面示 意圖。 圖4至圖8為一凸塊製程的流程剖面示意圖，顯示為依 照本發明較佳實施例之凸塊製程。 元件符號說明： 100 晶圓 102 保護層 104 晶圓銲墊 106 球底金屬層 108 迴銲後之銲料凸塊 200 晶圓 202 保護層 204 晶圓鮮塾 206 球底金屬層 2 0 8, 、212、 308: 凸塊結構 2 0 8 a、2 1 2 a : 第一銲料凸塊 208b、 212b: 第二銲料凸塊 210 線路重分佈層 210a： 線路重分佈銲墊
第14頁 589727 案號 92117874 _η 曰 修正 圖式簡單說明 214 300 302 304 306 3 0 6? 3 0 7 ^ 3 0 7a 3 0 8 a 3 0 8b 3 0 8 c 3 0 9 ： 3 0 9 a· 介電保護層 晶圓 保護層 晶圓鮮塾 球底金屬層 圖案化球底金屬層 第一光阻層、第二光阻層 第一開口 、第二開口 第一銲料凸塊 第二銲料凸塊 迴銲後之第二銲料凸塊
第15頁

Claims (1)

  1. 589727 _案號 92117874_年月日__ 六、申請專利範圍 1 · 一種凸塊結構，適於配置在一晶圓上，該晶圓上具有一 保護層及暴露出複數個晶圓銲墊，且該晶圓銲墊上形成有 一球底金屬層，其中該凸塊結構係設置於該球底金屬層 上，其中該凸塊結構係包括： 一第一銲料凸塊，其係與該球底金屬層相連接；及 一第二銲料凸塊，其係包覆該第一銲料凸塊且與該球底金 屬層相連接。 2 .如申請專利範圍第1項所述之凸塊結構，其中該第一銲 料凸塊之熔點係高於第二銲料凸塊之熔點。 3 .如申請專利範圍第1項所述之凸塊結構，其中該第一銲 料凸塊係為一局錯鲜料凸塊。 4 .如申請專利範圍第3項所述之凸塊結構，其中該第一銲 料凸塊中錫與鉛之重量比為5 : 9 5。 5 .如申請專利範圍第1項所述之凸塊結構，其中該第二銲 料凸塊中錫與船之重量比為6 3 : 3 7。 6 .如申請專利範圍第1項所述之凸塊結構，其中該第一銲 料凸塊之熔點係高於凸塊結構之迴銲溫度。 7 .如申請專利範圍第1項所述之凸塊結構，其中該球底金
    589727 _案號92117874_年月曰 修正_ 六、申請專利範圍 屬層係包含黏著層、阻障層及潤濕層。 8 .如申請專利範圍第1項所述之凸塊結構，其中該球底金 屬層係為一線路重分佈層。 9 .如申請專利範圍第8項所述之凸塊結構，其中該線路重 分層上係設置有一介電保護層，並暴露出複數個開口且凸 塊結構係設置於該開口中。 1 0 .如申請專利範圍第1項所述之凸塊結構，其中該球底金 屬層係為鈦金屬/鎳-釩合金/銅金屬三層結構。 1 1.如申請專利範圍第1項所述之凸塊結構，其中該球底金 屬層之材質係選自於由鈦、鈦鎢合金、鋁、鉻、鎳、鎳釩 合金、鉻銅合金、銅及鎳鈦合金所組成之族群中的一種材 質。 1 2 . —種凸塊製程·，包含： 提供一晶圓，該晶圓上具有一保護層及複數個晶圓銲墊， 且該保護層係暴露出該等晶圓銲墊； 形成一球底金屬層於該等晶圓銲墊上； 形成一第一光阻層於該晶圓上，並形成複數個第一開口以 分別暴露出該球底金屬層； 填入一第一銲料於該等第一開口中以形成複數個第一銲料
    第17頁 589727 _案號 92117874_年月日__ 六、申請專利範圍 凸塊； 去除該第一光阻層； 形成一第二光阻層於該晶圓上，並形成複數個第二開口以 分別暴露出該球底金屬層及該等第一銲料凸塊； 填入一第二銲料於該等第二開口中以形成複數個第二銲料 凸塊，其中每一該等第二凸塊係分別包覆該第一銲料凸 塊；及 去除該第二光阻層。 1 3 .如申請專利範圍第1 2項所述之凸塊製程，更包含圖案 化該球底金屬層之步驟以分別於每一該等晶圓銲墊上形成 一圖案化球底金屬層。 1 4 .如申請專利範圍第1 3項所述之凸塊製程，其中係以該 等第一銲料凸塊及該等第二銲料凸塊為遮罩以圖案化該球 底金屬層。 1 5 .如申請專利範圍第1 2項所述之凸塊製程，其中該第一 開口係暴露出每一該等晶圓銲墊上方之該球底金屬層。 1 6 .如申請專利範圍第1 2項所述之凸塊製程，其中該第二 開口係暴露出每一該等銲墊上方之該球底金屬層。 1 7 .如申請專利範圍第1 2項所述之凸塊製程，其中該第二
    第18頁 589727 _案號92117874_年月曰 修正_ 六、申請專利範圍 開口係大於第一開口。 1 8 ·如申請專利範圍第1 2項所述之凸塊製程，其中該第一 銲料凸塊之熔點係高於第二銲料凸塊之熔點。 1 9 .如申請專利範圍第1 2項所述之凸塊製程，其中該第一 銲料凸塊係為一高鉛銲料凸塊。
    2 〇 .如申請專利範圍第1 9項所述之凸塊製程，其中該第一 銲料凸塊中之錫與錯重量比為5 : 9 5。 2 1 .如申請專利範圍第1 2項所述之凸塊製程，其中該第二 銲料凸塊中之錫與鉛重量比為6 3 : 3 7。 2 2 .如申請專利範圍第1 2項所述之凸塊製程，其中該第一 銲料凸塊之熔點係高於凸塊結構之迴銲溫度。 2 3 .如申請專利範圍第1 2項所述之凸塊製程，其中該球底 金屬層係包含黏著層、阻障層及潤濕層。
    2 4 .如申請專利範圍第1 2項所述之凸塊製程，更包含一迴 銲步驟。 2 5 .如申請專利範圍第1 2項所述之凸塊製程，其中該等第
    第19頁 589727 _案號 92117874 年_^_Θ_修正_ 六、申請專利範圍 一銲料凸塊係以網版印刷之方法形成。 2 6 ·如申請專利範圍第1 2項所述之凸塊製程，其中該等第 二銲料凸塊係以網版印刷之方法形成。 2 7 .如申請專利範圍第1 2項所述之凸塊製程，其中該等第 一銲料凸塊係以電鍍方式形成。 2 8 .如申請專利範圍第1 2項所述之凸塊製程，其中該等第 二銲料凸塊係以電鍍方式形成。 2 9 .如申請專利範圍第1 2項所述之凸塊製程，其中該圖案 化球底金屬層係為一線路重分佈層。 3 0 .如申請專利範圍第1 2項所述之凸塊製程，其中該第一 光阻層形成於晶圓上之前，更設置有一介電層於該線路重 分層上。 3 1.如申請專利範圍第3 0項所述之凸塊製程，其中該介電 層之材質係包含聚亞驢胺（ρ ο 1 y i m i d e，P I )。 3 2 .如申請專利範圍第3 0項所述之凸塊製程，其中該介電 保護層之材質係包含苯併環丁烯 (Benzocycl〇butene，BCB)。
    第20頁 589727 修正 _案號 92117874 六、申請專利範圍 3 3 ·如申請專利範圍第1 2項所述之凸塊製程，其中該球底 金屬層之材質係選自於由鈦、鈦鎢合金、鋁、鉻、鎳、鎳 釩合金、鉻銅合金、銅及鎳鈦合金所組成之族群中的一種 材質。
    第21頁
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US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
KR100871388B1 (ko) 2007-08-09 2008-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
US8759209B2 (en) * 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US9147661B1 (en) 2014-02-03 2015-09-29 Xilinx, Inc. Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same
DE102015100521B4 (de) * 2015-01-14 2020-10-08 Infineon Technologies Ag Halbleiterchip und Verfahren zum Bearbeiten eines Halbleiterchips
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
TWI636533B (zh) 2017-09-15 2018-09-21 Industrial Technology Research Institute 半導體封裝結構

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JPH10125685A (ja) * 1996-10-16 1998-05-15 Casio Comput Co Ltd 突起電極およびその形成方法
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Publication number Priority date Publication date Assignee Title
US7586187B2 (en) 2006-03-31 2009-09-08 Industrial Technology Research Institute Interconnect structure with stress buffering ability and the manufacturing method thereof
US8123965B2 (en) 2006-03-31 2012-02-28 Industrial Technology Research Institute Interconnect structure with stress buffering ability and the manufacturing method thereof

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