TW587315B - Multi-chip module - Google Patents

Abstract

A multi-chip module is provided. The multi-chip module at least includes: a first chip, a substrate, a second chip, pluralities of wires, and a package material. The first chip has an active surface, pluralities of bonding pads, and the bonding pads are disposed on the active surface. The substrate has a top surface, a bottom surface, and at least a slot, wherein the first chip is disposed on the bottom surface of the substrate by the active surface, and the bonding pads are exposed in the slot. The wires are connected to the bonding pads and the top surface of the substrate electrically. The second chip is disposed on the top surface of the substrate, and the second chip is connected to the top surface of the substrate electrically. And the first chip, second chip, the wires, the top surface and the bottom surface are covered by package material.

Description

587315 V. Description of the invention (l) The technical leadership of Dengming The present invention relates to a multi-chip package module, and more particularly to a method capable of reducing substrate warpage, preventing wafer cracking, and reducing Multi-chip package modules with signal transmission loss. The production of integrated circuits (ICs) in the semiconductor industry in the previous technology is mainly divided into three stages: wafer (Wafer) manufacturing, integrated circuit (IC) manufacturing, and integrated circuit (IC) manufacturing. Package, etc. Among them, the "bare wafer is completed by steps such as forming a semiconductor element on the wafer and dicing the wafer, and each of the bare wafers formed by the wafer dicing" is performed by bonding pads on the bare wafer and After the external signal is electrically connected, the bare chip is then covered with a sealing material. The purpose of the package is to prevent the bare chip from being affected by moisture, heat and noise, and to provide the bare chip and external circuits, such as printed circuits. Printed Circui1: Board (PCB) or other medium for electrical connection between substrates for packaging, so as to complete the packaging step of the integrated circuit. In order to connect the bare chip and the packaging substrate mentioned above, wires (Wiry or Bump) are usually used as the bonding medium. With the increase in the number of chip packages, Multi-Chip Module Packaging (Multi-Chip Module) (Mcm) has gradually become the main trend of future packaging types. Refer to Figure 1 and Figure 1 for a cross-sectional schematic diagram of a conventional multi-chip packaging module. The multi-chip packaging module 100 at least includes One base, board 11 〇9—wafer 130, 150, a packaging material 170. Among them, the wafer 130 is, for example, a logic chip (10 gic ce 11), and the wafer 150 is, for example, a memory crystal.

587315 V. Description of the invention (2) slice (memory cel 1), and the area of the wafer 130 is larger than the area of the wafer 150. The wafer 1 50 is arranged on the active surface of the substrate 1 1 0 with bumps 15 2. The sti ferner ring 140 is arranged on the substrate i 10 around the wafer 150, and the wafer 1 3 0 is stacked. The chip 130 is arranged on the chip 150 and the fixing ring j 4, and the chip 130 is electrically connected to the substrate 11 through a wire 132. The packaging material ι70 is an active surface that covers the wafer 130, 150, the wires 132, and the substrate 110. In addition, pads 1 12 and solder balls 11 4 are also disposed on the back surface of the substrate 1 10. Please refer to FIG. 2. FIG. 2 is a schematic cross-sectional view showing another conventional multi-chip package module. The multi-chip package module 2000 includes at least one substrate 2 10, two chips 230, 250, and a packaging material 270. The wafer 230 is, for example, a memory wafer, and the wafer 250 is, for example, a logic wafer. The area of the wafer 230 is larger than the area of the wafer 250. Wafer 2 3 0 is attached on the active surface of substrate 2 10 with back bonding, and is electrically connected to substrate 210 through wires 2 32. Wafer 2 50 is attached to wafer 23 with back, and wafer 25 is The substrate 2 1 is electrically connected through the lead 2 5 2. The packaging material 270 is an active surface that covers the wafers 230, 250, the wires 232, 252, and the substrate 210. Further, pads 2 1 2 and solder balls 2 1 4 are arranged on the back surface of the substrate 2 10. However, if the package structure of FIG. 1 is used, a fixing ring 140 must be provided between the wafer 150 and the wafer 130 to strengthen the wafer 130 to prevent the wafer 150 from cracking. Moreover, because the wearing area of the wire 1 3 2 is very small and the length is very long, the phenomenon that the signal is rapidly reduced and the signal is delayed will affect the transmission performance of the signal. On the other hand, if the package structure shown in FIG. 2 is used, a larger substrate 2 1 0 needs to be used, so that the substrate 2 1 0 is easily susceptible to thermal expansion with the wafer.

10549twf.ptd Page 7 587315 V. Description of the invention (3) Warpage occurs due to different Coefficient of Thermal Expansion (CTE). Similarly, because the load area of wire 2 52 is very small and the length is very long 'makes The signal will be rapidly attenuated and the signal will be delayed, which will affect the signal transmission performance. Furthermore, when the area of the wafer 25b0 is much smaller than the area of the wafer 2 30, the lead wire 2 52 is easily collapsed and a short circuit occurs with the lead wire 232. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multi-chip package module, which can reduce the stress caused by the difference in thermal expansion coefficient between the substrate and the wafer, thereby avoiding surface warpage of the substrate. Another object of the present invention is to provide a multi-chip package module, which can shorten the signal transmission path between the chip and the substrate to improve the signal transmission efficiency. 0 The accumulation of another chip of the invention The invention provides a multi-chip package including at least one The first objective is to propose a multi-chip packaging module capable of making a first and a packaging material. The wire bonding pad is provided with a surface that is connected to the substrate. The top surface is a packaging material pad, and the bottom surface is provided with a wire system and the substrate is connected to the substrate. And said at least one lower surface wire bonding wafer package module, a substrate and a second piece having an active surface on the active surface. The base slot is the first and second slot and the substrate surface on the slot slot and the substrate, and the material covers the first wafer, the multi-chip package wafer, a plurality of faces, and a plurality of punching systems. Having a previous wafer mainly exposes the wire bonding surface. Electrical properties on the upper surface of the second wafer

10549twf.ptd Page 8 587315 V. Description of the invention (4) The upper and lower surfaces of the board. Moreover, in the above-mentioned multi-chip package module, the second chip can be interposed between the second chip and the substrate by a flip-chip bonding method and electrically connect the two. Moreover, in the above-mentioned multi-chip package module, a second chip can also be bonded to the substrate, and the second chip and the substrate can be electrically connected by wires by means of wire bonding. Moreover, in the above-mentioned multi-chip package module, a third chip can be stacked on the second chip, and the third chip can be electrically connected to the surface on the substrate. From the above, it can be known that, because the elongated holes are arranged in the substrate, when the thermal expansion coefficient of the wafer and the substrate is different and stress is generated, the elongated holes can be used to reduce the stress on the substrate at this time, so as to avoid substrate warping. Moreover, the wafers are individually attached to the upper and lower surfaces of the substrate. Therefore, the problem that the electrical connection path between the conventional chip and the substrate is relatively long can be avoided, and the signal transmission path can be shortened to improve the signal transmission performance. In addition, since the wafers are individually attached to the upper and lower surfaces of the substrate instead of being stacked, there is no need to provide a retaining ring and the problem of wafer cracking does not occur. -% Moreover, because the two wafers are individually attached to the upper and lower surfaces of the substrate, and another wafer is disposed on the wafer disposed on the upper surface, the signal transmission path length is equivalent to the conventional case. Because the packaging structure of the present invention can be configured with more wafers, the multi-chip packaging module can have a higher degree of packaging accumulation.

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In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, if ', a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows:. ^ Embodiments: FIG. 3 is a cross-sectional view of a multi-chip package module according to a preferred embodiment of the present invention, and FIG. 4 is a top view of the multi-chip package module according to a preferred embodiment of the present invention. view. Please refer to Figure 3 and Figure 4 at the same time. The packaging structure 300 of the preferred embodiment of the present invention includes at least a substrate 310, a wafer 330, 350, and a packaging material 370. The wafer 330 is, for example, a logic wafer, and the wafer 350 is, for example, a memory (mem) wafer, and the area of the wafer 330 is larger than the area of the wafer 350. The chip 330 has an active surface 33 2 a and a corresponding back surface 332 b, and the chip 330 also has a bonding pad 334 that surrounds the surrounding positions on the active surface 332 a of the chip 330. The substrate 310 has an upper surface 312a and a lower surface 312b, and each of the upper surface 312a and the lower surface 312b has a wafer setting area 322a and a wafer setting area 322b. The wafer 330 is a wafer setting area 322b with the active surface 332a disposed on the lower surface 3 1 2 b, and the substrate 31 has a plurality of elongated holes (S 1 ot) 3 2 4, among which the elongated holes The 3 2 4 is arranged corresponding to the wire bonding pad 3 3 4 of the wafer 3 3 0 so that the wire bonding pad 3 3 4 of the wafer 3 3 0 'is exposed in the elongated hole 3 2 4. In this embodiment, the slotted holes 3 2 4 are four and are arranged around the wafer self-receiving area 322b. In addition, the substrate 3 1 0 also has a plurality of wire contacts 3 丨 4 and a plurality of bump contacts 3 1 6, wherein the bump contacts 3 1 6 are wafers arranged on the upper surface 3 1 2 a.

587315

Provisioning area 322a. As shown in FIG. 4, some of the wire bonding contacts 314 can be arranged on the wafer arrangement area 322a near the side of the slot 324, and some of the wire bonding contacts 314 can be arranged. On the upper surface 31 2a of the substrate 31 0 near the other side of the slot 324. The wafer 3 5 0 has an active surface 3 5 2 a and a corresponding back surface 352 b ′, and the wafer 350 also has a bump pad 354 disposed on the active surface 352 a of the wafer 330, and the wafer 3 0 0 is formed by convex The blocks 3 56 are electrically connected to the bump contacts 316 of the bump bonding pads 354 and the wafer arrangement area 322a.

In addition, the wafer 330 is passed through the wire 380 to electrically connect the wafer 330 to the substrate 31, and one end of the wire 380 is bonded to the wire bonding pad 334 of the wafer 33. The other end of the wire 380 is bonded to the substrate 31. In addition, the wiring contacts ′ are encapsulating material 370 that covers the wafers 330, 350, the wires 38 (), the upper surface 312a and the lower surface 312 of the substrate 310] ^. Moreover, on the substrate ο surface 314, a solder pad 39 is disposed at a position not covered by the packaging material 370, and a solder ball 392 is disposed on the solder pad 390. In the above-mentioned multi-chip package, In module 3 00, since holes 324 are provided in the substrate 31, when the wafers 330, 35 and the substrate 31 are not stressed by the thermal expansion coefficient, the stress on the substrate 310 can be released through the elongated holes 324 at this time. Avoid warping of the substrate 31. Moreover, since the wafers 330 and 350 are individually attached to the substrate 31, the wafer arrangement area 322b of the table H 12b below and the wafer arrangement area of the upper surface 3i2a can be avoided, so that it can be avoided A problem of long electrical connection between the chip and the substrate can shorten the signal transmission path and improve the signal

587315 V. Description of the invention (7) Transmission efficiency, and can avoid the problem that the wires are easy to collapse and cause short circuit when the wafer area difference is large. Furthermore, since the wafers 3 3 0 and 3 50 are individually attached to the wafer arrangement area 3 2 2 b of the lower surface 3 1 2 b of the substrate 3 10 and the wafer arrangement area 322 a of the upper surface 3 1 2 a, Instead of adopting a stacking method, there is no need to provide a fixing ring, and the problem of chip cracking does not occur.

In the first embodiment, the wafer 350 is electrically connected to the substrate by flip-chip bonding. However, the present invention is not limited to this. Please refer to FIG. 5, which shows a multi-layer circuit according to the second embodiment of the present invention. An enlarged cross-sectional view of the chip package module 'If the reference numerals in this embodiment are the same as those in the preferred embodiment, it means that the components specified in this embodiment are the same as those in the first embodiment. The components are not repeated here. In this embodiment, the wafer 350 is attached to the wafer configuration area 3 2 2 a on the upper surface 312 a of the substrate 31 with the back surface 352 b, and is replaced with a plurality of wire bonding pads 3 5 8 on the wafer 3 5 ^ A plurality of bump pads 354 are provided in the conventional embodiment, and the bump pads 354 are arranged around the active surface 352 a of the wafer 330. In addition, the plurality of bump contacts 316 of the first embodiment are replaced with a plurality of wire bonding contacts 318 on the substrate 310, and are arranged in a wafer configuration area 322 & Then, the wire bonding pad 358 and the wire bonding contact 318 are electrically connected by the conductor f382. In the first embodiment described above, the wafers 330 and 3500 are arranged below the & 9 plate 3 1 0 and the upper surface 3 1 2 b and 3 1 2 a are the wafer arrangement areas 3 2 2 b. , A, however, the present invention is not limited to this. Please refer to FIG. 6, which shows a cross-sectional view of a multi-chip package module of two examples a, a, and J. If the number in this embodiment is the same as the above, The preferred embodiment is the same

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This means that the components specified in this embodiment are identical to those specified in the first and consistent embodiments, and will not be repeated here. In this embodiment, the multi-chip package module 300 of the first embodiment further includes a wafer 4 10. Chip 4 1 0 has an active surface 4 J 2a and a corresponding back surface

4 1 2b, and the wafer 4 1 〇 also has a wire bonding pad 4 j 4, which is arranged on the surrounding surface of the active surface 4 i 2 a of the wafer 4 j Q, and a corresponding wire bonding contact is arranged on the surface 312 a above the substrate 31 〇 32〇. The wafer 41o is attached to the back surface 352b of the wafer 350 with the back surface ", and the wafer 41o is electrically connected to the substrate 310 by a wire 42o, and the -end of the wire 42o is bonded to the wafer 410.

The other end of the wire 42G on the wire bond pad 414 is bonded to the wire contact 3 2 0 of the substrate 31. / In the above-mentioned multi-chip package module 300, the wafers 330 and 350 are individually attached to the lower and upper surfaces H and 322b of the wafer arrangement area 32o of the substrate 31o, and further to the wafer 35o. A chip 410 is arranged on the chip and electrically connected to the substrate. Under the condition that the length of the signal transmission path is equivalent to the conventional one, more chips (3 3 0, 3 5 0, 4 1 0) can be configured in the present invention. : And the moon dagger is enough to make the Shiduo chip packaging module 300 have a higher package accumulation degree. • As mentioned above, the multi-chip package module of the present invention has at least the following multi-chip package modules. When the substrate is provided with a narrow pull-out piece and the substrate has a different thermal expansion coefficient, stress occurs. At this time, the curvature: the stress on the substrate is reduced by the elongated hole, so that the substrate is not warped

587315 V. Description of the invention (9) 2. In the above, the upper and lower sexual connection paths of the substrate are relatively long. Signal transmission performance. 3. It is not necessary to install a fixing ring on the substrate above or below the substrate. 4. In the above-mentioned multi-chip package module attached to the substrate, the wafer is individually attached to the surface. Therefore, the electrical problems of the conventional chip and the substrate can be avoided, and the signal transmission path can be shortened, and the multi-chip surface on the other side can be increased. Multi-chips and the following table will be generated. Even though the present invention has been defined by the present invention to limit the present invention, within any familiarity and scope, it can be used as a protection scope when the attached packaging mold is used instead of the chip package. The structure can have a better practice of this technology in a more patented group. From the problem group that uses stacking cracks, it is more suitable to configure a path with a length enough to provide a higher package. The refining enclosure is defined by the wafer system, so there is a large amount of wafers in which the two crystals are set on the upper surface and the conventional one has a degree of accumulation. As above, however, it does not depart from this issue, so this issue prevails. Don't attach the situation that does not require individual chips

10549twf.ptd Page 14 587315 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional multi-chip package module. FIG. 2 is a schematic cross-sectional view showing another conventional multi-chip package module. FIG. 3 is a schematic cross-sectional view of a multi-chip package module according to a first embodiment of the present invention. Fig. 4 is a schematic top view of a multi-chip package module according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a multi-chip package module according to a second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a multi-chip package module according to a third embodiment of the present invention. Graphical description: 100, 2 0, 30 0: Multi-chip package module 1 1 0, 2 1 0, 3 1 0: Substrate 1 1 2, 2 1 2, 3 9 0: Solder pad 1 14, 214 392: Solder balls 130, 150, 230, 250, 330, 350, 410: Wafers 132, 232, 252, 380, 382, 4 20 ·· Wire 1 5 2, 3 5 6: Bumps' 1 7 0, 2 7 0, 3 7 0: packaging material 3 1 2 a: upper surface 312b: lower surface 3 1 4, 3 1 8, 3 2 0: wire contact

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Claims (1)

587315 VI. Application for patent scope 1. A multi-chip package module, at least comprising: a first chip having an active surface, a plurality of wire bonding pads, and the wire bonding pads are arranged on the active surface; a substrate Having an upper surface, a lower surface and at least one slotted hole, wherein the first chip is arranged on the lower surface of the substrate with the active surface, and the wire bonding pads are exposed in the slotted hole system; A first wire, and the wire bonding pads and the upper surface of the substrate are electrically connected by the first wires; a second chip is disposed on the upper surface of the substrate, and the second chip and the The upper surface of the substrate is electrically connected; and a packaging material covering the first chip, the second chip, the first wires, the upper surface of the substrate and the lower surface of the substrate. 2. The multi-chip package module described in item 1 of the scope of patent application, further comprising a plurality of bumps, the bumps being interposed between the second chip and the substrate, and by the bumps The second chip is electrically connected to the substrate. 3. The multi-chip package module described in item 1 of the patent application scope, further comprising a plurality of second wires, the second chip is attached to the upper surface of the substrate, and the second wires and the The upper surface of the substrate is electrically connected. '4. The multi-chip package module described in item 1 of the scope of patent application, further comprising a third chip, which is stacked on the second chip, and the third chip is electrically connected to the upper surface of the substrate. Sexual connection. 5. The multi-chip package module described in item 4 of the scope of patent application, which 10549twf.ptd Page 17 587315 6. The scope of patent application further includes a plurality of third wires, and the third chip is electrically connected to the upper surface of the substrate through the third wires. 6. The multi-chip package module described in item 1 of the scope of the patent application, wherein a plurality of solder balls are further arranged on the lower surface of the substrate not covered by the packaging material. 7. The multi-chip package module according to item 1 of the scope of patent application, wherein the area of the first chip is larger than the area of the second chip. 8. A multi-chip package module, at least comprising: a first chip having an active surface and a plurality of wire bonding pads, and the wire bonding pads are arranged on the active surface; a substrate having an upper surface A lower surface and at least one elongated hole, wherein the first chip is arranged on the lower surface of the substrate with the active surface, and the wire bonding pads are exposed in the elongated hole system; a plurality of first wires, and The wire bonding pads and the upper surface of the substrate are electrically connected by the first wires; a second chip, wherein the second chip is arranged on the upper surface of the substrate by a flip-chip bonding method And a packaging material 'covering the first chip, the second chip, the first wires, the upper surface of the substrate and the lower surface of the substrate. 9. The multi-chip package module described in item 8 of the scope of patent application / which further includes a plurality of bumps, the bumps are interposed between the second chip and the upper surface of the substrate, and The bumps bond the second wafer to the top surface of the substrate. 10. The multi-chip package module according to item 8 of the scope of patent application, which 10549twf.ptd Page 18 587315 6. The scope of the patent application further includes a third chip, which is stacked on the second chip, and the third chip is electrically connected to the upper surface of the substrate. 11. The multi-chip package module according to item 10 of the scope of patent application, further comprising a plurality of second wires, and the third chip is electrically connected to the upper surface of the substrate through the second wires. . 1 2. The multi-chip package module according to item 8 of the scope of patent application, wherein a plurality of solder balls are further arranged on the lower surface of the substrate not covered by the packaging material. 1 3. The multi-chip package module according to item 8 of the scope of patent application, wherein the area of the first chip is larger than that of the second chip. 14. A multi-chip package module comprising: a first chip having an active surface and a plurality of wire bonding pads, and the wire bonding pads are arranged on the active surface; a substrate having an upper surface, A surface and at least one slotted hole, wherein the first chip is arranged on the lower surface of the substrate with the active surface, and the wire bonding pads are exposed in the slotted hole system; a plurality of first wires, and The first wires are electrically connected to the wire bonding pads and the upper surface of the substrate; a second chip, wherein the second chip is arranged on the upper surface of the substrate by wire bonding; and The packaging material covers the first chip, the second chip, the first wires, the upper surface of the substrate and the lower surface of the substrate. 15. The multi-chip package module according to item 14 of the scope of patent application, further comprising a plurality of second wires, and the second wires are used to make the first wire 10549twf.ptd Page 19 587315 6. Scope of patent application The second chip is electrically connected to the upper surface of the substrate. 16. The multi-chip package module according to item 14 of the scope of patent application, further comprising a third chip, which is stacked on the second chip, and the third chip and the upper surface of the substrate Electrical connection. 1 7. The multi-chip package module according to item 16 of the scope of patent application, further comprising a plurality of third wires, and the third chip is electrically connected to the upper surface of the substrate through the third wires. connection. 1 8. The multi-chip package module according to item 14 of the scope of patent application, wherein a plurality of solder balls are further arranged on the lower surface of the substrate not covered by the packaging material. 19. The multi-chip package module according to item 14 of the scope of patent application, wherein the area of the first chip is larger than that of the second chip. 10549twf.ptd Page 20