TW586237B - Structure of a low temperature polysilicon thin film transistor - Google Patents

Abstract

A structure of a low temperature polysilicon thin film transistor (LTPS-TFT) comprises several polysilicon layers on a substrate, wherein each of the polysilicon layers includes a source region, a drain region and a channel region between the source region and the drain region. A gate dielectric layer is covering the polysilicon layers and a gate is on the gate dielectric layer above the channel regions. An inter-layer dielectric layer is covering the gate. Several source contacts/drain contacts are in the inter-layer dielectric layer and the gate dielectric layer, wherein each of the source contacts/drain contacts are connected to the source/drain correspondingly. A source metal/drain metal is on the inter-layer dielectric layer, wherein the source metal/drain metal are connected to the source contacts/drain contacts.

Description

586237 V. Description of the invention (1) 晷 2 TECHNICAL FIELD The present invention relates to the structure of a thin film transistor, and more particularly to the structure of a low temperature polycrystalline silicon thin film transistor. The low temperature polycrystalline silicon thin film transistor of the previous family is a technology different from the traditional 7 P Amorphous Si 1 icon TFT, and its electron mobility can reach more than 200cm2 / V-sec. Therefore, the thin film transistor element can be made smaller, and the aperture ratio (Aperture Rat io) can be increased, thereby increasing the brightness of the display and reducing the power consumption function. In addition, due to the increase in electron mobility, some driving circuits can be manufactured on the glass substrate at the same time as the thin film transistor process, which greatly improves the characteristics and reliability of the liquid crystal display panel, which greatly reduces the manufacturing cost of the panel, so the manufacturing cost is relatively amorphous. Shi Xi thin film transistor liquid crystal display is much lower. In addition, the low-temperature polycrystalline silicon thin-film electric aa liquid crystal display has the characteristics of thin thickness, light weight, and good resolution, so it is particularly suitable for mobile terminal products that require lightness and power saving. Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a schematic top view of a conventional low-temperature polycrystalline silicon thin film transistor; FIG. ^ Is a schematic cross-sectional view of FIG. The conventional low-temperature polycrystalline silicon thin film transistor includes a polycrystalline silicon layer 106 (including a source region 12, an electrode region 14, and a channel region 13), a gate electrode 108, a source metal layer 102, and an electrodeless metal layer. 104, a gate dielectric layer, an inter_layer dielectric layer 10g, and contact windows 12a, 1 ". Among them, the polycrystalline silicon layer 106 is disposed on the substrate 100, and the polycrystalline silicon Floor

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^, / 系 系 [^ 90% has two exchange regions (source region 12 and electrodeless region 14) and a channel region 13 between the source electrode 12 and electrodeless region 14. , Animal, f 22 1 2? The layer 107 covers the polycrystalline silicon layer 106. The gate is formed on the gate dielectric layer # 7 of # 1 Μ 方. In addition, an intermediate dielectric layer is formed above the substrate 100 and covers the gate electrode 108. Furthermore, the contact window 12a is in the gate dielectric layer 107, and the source is formed in the intermediate dielectric layer 107. The contact window 12a is connected to the dielectric layer 107 via the contact window 12a. 1 and 4 a are disposed on the intermediate dielectric layer 10, the electrode metal layer 102, and the drain metal layer 104, and the source metal layer 102 and the drain metal layer 14a are connected to the source region 12 and the drain. The low-temperature polycrystalline silicon thin-film transistor described in the polar region 14 has a channel length of L, and a channel length of w (as shown in FIG. 1A), and the channel length ratio is w / L. Thin film transistors are designed with large aspect ratios. However, when the low-temperature polycrystalline silicon thin-film transistor with two # 3 length ratios is operated at high current, Ergu is liable to be deteriorated due to the excessive current, which makes the critical voltage of the device re = Id Voltage) and the subcritical slope (sub — Thresh. ld wing) becomes larger, resulting in poor component reliability. The invention of the inner palace Z The purpose of the present invention is to provide a low-temperature polycrystalline silicon thin film electro-crystal structure to solve the conventional low-temperature polycrystalline silicon thin-film transistor's current operation during the conventional large aspect ratio. This leads to the problem of poor component reliability. ^ Invention_ A structure of low temperature polycrystalline silicon thin film transistor, which includes a silicon layer, a gate dielectric layer, a gate electrode, an intermediate dielectric layer,

l〇762twf.ptd V. Description of the invention (3) Several source contact windows, several & drain metals. In the basin :: = contact,-source metal layer and-per-polycrystalline stone layer; package = = is arranged on the-substrate, and between the polar region and the non-polar region,-the drain Area and multiple layers above the source area. In addition, the closed electrode system is arranged on the channel to cover the gate m, and the intermediate dielectric layer is formed above the substrate and the idle dielectric layer; each window system is located in the intermediate dielectric layer to make electrical contact. At the same time, it is related to the corresponding source-source and gate dielectric layers, and each of the two: electrical layer: area and further: the source metal layer is connected to two sides, and belongs to the above-mentioned ones. The source contact window is electrically connected. The electrodeless metal layer is formed in the intermediate dielectric layer and the several electrodeless contact windows mentioned above are electrically connected: the electrode metal region / electrode region / channel region and the gate electrode system—sub-thin electrode The channel width of a sub-thin film transistor is w, the solar body and the mother plane are between (MW:. The degree is W 11 channel length machine, the width-length ratio of 2 is proposed. A low-temperature polycrystalline silicon thin-closed, closed-pole, one Idle dielectric layer, several polycrystalline silicon layers, several source contact windows, several drain contact windows, a source electrode, and a drain metal layer. Among them, the gate system is a matching layer and a system is formed. Above the substrate, t covers the free electrode. The upper number = the electrical layer is arranged on the gate dielectric layer, each polycrystalline stone layer in the # is a pole region, a drain region, and a source region and 10762twf.ptd between the drain regions Page 8 586237 V. Description of the invention (4) Region and the channel region is located on the substrate above the gate, covering the polycrystalline stone: The electrical layer is formed in the In the middle dielectric layer, and each source contact window system spot = system layer *, and each-non-contact window system is in contact with the corresponding one ==. Furthermore, The electrode metal layer is formed in the intermediate dielectric layer. The electrode metal layer is electrically connected to the above-mentioned source contact windows. :: The plurality of drain contact windows are electrically connected. Here, each -source diode region, The channel area and the interfacial system are composed of sub-thin film transistors, and the channel width of each sub-film thunder body is W, the channel length is 丨, and the A palace is between 卞 溥 1 and 8 The length is L, and the width-to-length ratio (W / L) is between the temperature of the low-temperature polycrystalline silicon thin film transistor system of the present invention and several sub-films. By avoiding each sub-film transistor: 10: N (N is the total number of sub-film transistors), so it can avoid the problem of component degradation under high current operation. It is easy to make the above and others. , Features, and advantages can be explained in more detail below + a preferred embodiment, and in conjunction with the attached drawings, detailed

And # Γ | ί According to FIG. 2 and FIG. 2 A, the edge diagram is a top view of a preferred low-temperature polycrystalline silicon thin film transistor according to the present invention. 'Sectional schematic diagram. The low-temperature polycrystalline silicon and transistor of the present invention include several polycrystalline silicon layers 20 6a, 206b to 20 6η, a gate. Page 10762twf.ptd 586237 V. Description of the invention (5) Dielectric layer 1 0 7, a gate 1 〇8, an intermediate dielectric layer 109, several source contact windows 12a, 12b to 12η, several drain contact windows i4a, 14b to 14η, one, source metal layer 102, and one drain metal Layer 1 04. Among them, several polycrystalline silicon layers 206a, 206b to 206η are arranged on a substrate 100, and each of the polycrystalline silicon layers 206a, 206b to 20611 includes a source region, an electrodeless region, and A channel region located between the source region and the non-electrode region. Take the polycrystalline silicon layer 206a in FIG. 2A as an example. The polycrystalline silicon layer 206a includes a source region 202a and a drain region 20. 4a and a channel region 203a located between the source region 202a and the drain region 204a. The gate dielectric layer 107 is located above the substrate 100 and covers the polycrystalline silicon layers 206a, 206b to 206n. In addition, the gate electrode 108 is disposed on the gate dielectric layer 107, and it is disposed correspondingly above the channel region of the polycrystalline silicon layer 206 & 2061) to 2061. The intermediate dielectric layer 109 is formed on the substrate 100 and covers the gate electrode 108. In addition, a plurality of source contact windows 12a, 12b to 12n are located in the intermediate dielectric layer 109 and a gate dielectric layer 107, and each of the source contact windows 12a, 12b to 12n is corresponding to one of them. A source region is in electrical contact (for example, the source contact window 12a is in electrical contact with the source region 202a). Similarly, several drain contact windows 14a ′ 14b to 14η are located in the middle dielectric layer 〇09 and gate dielectric layer 107, and each of the drain contact windows 14a, i4b to 14η is corresponding to the corresponding one of them. First and / or the pole area electrical contact (for example, the drain contact window 4a is in electrical contact with the drain area 204a). Furthermore, the source metal layer 102 is formed on the intermediate dielectric layer 9 and the source metal layer 102 is electrically connected to the source contact window 2a and 2b to 12n.

10762twf.ptd Page 10 586237 V. Description of the invention (6) It is connected so that the source region of each polycrystalline silicon layer 206, 206a to 206η is electrically connected. The light-emitting metal layer 104 is formed on the intermediate dielectric layer 10, and the drain metal layer 104 is electrically connected to the drain contact windows 14a, 14b to 14η, so that each polycrystalline silicon layer is formed. The non-polar regions in 206a, 206b to 206n are electrically connected. Here, the source region / drain region / channel region and the gate electrode 108 of each polycrystalline silicon layer 20 6a, 20 6b to 20 6η constitute a sub-thin film transistor, and each = the channel width of the thin film transistor It is SWn, the channel degree is L, and the channel width-to-length ratio (Wa / L, Wb / L to Wn / L) of each sub-film transistor is, for example, between 0.1 and 8. In a preferred embodiment, each sub-thin-film transistor system is a thin-film transistor in the same form, for example, each sub-thin-film transistor is a p-type thin-film transistor or each sub-thin-film transistor is η Thin film transistor. If the above-mentioned sub-thin-film transistor system is an n-type thin-film transistor, a light and heterodyne drain region is further included between the source / drain region and the channel region of each sub-thin-film transistor, for example, 2A As shown in the figure, a lightly doped drain region 201a is further included between the ^ region / drain region 20 2a / 204a and the channel region 203a of the polycrystalline silicon layer 206a.乂 Therefore, the low-temperature polycrystalline silicon thin film transistor system of the present invention is composed of a plurality of sub-thin thin film transistors in parallel, and each sub-thin film transistor system shares the same gate electrode 8. The source region of the mother-child thin-film transistor is electrically Connected to the same source-, layer 102, the drain region of each sub-film transistor is electrically connected to the same-drain metal layer 104. Because the channel length of each sub-thin-film transistor is ’and the channel width is taken from Wa, Wb to Wn, this low temperature polycrystalline ^ film

586237 V. Description of the invention (7) The channel width ratio (W / L) of the transistor is:

W / L = (Wa + Wb + ........ + Wn) / L The low temperature polycrystalline silicon thin film transistor system of the present invention is made up of several thin film transistors with small channels: aspect ratio. During high current operation, the current flowing through each sub-film transistor is 1 / N of the total current amount (N is the total number of sub-film t crystals). In other words, the current flowing through each sub-film transistor is · IX = IX Wx / (Wa + Wb + ......... +? !!) I x: current flowing through one of the thin film transistors I: total current

Wx: the channel width of one of the sub-thin film transistors. Therefore, the present invention can avoid the deterioration of the device due to the excessive current. The low-temperature polycrystalline silicon thin film transistor system shown in FIG. 2A is a gate-on-type low-temperature polycrystalline silicon thin film transistor (Top Gate LTPS-TFT). However, the present invention is not limited to this type of low-temperature polycrystalline silicon. In thin film transistors, the present invention can also be applied to low-temperature polycrystalline silicon with gates at the bottom

Transistor (Bottom Gate LTPS-TFT), as shown in Figure 2B. In Section 2B 1 FIG. 08 / a cross-sectional view of the eleven sub-thin film transistors is shown, in which the gate system is arranged on the substrate 100, and the polycrystalline stone · 6a system is configured with a gate 108 screen and / Between the pole 1G8 and the polycrystalline broken layer 2G6a, there is also a gate = H \ gate pole Ganm and the polycrystalline stone layer _ is arranged in the same manner as in the second 2A. Other than that, the other components and configuration are the same as in Figure 2A. 10762twf.ptd Page 12 586237 V. Description of the invention (8) The structure of the low-temperature polycrystalline silicon thin film transistor of the present invention is composed of several sub-thin: transistors in parallel In addition to the arrangement, as shown in the figure, the super-fast gate 108 series is a linear gate, and the source metal layer 102 and the non-polar metal layer 104 are respectively a linear source metal layer and A linear drain metal layer, the arrangement of the low-temperature polycrystalline silicon thin film transistor of the present invention can also be shown in FIG. 3. Referring to FIG. 3, the source metal layer 302 has a plurality of source metal layers.卩 302b and a source metal layer connection portion 302a, and each source metal «contact portion 302b is electrically connected to each source contact window 12a, m to 12n, and the source metal layer connection portion 3 〇 2a is a series connection of several source metal layer contact portions 30b. In addition, the drain metal layer 304 has a plurality of drain metal layer contact portions 304b and a drain metal layer connection portion 304a, and each of the drain metal layer contact portions 304b is in contact with each drain electrode, respectively. The windows 14a, Hb to 14n are electrically connected, and the drain metal layer connection portion 300 is connected in series with a plurality of drain metal layer contact portions 304b. In another preferred embodiment, the arrangement of the low-temperature polycrystalline silicon thin film transistor can be as shown in FIG. 4, that is, the gate 408 is a u-shaped gate, and the source metal layer 402 is correspondingly configured. Inside the U-shaped gate 408, the drain metal layer 404 is a u-shaped drain metal layer correspondingly disposed outside the u-shaped gate 408. This arrangement can place more sub-film transistors in a single low-temperature polycrystalline silicon thin-film transistor. In another preferred embodiment, the arrangement of the low-temperature polycrystalline silicon thin film transistor can be as shown in FIG. 5. The same as FIG. 4 is that the gate 408 is ϋ 幵 y gate, and the source is The electrode metal layer 5 〇2 is arranged corresponding to the u-shaped gate 4 〇 8

10762twf.ptd Page 13 586237 V. Description of the invention (9) The internal 'electrodeless metal layer 5 0 4 is a U-shaped electrodeless metal layer correspondingly disposed outside the U-shaped gate 408. In addition, the source metal layer 502 has a plurality of source metal layer contact portions 502b and a source metal layer connection portion, and each source metal layer contact portion 502b is connected to each source contact window 12a. 12b to 12n are electrically connected, and the source metal layer connection portion 502a is a series connection of a plurality of source metal layer contact portions 502b. In addition, the drain metal layer μα has a plurality of drain metal layer contact portions 504b and one drain metal layer contact portion, and each of the 7 drain metal layer contact portions 504b is respectively 'each; the pole contacts are from 14a, 14b to 14η. The drain metal is connected in series with a plurality of drain metal layer contact portions 504b. ^ 8-Low fx: S: is an arrangement of several low-thickness silicon thin-film transistors made up of several sub-thin-film transistors in parallel, however, in the above-mentioned arrangement. It ’s not limited. Although the present invention has been disclosed in a preferred embodiment, such as the upper limit, the present invention, anyone skilled in this art: ... is not intended to be used within the scope. When you can do something outside the scope of the present invention, The attached application patent 2 and retouching 'are therefore subject to the protection of the present invention as defined by the patent.

586237 A brief description of the drawing. Figure 1A: A schematic top view of a conventional low temperature polycrystalline silicon thin film transistor; Figure 1B is a schematic cross section of a conventional low temperature polycrystalline silicon thin film transistor; Figure 2: a preferred embodiment of the present invention Top view of a low temperature polycrystalline silicon thin film transistor; FIG. 2A is a schematic cross-sectional view of a low temperature polycrystalline silicon thin film transistor according to a preferred embodiment of the present invention; FIG. 2B is a low temperature polycrystalline silicon thin film according to another preferred embodiment of the present invention A schematic cross-sectional view of a transistor; FIG. 3 is a schematic top view of a low-temperature polycrystalline silicon thin-film transistor according to another preferred embodiment of the present invention; and FIG. 4 is a schematic view of a low-temperature polycrystalline silicon thin-film transistor according to another preferred embodiment of the present invention. A schematic top view; and FIG. 5 is a top view of a low temperature polycrystalline crystalline thin film transistor according to another preferred embodiment of the present invention. Phoenix Labeling Description 100: Substrate 102, 302, 502: Source metal layers 104, 304, 504: Drain metal layers 106, 206a, 206b to 206η: Polycrystalline stone layer 1 0 7: Gate dielectric layer 1 0 8: Gate 1 0 9: Intermediate dielectric layer 1 2, 2 0 2 a: Source region 13, 203a: Channel region

10762twf.ptd Page 15 586237 Brief description of drawings 14, 204a: Drain regions 12a, 12b to 12η: Source contact windows 14a, 14b to 14η: Drain contact window 2 0 1a: Lightly doped drain region 302a , 502a: source metal layer connection portion 304b, 504b: non-polar metal layer connection portion L: channel length W, Wa, Wb to Wn: channel width

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Claims (1)

586237 VI. Scope of patent application 1. A low-temperature polycrystalline polycrystalline crystalline silicon layer includes a gate dielectric layer and a gate dielectric layer between the > and the pole region, which is covered with a gate electrode and arranged in a An intermediate dielectric layer, a pole; each of the plurality of source contact layers is electrically contacted; each of the plurality of non-contact layers, each of which is electrically non-contact; a source metal layer, a metal The layer system and the source electrodes are metal layers, and the metal layer system forms a sub-film transistor with each of the sources, which is W, and the channel length is L. 2. As the structure of the patent application, each crystal. The structure of the silicon thin film transistor includes: arranged on a substrate, each of the multiple source regions, a drain region, and a channel region located in the source region; covering the polycrystalline silicon layers; Formed on the gate dielectric layer above the channel regions; formed above the substrate, covering the gate window, located in the intermediate dielectric layer and the gate dielectric contact window and corresponding one of the source region windows Located on the intermediate dielectric layer and the gate dielectric contact window are formed on the intermediate dielectric layer with corresponding ones of the drain regions, wherein the source contact window is electrically connected; and formed on the intermediate dielectric On the electrical layer, the drain contact window is electrically connected, the pole region / drain region / channel region and the gate structure and the channel width of each of the sub-thin film transistors surround the low-temperature polycrystalline silicon described in item 1 1. The thin film transistor is a P type thin film transistor. 10762twf.ptd Page 17 586237 VI. Scope of patent application 3 · The structure of the low-temperature polycrystalline silicon thin film electric body as described in item 1 of the scope of patent application, each of which is a η-type crystal system Membrane transistor. 4. The structure of the low-temperature polycrystalline silicon film as described in item 3 of the patent application, wherein each of the thin film transistors further includes a lightly doped drain region disposed in each of the source regions. / Drain region and its channel region. 5. The structure of the low-temperature polycrystalline silicon thin film transistor described in item 丨 of the patent application range, wherein the channel width-to-length ratio (W / L) of each of the sub-thin film transistors is between 0.1 to 8 . 6. The structure of the low-temperature polycrystalline silicon thin film transistor according to item 1 of the scope of the patent application, wherein the gate is a linear gate, and the source metal layer and the drain metal layer are linear sources, respectively. An electrode metal layer and a linear drain metal layer. 7. The structure of the low-temperature polycrystalline silicon thin film transistor according to item 1 of the scope of the patent application, wherein the gate is a U-shaped gate, and the source metal layer is correspondingly arranged inside the U-shaped gate, and The electrodeless metal layer is a u-shaped wave electrode metal layer correspondingly disposed outside the U-shaped gate. 8 · The structure of the low-temperature polycrystalline silicon thin film transistor described in item 1 of the scope of the patent application, wherein the source metal layer has a plurality of source metal layer contacts, and a source metal layer connection portion. The source metal layer contact is electrically connected to each of the source contact windows, and the source metal layer contact is connected in series with the source metal layer contacts. 9 · The low-temperature polycrystalline silicon thin film transistor described in item 丨 of the patent application scope / 6. The structure of the patent application body, the middle part and a drain electrode gold part are connected to each layer separately. A gate electrode, a gate dielectric layer, a plurality of polycrystalline polycrystalline stone layers, and the drain electrode above the gate electrode; And the electrode metal layer has a plurality of drain metal layer contacts, layer connection portions, and each and every of the drain metal layers are in electrical contact with the electrode contact window, and the drain metal is non-polar metal The layer contacts are connected in series. The structure of the left polycrystalline stone thin film transistor includes: placed on a substrate; formed on the substrate to cover the gate electrode; a stone Xi layer disposed on the gate dielectric layer, each of which It includes a source region, a drain region, and a channel region between the source regions, and the channel regions are located on the silicon layer; an intermediate dielectric layer is formed on the substrate and covers the polycrystal A plurality of source contact windows are located in the intermediate dielectric layer, and each of the source contact windows is in electrical contact with a corresponding one or more of the source regions; a plurality of drain contact windows are located in the intermediate dielectric layer. In the electrical layer, each drain contact window system is in electrical contact with a corresponding one or more of the drain regions; a source metal layer is formed on the intermediate dielectric layer, and a straight metal layer is in contact with the A source contact window is electrically connected; and a metal electrode layer is formed on the intermediate dielectric layer, wherein the drain metal layer is electrically connected to the drain contact windows, and the gate system Channel width Each of these source regions / drain regions / channel regions forms a sub-thin film transistor, and each of these sub-films has an electrical w and a channel length of L. ' 10762twf.ptd Page 19 586237 VI. Application for Patent Scope 11 · The structure of the low-temperature polycrystalline silicon thin film transistor described in item 10 of the patent application scope, wherein each of these sub-thin dielectric transistor systems is a p-type thin film Crystal. 1 2 · The structure of the low-temperature polycrystalline silicon thin film transistor as described in item 10 of the scope of the patent application, wherein each of the plurality of thin film transistor systems is an n-type thin film transistor. 1 3 · The structure of the low-temperature polycrystalline silicon thin film transistor described in item 2 of the patent application range, wherein each of the n-type thin film transistors further includes a lightly doped drain region disposed at each of the source electrodes. Region / drain region and its channel region. 1 4 · The structure of the low-temperature polycrystalline silicon thin film transistor as described in item 10 of the scope of the patent application, wherein the channel width-to-length ratio (W / L) of each of the thin transistors is between 0.1 to 8 between. 15 · The structure of the low-temperature polycrystalline silicon thin film transistor as described in the item No. of the application scope, wherein the gate is a linear gate, and the source metal layer and the drain metal layer are respectively, A linear source metal layer and a linear non-polar metal layer. 16 · The structure of the low-temperature polycrystalline silicon thin film transistor described in item 10 of the scope of patent application, wherein the gate is a / U-shaped gate, and the source metal layer is correspondingly arranged inside the U-shaped gate The drain metal layer is a υ-shaped wave electrode metal layer correspondingly disposed outside the U-shaped gate. 17 · The structure of the low-temperature polycrystalline silicon thin film transistor described in item 10 of the scope of the patent application, wherein the source metal layer has a plurality of source metal layer contact portions and a source metal layer connection portion, each of which Source metal layer 10762twf.ptd Buy 20 586237 / 、 Scope of patent application The contact part is electrically connected to each of the source contact windows, and the source metal layer connection part connects the source metal layer contact parts in series. 18. The structure of the low-temperature polycrystalline silicon thin film transistor described in item 0 of the scope of the patent application, wherein the contact portion and a drain gold contact portion are respectively connected to each of the metal layer layers, and the metal electrode layer has a metal property. Each of the drain contact windows is electrically connected to a plurality of drain metal layers and connected to the drain metal layers, and the drain gold portions are connected in series. 10762twf.ptd Page 21