584965 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、絲技術、内容、實施方式及圖式簡單說明） 【發明所屬之技術領域】 本發明係有關於一種半導體元件的製造方法，特別是 有關於一種溝渠式功率型金氧半場效電晶體的製造方法。 【先前技術】 在傳統技術中，金氧半場效電晶體（M〇SFET)的發 展，已經逐漸取代了雙載子電晶體之應用。由於其能節省# 電能及較快的元件切換速度之緣故，金氧半場效電晶體已 成為積體電路巾最常被使用的半導體元件。特定而言，溝 渠式功率型金氧半場效電晶體（p〇WER m〇sfet)的基本 操作和任何的金氧半場效電晶體相同，但是其流通電流可 ，數安培。此外，溝渠式功率型金氧半場效電晶體的優點 疋了、在耗費低功率的狀況下，利用小控制電壓進行元件 的操作。 第1-5圖顯示傳統溝渠式功率型金氧半場效電晶體 的製造流程之剖面示意圖。在第1圖中，先提供-石夕基材 5〇’其中矽基材50作為金氧半場效電晶體的汲極。接著 在石夕基材50 t形成複數個溝渠52。隨後在第2圖中，依 序於溝渠52的侧壁形成閘氧化層54以及在溝渠52中填 入複晶矽i 56。然後蝕刻去除複晶矽層％及閘氧化層 54’並且曝露出發基奸 、 暴材5〇的表面，其中殘留在溝渠52 中的複晶矽層56作為閘極。 接著在第3圖中，於石夕基材5〇的表面上形成一光阻 6 965 均5 8，進行k影製程，藉由遮蔽兩個溝渠5 2之間一部份 的矽基材50表面，此部份的矽基材5〇表面稱為基極區域 68，用於定義源極66。然後進行爐管驅入製程64，以形 成源極66。接著移除矽基材5〇上的光阻層58，如第4 圖所示。最後在第5囷中，沉積介電層6〇及金屬内連線 62，以形成溝渠式功率型金氧半場效電晶體。 上述之溝渠式功率型|氧半場效電晶趙的製程中，需 要使用-光阻層58來覆蓋基極區域68才足以能定義源極 66區域。然而隨著元件的縮小化’在進行光罩對準步驟_ 時’經常會有光罩對準不良的問題，使基極區域68的製 程難度增加，以致於無法利用光阻層58來定義源極M， 造成製程良率的下降。而且當對基極區域68進行驅入製 程時，將會抵消源極區域的原始的電性，使金屬内連線與 源極66的連接變差’導致電晶體的操作性能降低。 因此，如何改善溝渠式功率型金氧半場效電晶體的製 以避免產生光罩對準的問題’以及提高源極區域的電 性連接’已經成為目前半導體業界亟需解決的課題。 【發明内容】 本發明之一目的為提供-種溝渠式功率型金氧半場 效電晶體的製造方法’使用問極罩幕覆蓋閉極區域2 =、並且同時利用此罩幕層形成自動對準的源極區域，以 節省形成源極區域所需要的額外光罩。 本發明另-目的為提供一種溝渠式功 效電晶體的製造方法，藉由覆苔門杌广A 乳千％ 精甶覆蓋閘極區域的罩幕層來形成 584965 自動對準的源極區域，以避免產生源極區域之光罩對 問題。 一根據上述之目的，本發明提出一種溝渠式功率型金氧 半場效電晶體的製造方法。先在矽基材上形成矽磊層，其 中石夕蠢層作為汲極區域，並且於石夕磊層上形成元件區域二 接著對元件區域進行第一植入步驟，以於元件區域中 形成第一摻雜區域。然後對元件區域的第一摻雜區域進行 =一植入步驟，以於第一摻雜區域中形成第二摻雜區域。 奴後進行第一微影蝕刻步驟，以於元件區域中形成複數個¥ 溝渠，且溝渠的深度大於第一摻雜區域的深度。並且依序 於第二摻雜區域上形成一閘氧化層& 一複晶石夕層，以填滿 溝渠’並且藉由溝渠形成閘極區域。 然後進行第二微影蝕刻步驟，藉由一罩幕層覆蓋溝渠 上的閘氧化層及複晶矽層，以形成閘極罩幕，並且曝露出 每一溝渠之間一部份的第二摻雜區域，其中第二摻雜區域 定義為基極區域，且閘極罩幕的寬度大於基極區域的寬、 度。接著去除閘極罩幕層，以曝露出溝渠上的複晶矽層， 以及曝露複晶矽層之間的第二摻雜區域。接著進行毯覆蝕 刻式（Blanket Etching)製程。亦即蝕刻一部份的複晶矽 層，以曝露出閘氧化層，同時蝕刻基極區域，去除一部份 的第二摻雜區域，以曝露出第一摻雜區域，以形成自動對 準的源極區域，其中源極區域介於基極區域與閘極區域之 間。 具體而θ，姓刻製程係對閘極區域的複晶石夕層進行餘 刻，以閘氧化層作為蝕刻停止層，並且在溝渠中留下複晶 8 584965 矽層，以作為閘極區域。更重要的是，當蝕刻閘極區域的 複晶矽層，同時蝕刻基極區域的第二摻雜區域，直至曝露 出第一摻雜區域為止。換言之，利用基極區域將兩個溝渠 之間的第一掺雜區域分成兩個部份，每個部份作為源極區 域。最後在源極區域形成接觸窗，並且進行金屬内連線步 驟，利用一導電層連接於接觸窗，以形成溝渠式功率型金 氧半場效電晶體。 由於本發明之閘極罩幕的寬度大於基極區域的寬 度，當隨著元件縮小而必須減少源極區域以及基極區域的g 寬度，本發明藉由罩幕層覆蓋溝渠上的閘氧化層及複晶矽 層，以形成閘極罩幕，同時定義源極區域，以節省形成源 極區域所需要的光罩。特定而言，本發明的源極區域與導 電層具有較佳的電性接觸。因為本發明之源極區域的上表 面與導電層形成電性接觸，而且源極區域與基極區域具有 一接觸界面，增加了源極區域與導電層的電性接觸。 總之，本發明利用溝渠式功率半導體元件的製造方 法，使用間料幕覆蓋問極區域的表面，並且同時在兩個 閘極區域之間利用此罩幕層形成自動對準的源極區域，以 節省形成源極區域所需要的額外光罩。而且藉由覆蓋閘極 區域的罩幕層來形成自動對準的源極區域，以避免產生源 極區域之光罩對準的問題。 【實施方式】 針對傳統溝渠式功率车道_ - a A L ^ 、刀手牛導體兀件的製造方法的缺 點’本發明提供一種溝渠式#盡；丨〗&匕 再木式功率型金氧半場效電晶體的製 9 584965 造方法，使用罩幕層（例如光阻層）覆蓋閘極區域的表面， 並且同時在兩個閘極區域之間利用此罩幕層形成自動對 準的源極區域，以節省形成源極區域所需要的額外光罩。 而且藉由覆蓋閘極區域的罩幕層來形成自動對準的源極 區域’以避免產生源極區域之光罩對準的問題。 參閱第6_ 12圖，其繪示依據本發明溝渠式功率型金 氧半場效電晶體的製造流程之剖面示意圖。在第6圖中， 先在矽基材100上形成矽磊層102,其中矽磊層1〇2作為 汲極區域，並且於矽磊層上形成元件區域1〇4。而且形成· 矽磊層102的步驟之後，在矽磊層1〇2上形成一場氧化層 (未圖示），並且去除一部份的場氧化矽層，以於矽磊層1〇2 上形成上述之元件區域1〇4。 接著在第7圖中，對元件區域1〇4進行第一植入步 驟，以於元件區域104中形成第一摻雜區域1〇6。然後對 元件區域104的第一摻雜區域106進行第二植入步驟，以 於第一摻雜區域106中形成第二摻雜區域1〇8。本發明較 佳實施例中，植入步驟例如可為爐管驅入或是離子佈植法· 來形成摻雜區域。而且第一摻雜區域1〇6的摻質之電性與 第二摻雜區域108之電性相反，例如可為N型或是p型 之摻質。其中第一摻雜區域1〇6的摻質例如可為硼，第二 摻雜區域108的摻質例如可為磷。 隨後在第8圖中，進行第一微影蝕刻步驟，以於元件 區域104中形成複數個溝渠110,且溝渠11〇的深度大於 第一摻雜區域106的深度。並且依序於第二摻雜區域ι〇8 上形成一閘氧化層m及一複晶矽層114，以填滿溝渠 10 584965 11 Ο ’並且藉由溝渠11 0形成閘極區域丨i 6。本發明較佳 實施例中’例如以熱氧化法形成閘氧化層丨12，其中閘氧 化層112的厚度介於100至8〇0埃之間。此外利用化學氣 相沉積（Chemical Vapor Deposition，CVD)法形成複晶矽 層114，而複晶矽層114的厚度介於woo至8000之間。 然後在第9圖中，進行第二微影蝕刻步驟，藉由一罩 幕層118覆蓋溝渠11〇上的閘氧化層112及複晶矽層 114，以形成閘極罩幕118a，並且曝露出每一溝渠u〇之 間一部份的第二摻雜區域108,其中第二摻雜區域ι〇8定嫌H 義為基極區域120，用以連接至金屬内連線，且閘極罩幕 118a的寬度大於基極區域120的寬度。具體而言，在複 晶矽層114上形成一光阻層118，然後利用一光罩對光阻 層118進行曝光顯影的步驟，利用所形成的光阻圖案作為 閘極罩幕11 8，並且藉由此閘極罩幕11 8覆蓋於閘極區域 Π 6上，同時在兩個閘極區域116之間利用此罩幕層丨i 8 定義源極區域。接著在第10圖中，去除閘極罩幕層U8a， 以曝露出溝渠上的複晶矽層114，以及曝露複晶矽層丨丨4 · 之間的第二摻雜區域108。 接著在第11圖中，進行毯覆蝕刻式（Blanket Etching) 製程，蝕刻試劑包含He、Cl2、HBr、C2F6、SF6及〇2之 試劑。亦即蚀刻一部份的複晶矽層114，以曝露出閘氧化 層112，同時蝕刻基極區域120，去除一部份的第二摻雜 區域108，以曝露出第一摻雜區域106，以形成自動對準 的源極區域122，其中源極區域122介於基極區域12〇與 閘極區域116之間。 11 584965 具體而言，餘刻製程係對閘極區域116的複晶石夕層 114進行蝕刻，以閘氧化層112作為蝕刻停止層，並且： 溝渠中留下複晶矽層114，以作為閘極區$ 116。更重要 的是，當蝕刻閘極區域116的複晶矽層114，同時蝕刻基 極區域120的第二摻雜區域1〇8，直至曝露出第一摻雜區 域106為止。換言之，利用基極區域12〇將兩個溝渠ιι〇 之間的第一摻雜區域1 0 8分成兩個部份，每個部份作為源 極區域122。 本發明較佳實施例中，蝕刻複晶矽層丨14的蝕刻劑例· 如可為He、Cl2、HBr、C2F6、SFj 〇2之試劑，基極區 域120的深度介於2500至45〇〇埃之間。此外，於蝕刻一 部份的複晶矽層114的步驟及同時蝕刻基極區域12〇的步 驟之後，更包含對基極區域120進行摻雜步驟，藉由增加 基極區域120的摻質濃度，以提高金屬内連線與源極區域 122的電性接觸。 最後在第12圖中，於閘極區域116及源極區域122 形成一介電層124，以覆蓋元件區域104，接著在源極區傷 域122形成接觸窗126,並且進行金屬内連線步驟，利用 一導電層128連接於接觸窗126,以形成溝渠式功率型金 氧半場效電晶體。 由於本發明之閘極罩幕118a的寬度大於基極區域 120的寬度，當隨著元件縮小而必須減少源極區域122以 及基極區域120的寬度，本發明藉由罩幕層118覆蓋溝渠 110上的閘氧化層112及複晶矽層114，以形成閘極罩幕 118a，同時定義源極區域122，以節省形成源極區域122 12 584965 所需要的光罩。換言之，在溝渠式功率型金氧半場效電晶 體的製程中’由於黃光製程的控制不易或是製程機台精度 的限制’以致於無法精確控制基極區域12〇的寬度。本發 明利用閘極罩幕11 8覆蓋閘極區域11 6上方的複晶矽層 u4 ’並且對;ε夕蠢層1〇2進行淺層蝕刻，以同時形成源極 區域122 ’節省使用源極光罩以及避免源極光罩對準不易 的問題。 特定而言，本發明的源極區域丨22與導電層128具有 較佳的電性接觸。因為本發明之源極區域丨22的上表面與 導電層128形成電性接觸，而且源極區域122與基極區域 120具有一接觸界面，增加了源極區域122與導電層128 的電性接觸。相較於傳統只使用源極區域的上表面連接於 導電層’本發明之源極區域122的接觸界面優於習知技 術’亦即本發明蝕刻穿透第二摻雜區域1〇8，藉由源極區 域122與導電層128形成較大的接觸界面，使電晶體在關 閉狀態（Turn Off)具有較高的崩潰電壓，以提升電晶體的584965 发明 Description of the invention (the description of the invention should state: the technical field, silk technology, content, embodiments and drawings of the invention briefly) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device. In particular, it relates to a method for manufacturing a trench-type metal-oxide-semiconductor field-effect transistor. [Previous Technology] In the traditional technology, the development of metal oxide half field effect transistors (MOSFETs) has gradually replaced the application of bipolar transistors. Because of its ability to save # power and faster component switching speeds, metal-oxide-semiconductor field-effect transistors have become the most commonly used semiconductor components for integrated circuit towels. In particular, the basic operation of a trench power type MOSFET is the same as that of any MOSFET, but its current can be several amps. In addition, the advantages of trench power metal-oxide-semiconductor field-effect transistors are simple. In the case of low power consumption, the device is operated with a small control voltage. Figures 1-5 show a schematic cross-sectional view of the manufacturing process of a conventional trench-type metal-oxide-semiconductor field-effect transistor. In the first figure,-Shi Xi substrate 50 'is provided first, wherein the silicon substrate 50 is used as the drain of a gold-oxygen half field effect transistor. Next, a plurality of trenches 52 are formed on the Shixi substrate 50 t. Subsequently, in FIG. 2, a gate oxide layer 54 is sequentially formed on the sidewall of the trench 52 and a polycrystalline silicon i 56 is filled in the trench 52. Then, the polycrystalline silicon layer% and the gate oxide layer 54 'are removed by etching and the surface of the substrate 50 and the exposed material 50 is exposed. The polycrystalline silicon layer 56 remaining in the trench 52 serves as a gate. Then in FIG. 3, a photoresist 6 965 and 5 8 are formed on the surface of Shi Xi substrate 50, and a k-image process is performed to shield a part of silicon substrate 50 between two trenches 5 2 The surface of this part of the silicon substrate 50 is called the base region 68 and is used to define the source 66. Then, a furnace tube driving process 64 is performed to form a source electrode 66. Next, the photoresist layer 58 on the silicon substrate 50 is removed, as shown in FIG. 4. Finally, in the fifth step, a dielectric layer 60 and a metal interconnect 62 are deposited to form a trench-type power-type metal-oxygen half field-effect transistor. In the above-mentioned trench power type | oxygen half field effect transistor manufacturing process, a photoresist layer 58 is needed to cover the base region 68 to be sufficient to define the source 66 region. However, with the shrinking of the components 'the mask alignment step _' often has the problem of poor mask alignment, which makes the process of the base region 68 more difficult, so that the photoresist layer 58 cannot be used to define the source Pole M, resulting in a decrease in process yield. Moreover, when the driver process is performed on the base region 68, the original electrical properties of the source region will be offset, and the connection between the metal interconnects and the source 66 will be deteriorated ', resulting in a decrease in the operating performance of the transistor. Therefore, how to improve the production of trench-type metal-oxide-semiconductor field-effect transistors to avoid the problem of mask alignment 'and to improve the electrical connection in the source region' has become an urgent problem for the semiconductor industry. [Summary of the Invention] An object of the present invention is to provide a method for manufacturing a trench-type power-type metal-oxide-semiconductor half-field-effect transistor. Source area to save the extra mask needed to form the source area. Another object of the present invention is to provide a method for manufacturing a trench-type power transistor, by forming a cover layer covering the gate region with a moss-covered gate A wide-range milk, and forming a 584965 self-aligned source region. Avoid masking problems in the source area. According to the above object, the present invention provides a method for manufacturing a trench-type power type metal-oxide-semiconductor field-effect transistor. First, a silicon epitaxial layer is formed on a silicon substrate, in which the Shi Xilei layer is used as a drain region, and a device region is formed on the Shi Xilei layer. Then a first implantation step is performed on the device region to form a first region in the device region. A doped region. An implantation step is performed on the first doped region of the device region to form a second doped region in the first doped region. After that, a first lithography etching step is performed to form a plurality of trenches in the device region, and the depth of the trenches is greater than the depth of the first doped region. And a gate oxide layer & a polycrystalline stone layer is sequentially formed on the second doped region to fill the trench ′ and the gate region is formed by the trench. Then, a second lithography etching step is performed to cover the gate oxide layer and the polycrystalline silicon layer on the trench with a mask layer to form a gate mask, and a part of the second dopant between each trench is exposed. The impurity region, wherein the second doped region is defined as the base region, and the width of the gate mask is larger than the width and degree of the base region. Then, the gate shield layer is removed to expose the polycrystalline silicon layer on the trench and the second doped region between the polycrystalline silicon layer. The blanket Etching process is then performed. That is, a part of the polycrystalline silicon layer is etched to expose the gate oxide layer, while the base region is etched, and a part of the second doped region is removed to expose the first doped region to form an automatic alignment. Source region, wherein the source region is between the base region and the gate region. Specifically, θ, the engraving process is performed on the polycrystalline spar layer in the gate region, using the gate oxide layer as an etch stop layer, and leaving a polycrystalline 8 584965 silicon layer in the trench as the gate region. More importantly, when the polycrystalline silicon layer in the gate region is etched, the second doped region in the base region is simultaneously etched until the first doped region is exposed. In other words, the base region is used to divide the first doped region between the two trenches into two parts, and each part serves as a source region. Finally, a contact window is formed in the source region, and a metal interconnecting step is performed, and a conductive layer is used to connect to the contact window to form a trench-type metal-oxide-semiconductor field-effect transistor. Since the width of the gate mask of the present invention is larger than the width of the base region, when the width of the source region and the base region must be reduced as the component shrinks, the present invention covers the gate oxide layer on the trench by the mask layer And a polycrystalline silicon layer to form a gate mask, and at the same time define a source region to save the photomask needed to form the source region. In particular, the source region of the present invention has better electrical contact with the conductive layer. Because the upper surface of the source region of the present invention is in electrical contact with the conductive layer, and the source region and the base region have a contact interface, the electrical contact between the source region and the conductive layer is increased. In summary, the present invention utilizes a trench-type power semiconductor device manufacturing method, which uses an intermediate material curtain to cover the surface of an interrogation region, and simultaneously uses this mask layer between two gate regions to form an automatically aligned source region, so that Save the extra mask needed to form the source area. Furthermore, a mask layer covering the gate region is used to form an automatically aligned source region to avoid the problem of mask alignment in the source region. [Embodiment] Aiming at the shortcomings of the traditional trench-type power lane _-a AL ^ and the manufacturing method of the knife-hand cattle conductor element, the present invention provides a trench-type ##; 〖〗 & dagger-wood type power type metal-oxygen half field The manufacturing method of the effect transistor 9 584965 uses a mask layer (such as a photoresist layer) to cover the surface of the gate region, and simultaneously uses the mask layer to form an automatically aligned source region between the two gate regions. To save the extra mask needed to form the source area. Moreover, a mask layer covering the gate region is used to form an automatically aligned source region 'to avoid the problem of mask alignment of the source region. Refer to FIG. 6-12, which is a schematic cross-sectional view showing a manufacturing process of a trench power metal-oxide-semiconductor field-effect transistor according to the present invention. In FIG. 6, a silicon oxide layer 102 is first formed on a silicon substrate 100, where the silicon oxide layer 102 is used as a drain region, and a device region 104 is formed on the silicon oxide layer. Furthermore, after the step of forming the silicon layer 102, a field oxide layer (not shown) is formed on the silicon layer 102, and a part of the field silicon oxide layer is removed to form the silicon layer 102. The above-mentioned element area 104. Next, in FIG. 7, a first implantation step is performed on the element region 104 to form a first doped region 106 in the element region 104. A second implantation step is then performed on the first doped region 106 of the element region 104 to form a second doped region 108 in the first doped region 106. In a preferred embodiment of the present invention, the implantation step may be, for example, furnace tube driving or ion implantation to form a doped region. Moreover, the electrical properties of the dopants of the first doped region 106 are opposite to those of the second doped region 108, and may be, for example, N-type or p-type dopants. The dopant of the first doped region 106 may be, for example, boron, and the dopant of the second doped region 108 may be, for example, phosphorus. Subsequently, in FIG. 8, a first lithography etching step is performed to form a plurality of trenches 110 in the device region 104, and the depth of the trenches 110 is greater than the depth of the first doped region 106. A gate oxide layer m and a polycrystalline silicon layer 114 are sequentially formed on the second doped region ι 08 to fill the trench 10 584965 11 ′ and to form a gate region 丨 i 6 through the trench 11 0. In the preferred embodiment of the present invention, for example, the gate oxide layer 12 is formed by a thermal oxidation method, wherein the thickness of the gate oxide layer 112 is between 100 and 800 angstroms. In addition, a chemical vapor deposition (Chemical Vapor Deposition, CVD) method is used to form the polycrystalline silicon layer 114, and the thickness of the polycrystalline silicon layer 114 is between woo and 8000. Then in FIG. 9, a second lithography etching step is performed, and a gate oxide layer 112 and a polycrystalline silicon layer 114 on the trench 11 are covered by a mask layer 118 to form a gate mask 118 a and exposed. A portion of the second doped region 108 between each trench u0, wherein the second doped region ι〇8 is defined as H and is used as a base region 120 for connecting to a metal interconnect and a gate shield The width of the curtain 118a is larger than the width of the base region 120. Specifically, a step of forming a photoresist layer 118 on the polycrystalline silicon layer 114, and then exposing and developing the photoresist layer 118 by using a photomask, using the formed photoresist pattern as the gate mask 118, and As a result, the gate mask 11 8 covers the gate region Π 6, and the mask region 丨 i 8 is used to define the source region between the two gate regions 116. Next, in FIG. 10, the gate mask U8a is removed to expose the polycrystalline silicon layer 114 on the trench and the second doped region 108 between the polycrystalline silicon layer 丨 4 ·. Next, in FIG. 11, a blanket etching process is performed. The etching reagent includes He, Cl2, HBr, C2F6, SF6, and 〇2 reagents. That is, a part of the polycrystalline silicon layer 114 is etched to expose the gate oxide layer 112, while the base region 120 is etched, and a part of the second doped region 108 is removed to expose the first doped region 106. In order to form an automatically aligned source region 122, the source region 122 is interposed between the base region 120 and the gate region 116. 11 584965 Specifically, the post-etching process is to etch the polycrystalline stone layer 114 in the gate region 116, use the gate oxide layer 112 as an etch stop layer, and: leave the polycrystalline silicon layer 114 in the trench as a gate Polar area $ 116. More importantly, when the polycrystalline silicon layer 114 of the gate region 116 is etched, the second doped region 108 of the base region 120 is simultaneously etched until the first doped region 106 is exposed. In other words, the base region 120 is used to divide the first doped region 108 between the two trenches ιιm into two parts, and each part serves as the source region 122. In the preferred embodiment of the present invention, examples of the etchant for etching the polycrystalline silicon layer 14 include a reagent such as He, Cl2, HBr, C2F6, and SFj 〇2, and the depth of the base region 120 is between 2500 and 4500. Between Egypt. In addition, after the step of etching a part of the polycrystalline silicon layer 114 and the step of simultaneously etching the base region 120, the method further includes a doping step for the base region 120 to increase the dopant concentration of the base region 120. To improve the electrical contact between the metal interconnect and the source region 122. Finally, in FIG. 12, a dielectric layer 124 is formed on the gate region 116 and the source region 122 to cover the element region 104, and then a contact window 126 is formed on the source region damage region 122, and a metal interconnection step is performed. A conductive layer 128 is connected to the contact window 126 to form a trench type power metal-oxide half field effect transistor. Since the width of the gate mask 118a of the present invention is greater than the width of the base region 120, when the width of the source region 122 and the base region 120 must be reduced as the device shrinks, the present invention covers the trench 110 with the mask layer 118 The gate oxide layer 112 and the polycrystalline silicon layer 114 are formed thereon to form the gate mask 118a, and the source region 122 is defined at the same time, so as to save the photomask required to form the source region 122 12 584965. In other words, in the manufacturing process of the trench-type metal-oxide-semiconductor field-effect transistor, 'because the control of the yellow light process is not easy or the precision of the process machine is limited', it is impossible to accurately control the width of the base region 120. In the present invention, the gate mask 118 is used to cover the polycrystalline silicon layer u4 'above the gate region 116, and shallow etching is performed on the epsilon layer 102 to simultaneously form the source region 122' to save the use of source light. Cover and avoid the problem of difficult alignment of the source mask. In particular, the source region 22 of the present invention and the conductive layer 128 have better electrical contact. Because the upper surface of the source region 22 of the present invention makes electrical contact with the conductive layer 128, and the source region 122 and the base region 120 have a contact interface, the electrical contact between the source region 122 and the conductive layer 128 is increased. . Compared with the conventional method, only the upper surface of the source region is connected to the conductive layer. The contact interface of the source region 122 of the present invention is better than the conventional technique. That is, the etching of the present invention penetrates the second doped region 108. A larger contact interface is formed between the source region 122 and the conductive layer 128, so that the transistor has a higher breakdown voltage in the Turn Off state to improve the transistor's
綜上所述’本發明利用溝渠式功率半導體元件的製造 方法，使用罩幕層覆蓋閘極區域附近，並且同時在兩個閘 極區域之間利用此罩幕層形成自動對準的源極區域，以節 省形成源極區域所需要的額外光罩。而且藉由覆蓋閘極區 域的罩幕層來形成自動對準的源極區域，以避免產生源極 區域之光罩對準的問題。進一步利用源極區域與導電層形 成較大的接觸界面，使電晶體在關閉狀態（Turn 〇ff)具有 較高的崩潰電壓，提升電晶體的操作性能。 13 584965 本發明已揭示較佳實施例如上，僅用於幫助瞭解本發 明之實施’非用以限定本發明之精神，而熟悉此領域技藝 者於領悟本發明之精神後，在不脫離本發明之精神範圍 内’當可作些許更動潤飾及等同之變㈣換， 範圍當視後附之申請專侧及其等同領域 【圖式簡單說明】 為使本發明之上述和其他目的、特徵及優 懂，配合後附圖式，作詳細說明如下： 尺貝易 第1-5圖顯示傳統溝渠式功率型金氧半場效電In summary, the method for manufacturing a trench-type power semiconductor device according to the present invention uses a mask layer to cover the vicinity of a gate region, and simultaneously uses the mask layer to form an automatically aligned source region between two gate regions. To save the extra mask needed to form the source area. Furthermore, a mask layer covering the gate region is used to form an automatically aligned source region to avoid the problem of mask alignment in the source region. Further, a larger contact interface is formed between the source region and the conductive layer, so that the transistor has a higher breakdown voltage in the turn-off state, and the operation performance of the transistor is improved. 13 584965 The disclosed preferred embodiments of the present invention are only used to help understand the implementation of the present invention. It is not intended to limit the spirit of the present invention, and those skilled in the art will not depart from the present invention after understanding the spirit of the present invention. Within the scope of the spirit ', some modifications and equivalent changes can be made. The scope should be based on the attached application and its equivalent [Simplified illustration of the drawings] In order to make the above and other purposes, features and advantages of the present invention Yes, with the following drawings, the detailed description is as follows: Figure 1-5 shows the traditional trench power type metal-oxygen half-field effect power
晶 體 的製造流程之剖面示意圖；以及 第6-12时示依據本發明溝渠式功率 電晶體的製造流程之剖面示意圖。 、乳牛场效 【元件代表符號簡單說明】 50 矽基材 54 閘氧化層 58 光阻層 62 金屬内連線 66 源極 100 矽基材 104 元件區域 108 第二摻雜β 112 閘氧化層 116 閘極區域 118a 閘極罩幕 52 溝渠 56複晶矽層 6〇 介電層 64驅入製程 6 8 基極區域 1 02 矽磊層 10 6 坌 第—摻雜區域 110溝渠 114複晶矽芦 "8 I幕層9 120基極區域 14 584965 122 源極區域 124 介電層 126 接觸窗 128 導電層A schematic sectional view of the manufacturing process of the crystal; and a schematic sectional view of the manufacturing process of the trench power transistor according to the present invention at time 6-12. 、 Dairy field effect [Simple description of component representative symbols] 50 silicon substrate 54 gate oxide layer 58 photoresist layer 62 metal interconnect 66 source 100 silicon substrate 104 element region 108 second doped β 112 gate oxide layer 116 gate Electrode region 118a gate mask 52 trench 56 polycrystalline silicon layer 60 dielectric layer 64 driving process 6 8 base region 1 02 silicon epitaxial layer 10 6 first-doped region 110 trench 114 polycrystalline silicon reed " 8 I curtain layer 9 120 base region 14 584965 122 source region 124 dielectric layer 126 contact window 128 conductive layer
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