TWI751697B - Method for manufacturing trench type semiconductor device - Google Patents

Abstract

A method for manufacturing a trench type semiconductor device includes the following steps. First, an epitaxial layer is formed on a substrate, then a trench is formed in the epitaxial layer, and a gate structure is formed in the trench. The gate structure includes an upper gate and a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in and above the upper gate.

Description

Manufacturing method of trench semiconductor device

The present invention relates to a method for manufacturing a semiconductor element. In particular, it relates to a method of manufacturing a trench semiconductor device.

Power Metal Oxide Semiconductor Field Effect Transistor (Power MOSFET), referred to as power transistor for short, is currently widely used in analog circuits and digital circuits as field effect transistors. Power MOSFETs have very low on-resistance and have the advantages of very fast switching speed, so they have become the mainstream of power components at present.

The structure of the power metal-oxide semi-field effect transistor can be classified according to the current flow path. The current flowing in parallel on the surface of the element is called horizontal type, and the current flowing vertically is called vertical type. The drain terminal of the vertical power MOSFET is made at the lower end of the element, so the resistance per unit chip area can be reduced.

In addition, trench gate power MOSFETs can reduce on-resistance and become the mainstream of high-frequency and low-voltage power components. For electronic power, reducing on-resistance and gate capacitance helps to improve the response speed of power components and improve product quality.

SUMMARY The purpose of this summary is to provide a simplified summary of the disclosure to give the reader a basic understanding of the disclosure. This summary is not an exhaustive overview of the disclosure, and it is not intended to identify key/critical elements of embodiments of the invention or to delineate the scope of the invention.

One objective of the present invention is to provide a method for manufacturing a trench semiconductor element, which can further reduce the input capacitance and reverse transfer capacitance of the semiconductor element, increase the output capacitance, and effectively improve the switching speed of the semiconductor element.

In order to achieve the above-mentioned purpose, one technical aspect of the present invention relates to a method for manufacturing a trench semiconductor device including the following steps. First, an epitaxial layer is formed on a substrate, and then a trench is formed in the epitaxial layer. layer, and a gate structure is formed in the trench, wherein the gate structure includes an upper gate, a lower gate and an intermediate insulating portion, and the intermediate insulating portion is located between and above the upper gate.

In some embodiments, the method for fabricating the trench semiconductor device further includes depositing a first oxide layer in the trench, and depositing a first polysilicon layer on the first oxide layer and in the trench.

In some embodiments, the thickness of the first oxide layer is between about 2000 angstroms (Ångström; Å) and 3000 angstroms, and the thickness of the first polysilicon layer is between about 3000 angstroms and 8000 angstroms, and fills the trenches.

In some embodiments, the method for fabricating the trench semiconductor device further includes etching back the first polysilicon layer to a position about 0.7 micrometers to 1.2 micrometers below the upper surface of the first oxide layer.

In some embodiments, the method for fabricating the trench semiconductor device further includes etching back the first oxide layer to a position about 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer to form a first dielectric Floor.

In some embodiments, the method for fabricating the trench semiconductor device further includes oxidizing the surfaces of the epitaxial layer and the first polysilicon layer to form a gate oxide layer, and using the gate oxide layer and the first dielectric layer Cover the lower gate.

In some embodiments, the method for fabricating the trench semiconductor device further includes depositing a second polysilicon layer to fill the trench, and etching back the second polysilicon layer to below the upper surface of the gate oxide layer About 1000 angstroms to 1500 angstroms.

In some embodiments, the method for fabricating the trench semiconductor device further includes depositing a second oxide layer, and blanket etching the second oxide layer to form an upper surface of the second polysilicon layer in the trench. The spacer, and using the spacer as a mask, self-aligned etching of the second polysilicon layer to form an upper gate.

In some embodiments, the method for fabricating the trench semiconductor device further includes depositing a third oxide layer, etching back the third oxide layer and the spacers to form an intermediate insulating portion, and the intermediate insulating portion, the gate oxide layer and the The first dielectric layer covers the upper gate electrode.

In some embodiments, the trench semiconductor device fabrication method further includes ion implantation in the epitaxial layer, heating for ion drive in, and using a source mask to define a source region.

In some embodiments, the method for fabricating the trench semiconductor device further includes forming a second dielectric layer on the gate oxide layer, and etching the second dielectric layer and the gate oxide layer by using a contact region mask, so as to A plurality of openings are formed, and a metal layer is deposited on the second dielectric layer and in the openings.

Therefore, the method for manufacturing a trench semiconductor device disclosed in the present invention can manufacture a power MOSFET, effectively reduce the size of the upper gate through the intermediate insulating portion, and use a self-aligned etching process to accurately form The upper gate is located between the first dielectric layer, the intermediate insulating part and the gate oxide layer, and the lower gate is covered by the first dielectric layer and the gate oxide layer, which effectively improves the gate capacitance characteristics , and improve the gate response speed.

The following examples are described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit the order of its execution. Any recombination of elements The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn on the original scale. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.

In addition, the terms (terms) used in the entire specification and the scope of the patent application, unless otherwise specified, usually have the ordinary meaning of each term used in this field, the content disclosed herein and the special content. . Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the present disclosure.

In the embodiments and the scope of the patent application, unless there is a special limitation on the article in the context, "a" and "the" may refer to a single or plural. The numbers used in the steps are only used to mark the steps for the convenience of description, and are not used to limit the sequence and implementation.

Secondly, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, which means including but not limited to.

FIG. 1 to FIG. 10 are partial cross-sectional schematic diagrams illustrating the process steps of a trench semiconductor device according to an embodiment of the present invention. Referring to FIG. 1 to FIG. 10, a method of fabricating a trench semiconductor device will be described. The fabrication method of the trench semiconductor device includes the following steps. First, referring to FIG. 1 , an epitaxial layer 120 is formed on a substrate 110 , and a trench 122 is formed in the epitaxial layer 120 . In some embodiments, the substrate 110 is an N-type semiconductor substrate or a P-type semiconductor substrate. Taking a silicon substrate as an example, the N-type conductive impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, and The P-type conductivity impurities are trivalent element ions, such as boron ions, aluminum ions, or gallium ions.

In addition, the epitaxial layer 120 has the same conductivity type as the substrate 110 , but the doping concentration of the epitaxial layer 120 is generally lower than that of the substrate 110 . When the substrate 110 has a high concentration of N-type doping, the epitaxial layer 120 may have a low concentration of N-type doping, but the invention is not limited to this.

In some embodiments, the width of the trenches 122 is between about 0.5 micrometers and 1 micrometer, and the depth of the trenches 122 is between about 1.5 micrometers and 2.0 micrometers.

Next, referring to FIG. 2 , a first oxide layer 130 is deposited in the trench 122 , and then a first polysilicon layer 140 is deposited on the first oxide layer 130 and in the trench 122 . In some embodiments, the thickness of the first oxide layer 130 is about 2000 angstroms (Ångström; Å) to 3000 angstroms, and the thickness of the first polysilicon layer 140 is about 3000 angstroms to 8000 angstroms, and is used for filling Groove 122 .

Referring to FIG. 3 , the first polysilicon layer 140 is etched back so that the upper surface of the first polysilicon layer 140 is lower than the upper surface of the first oxide layer 130 by about 0.7 μm to 1.2 μm. Then, the first oxide layer 130 is etched back to a position about 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer 140 to form a first dielectric layer 132 . In some embodiments, wet etching is used to etch back the first oxide layer 130 , and the first oxide layer 130 on the side of the trench 122 is removed so that it is lower than the upper surface of the first polysilicon layer 140 by about 1000 angstroms to 1500 angstroms, and the surfaces of the first polysilicon layer 140 and the epitaxial layer 120 are exposed.

Referring to FIG. 4 , the exposed surfaces of the first polysilicon layer 140 and the epitaxial layer 120 are then oxidized to form a gate oxide layer 150 . Next, a second polysilicon layer 160 is deposited to fill the space of the trench 122 . In some embodiments, the thickness of the gate oxide layer 150 is about 500 angstroms to 1000 angstroms. The thickness of the second polysilicon layer 160 is about 3000 angstroms to 8000 angstroms and fills the space of the trench 122 . In some embodiments, the gate oxide layer 150 includes a first portion 152 and a second portion 154, the first portion 152 is formed by oxidizing the exposed surface of the first polysilicon layer 140, and the second portion 154 is formed by epitaxy The exposed surface of the crystal layer 120 is formed by oxidation. The first portion 152 of the gate oxide layer 150 and the first dielectric layer 132 cover the lower gate electrode 142 , so that the lower gate electrode 142 is sealed in the first dielectric layer 132 and the gate oxide layer 150 .

Referring to FIG. 5 , as shown in the figure, the second polysilicon layer 160 is etched back to a position about 1000 angstroms to 1500 angstroms below the upper surface of the gate oxide layer 150 to form a recessed polysilicon layer 162 . Next, a second oxide layer 170 , such as a silicon oxide layer with a thickness of about 2000 angstroms to 3000 angstroms, is deposited to fill the recessed portion of the recessed polysilicon layer 162 in the trench 122 .

Referring to FIG. 6, as shown in the figure, the second oxide layer 170 is blanket etched to form the upper surface of the concave polysilicon layer 162 formed by the second polysilicon layer 160 in the trench 122. Spacer 172 . In some embodiments, the length of the spacers 172 is between about 1500 angstroms and 2200 angstroms.

Then, referring to FIG. 7, as shown in the figure, using the spacer 172 as a mask, the lower concave polysilicon layer 162 formed by self-aligned etching of the second polysilicon layer 160 is used to form the desired upper gate 164 .

Then, referring to FIG. 8 , a third oxide layer 180 is deposited on the opening in the middle of the upper gate electrode 164 to fill the trench 122 . In some embodiments, the third oxide layer 180 is, for example, a silicon oxide layer with a thickness of about 3000 angstroms to 5000 angstroms to fill the trenches 122 .

Referring to FIG. 9, the aforementioned third oxide layer 180 and the spacer 172 are etched back to form an intermediate insulating portion 230, wherein the intermediate insulating portion 230 includes the intermediate oxide layer 182 formed by etching back the third oxide layer 180, It also includes the spacer 172 or the residual spacer 174 after the etch back, which is determined by the depth of the etch back, and does not deviate from the spirit and protection scope of the present invention.

In some embodiments, the intermediate insulating portion 230 , the gate oxide layer 150 and the first dielectric layer 132 cover the upper gate 164 .

Then, ion implantation is performed to perform ion implantation on the epitaxial layer 120 next to the gate structure 220, and further heating is performed to perform ion drive in. In some embodiments, a P-type ion implantation is performed with a trivalent element such as boron, and then heated to induce the trivalent element such as boron. Next, a source mask is used to define a source region 190 . In some embodiments, a source mask is used for ion implantation of the source region 190 and further heating for ion implantation, such as pentavalent arsenic, phosphorous, antimony, etc. The element is partially shielded with a source mask for N-type ion implantation, and heated for ion implantation.

Referring to FIG. 10, as shown in the figure, a second dielectric layer 200 is then formed on the gate oxide layer 150 and on the gate structure 220, and a contact mask is used for etching The second dielectric layer 200 and the gate oxide layer 150 are formed to form the required openings 156, and then a metal layer 210 is deposited on the second dielectric layer 200 and in the openings 156, and then a photomask and an etching process are used. to form the desired metal lines. In some embodiments, the second dielectric layer 200 includes boro-phospho-silicate glass (BPSG) as a dielectric layer with a thickness of about 6000 angstroms to 10000 angstroms. The metal layer 210 can be an aluminum metal layer with a thickness of about 3.0 μm to 5.0 μm, however, the invention is not limited thereto.

In some embodiments, the upper gate 164 of the aforementioned gate structure 220 is formed between the intermediate insulating portion 230 , the gate oxide layer 150 and the first dielectric layer 132 , and the intermediate insulating portion 230 may be located on the upper gate 164 The middle and upper, and lower gate electrodes 142 are encapsulated in the first dielectric layer 132 and the gate oxide layer 150 .

To sum up, the method for manufacturing a trench semiconductor device disclosed in the present invention can produce power MOSFETs, effectively reduce the size of the upper gate by the intermediate insulating portion, and precisely form the upper gate by using the spacer The gate electrode is formed, and the upper gate electrode is formed between the first dielectric layer, the intermediate insulating portion and the gate oxide layer, and the lower gate electrode is covered by the first dielectric layer and the gate oxide layer, thus effectively improving the Drain-source breakdown voltage (BVDSS) and reduce input capacitance (Ciss) and reverse transfer capacitance (Crss), increase output capacitance (Coss) , improve the gate capacitance characteristics, improve the response speed of the gate.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure The scope of protection shall be determined by the scope of the appended patent application.

110: Substrate 120: epitaxial layer 122: Groove 130: first oxide layer 132: first dielectric layer 140: first polysilicon layer 142: Lower gate 150: gate oxide layer 152: Part 1 154: Part Two 156: Opening 160: Second polysilicon layer 162: Recessed polysilicon layer 164: Upper gate 170: Second oxide layer 172: Spacer 174: Residual spacers 180: The third oxide layer 182: Intermediate oxide layer 190: source region 200: Second Dielectric Layer 210: Metal Layer 220: Gate structure 230: Intermediate insulation

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 to FIG. 10 are partial cross-sectional schematic diagrams illustrating the process steps of a trench semiconductor device according to an embodiment of the present invention.

110: Substrate

120: epitaxial layer

132: first dielectric layer

142: Lower gate

150: gate oxide layer

156: Opening

164: Upper gate

174: Residual spacers

182: Intermediate oxide layer

200: Second Dielectric Layer

210: Metal Layer

230: Intermediate insulation

Claims (7)

A method for manufacturing a trench type semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming a gate structure in the trench, wherein the gate electrode The structure includes an upper gate electrode, a lower gate electrode and a middle insulating part, and the middle insulating part is located between and above the upper gate electrode; a first oxide layer is deposited in the trench; a first oxide layer is deposited A polysilicon layer is on the first oxide layer and in the trench; the first oxide layer is etched back to below the upper surface of the first polysilicon layer to form a first dielectric layer; oxidation Surfaces of the epitaxial layer and the first polysilicon layer to form a gate oxide layer, and the lower gate electrode is covered by the gate oxide layer and the first dielectric layer; a second polysilicon is deposited silicon layer to fill the trench; etch back the second polysilicon layer to below the upper surface of the gate oxide layer; deposit a second oxide layer; blanket etching the second oxide layer , forming a spacer on the upper surface of the second polysilicon layer in the trench; and using the spacer as a mask, self-aligning and etching the second polysilicon layer to form the upper gate. The method for fabricating a trench semiconductor device as claimed in claim 1, wherein the thickness of the first oxide layer is about 2000 angstroms to 3000 angstroms, and the thickness of the first polysilicon layer is about 3000 angstroms to 8000 angstroms , and fill the trench. The method for fabricating a trench semiconductor device according to claim 2, further comprising: etching back the first polysilicon layer to a position about 0.7 micrometers to 1.2 micrometers below the upper surface of the first oxide layer. The method for fabricating a trench semiconductor device according to claim 3, further comprising: etching back the first oxide layer to a position about 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer to form the first dielectric layer. The method for fabricating a trench semiconductor device according to claim 4, further comprising: etching back the second polysilicon layer to a position about 1000 angstroms to 1500 angstroms below the upper surface of the gate oxide layer. The method for manufacturing a trench semiconductor device according to claim 5, further comprising: depositing a third oxide layer; etching back the third oxide layer and the spacer to form an intermediate insulating portion, And the middle insulating part, the gate oxide layer and the first dielectric layer cover the upper gate. The method for manufacturing a trench semiconductor device as claimed in claim 6, further comprising: performing ion implantation in the epitaxial layer and heating to perform ion drive in; using a source mask to define a source forming a second dielectric layer over the gate oxide layer; using a contact area mask to etch the second dielectric layer and the gate oxide layer to form openings; and depositing a metal layer on the second dielectric layer and in the openings.

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