TW583753B - Multiple bit cell flash memory and fabricating method thereof - Google Patents

Abstract

A multiple bit cell flash memory structure is provided. The multiple bit cell flash memory is consisted of a control gate, a inter-gate dielectric layer, a floating gate, a tunneling oxide layer, a source/drain region and channel region. The floating gate further includes an isolation region. The isolation region partitions the floating gate into a plurality of conductive block, which formed a conductive block array. The source region to drain region is row direction, and each row comprises two conductive blocks. When the multiple bit cell flash memory is at un-coding condition, the channel region below the same row conductive blocks has same threshold voltage and the channel region below the different row conductive blocks has different threshold voltage.

Description

583753 V. Description of the invention (l) 1 The dry jaw field belonging to the Ming Dynasty This invention relates to a kind of non: if,. _ Volatile non-Volatile

Memory), and in particular a manufacturing method. The storage, reading, and erasing of fast flash memory data in the non-volatile memory of the previous method and its memory system have the advantage that it can be performed multiple times and will not disappear. Therefore, a kind of memory element that has been widely used after power-off has become a typical flash memory widely used in personal computers and electronic devices in exchange for μ ^ 々Γ + Λ Shi Xi makes a floating gate (^ 〇ating Gate) and a control gate (c〇ntr〇i) The straight gate is located on the control gate and the base Ϊ = Ϊί and the control gate is on the character line ⑽rd Line) t. π '^ With the oxide layer (Tunneling 0xide) and the inter-dielectric layer (Inter Gate Dielpp + r'i ·., VIII VI Ά ^ W ^ ^ ctric) are located on the substrate and the floating gate 1 Between the electrodes, when this memory is processed, Γ0βΙΊ is generated by applying a positive voltage to the control gate, and applying a smaller thunder region to the drain region (or source region) and the substrate.孰 Electron Λ '* (or source floating interpole order. Λ is injected with the oxygen Λ layer and trapped in the polycrystalline stone floating closed electrode layer; Electricity is distributed throughout θτ, so this kind of memory cell can only store two data states of "1" and "0", and it can store two memory cells for a single memory cell unit. However, as the degree of accumulation of semiconductor elements increases Flash memory also 09945twf.ptd Page 5 583753 V. Description of the invention (2) The trend of multi-bit storage to a single memory cell is developed. The No. 6420m case proposes a single memory cell for American exclusive memory The manufacturing method of the body. This patent is not based on the rapid storage of H storage blocks to form a double bit = case! Idle; isolated into two independent increases, single-memory cell double bit storage is no longer required; Therefore, there is a need for a single-memory storage shell body. As early as 5 years ago, many people have stored flash memory. SUMMARY OF THE INVENTION In view of this, the present invention --- the purpose is to provide a 2-memory body and its manufacturing method. Multiple materials are stored in the single-memory cell, so the accumulation degree of the components can be increased. Another object of the present invention is to shake the 括 — 括 xi k J: system it soil π milling π 1 Memory and manufacturing method thereof Flashing __Seven, said a mother " brother's N ° memory of excessive erasure phenomenon, and connected to increase the reliability of the memory element. The present invention provides a multi-bit quick question 9 households ^ ^ H ^ The repulsive flash memory, this multi-bit flash memory, is charged by $ and placed on the substrate. $ Extremely numb: n heart brake is set between the control gate and the substrate. ≫ 、 7 ^ ^ ^ ^ ^ and 罝 7, pre-position the source region and the polar region in the substrate on both sides of the gate electrode, and set them at 詈 榀 π + Ω, + Μ ΛΛ β e 1 The channel region below the gate and located in the bottom of the source and drain regions nt and the isolation region provided in the floating gate are formed by the isolation region that separates the floating closed electrode into a plurality of The conductive block array is a conductive block array. The direction of the conductive block array from the source region to the drain region is a column direction, and each column includes two conductive regions including n (n is a positive integer). & n t ^ ^ mother ^ J ^ ^ ^ ^ 芏 double; guide also ^ block. In addition, when the multi-bit flash memory is not written, the channels under the same conductive block are in the same row.

583753 V. Description of the invention (3) In the channel area, the gate electrode is tunneled, the oxygen electrode is separated from the conductive area, and the single material is stored and separated. Therefore, the rising element area has the same starting voltage, and the channels under different conductive blocks have different channels. The starting voltage. In the multi-bit flash memory described above, a gate dielectric layer and a chemical layer are respectively provided between the control gate and the floating gate and the substrate. In the above structure, I, Chaban on the 0th I less ^ ^ y ^ ^, the isolation zone in the gate is set to make the gate into a multi-bit structure, and the blocks under different columns are below The channel regions have different starting voltages. Therefore, the amount of data of multiple bits can be stored in the: cell, and the degree of component resource accumulation can be improved. Moreover, since the isolation gate divides the floating gate into conductive blocks (that is, the bits of the memory cell are separated from each other), the so-called secondary electron injection problem can be avoided and reliability can be improved. The present invention provides a method for manufacturing a multi-bit flash memory. The method is to form a tunneling oxide layer and a conductor layer on a substrate in order, and then to form an isolation region in the conductor layer. The conductor layer is separated into a plurality of electrical blocks, and these conductive blocks form an array of conductive blocks. This: the direction of the electrical, block array from one bit line to another bit line is the square of the column = each The column includes two conductive blocks, and each row includes η (n is a positive conductive block. Then, a layer of inter-gate dielectric ^ is formed on the conductor layer. A floating gate is formed. A bit line is formed in the substrate on both sides of the t ^ ^ gate, and after the thunder of the floating gate = the gate is made, an initial voltage adjustment step is performed to make different columns " The channel areas below the block have different starting voltages.

09945twf.ptd V. Description of the invention (4) Material of the layer ΐΐ 二 η: The manufacturing method of the body, wherein the conductor method is to form a box on the conductor layer, and a conductive photoresist layer is formed in the conductor layer to form an isolation area, and then An oxygen ion is implanted in the area where the isolation zone is formed (or into the step to form an interval to allow oxygen ion (or nitrogen ion) to be formed), and a tempering isolation zone is performed. . /, A silicon oxide layer is formed by the reaction of silicon. In addition, the above-mentioned multi-bits are included on the bit lines to form a field oxide layer. /, The side wall of the pre-positioned gate is formed between the above-mentioned multi-bit flash memory and the earliest implanted in the conductor layer + " the present invention in the method il il mm Ions (or lice ions) to form an isolation zone. Because the layer is separated into a plurality of regions, and the conductive regions in different columns are recorded and i 5: has a different starting value voltage, it can make a "^ L 7 Xi Yuan structure, and can not increase the memory cell volume Under these conditions, increasing the number of bits of stored data can increase component integration. Moreover, since the isolation layer separates the conductor layer into a plurality of independent regions (that is, each bit of the memory cell is separated from each other), the problem of so-called secondary electron injection can also be avoided. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, hereinafter, a preferred embodiment is described in detail with reference to the accompanying drawings, which are described in detail as follows: Embodiments Please refer to the attached drawings , Which is used to explain the multi-bit m 09945twf.ptd of the present invention, page 8 5837753 5. Description of the invention (5) The structure of a flash memory. Figure 丨 A (top view) and Figure 丨 B (cross-sectional view) illustrate the structure of a multi-bit flash memory according to an embodiment of the present invention. FIG. 2 is a structural top view of a multi-bit flash memory according to another embodiment of the present invention. In the second figure, the components are the same as those in the first figure and the first figure, and the description is omitted. Referring to FIG. 1 and FIG. 1A and FIG. 丨 B, the flash memory of the present invention is composed of a substrate 100, an idle structure 1 〇2, a source area 丨 〇4 and a drain area 丨 06, a channel area 107. The gate structure 102 is located on the substrate 100. The source region 104 and the drain region 106 are respectively located in a substrate 100 on both sides of the gate structure 102. The channel region 107 is disposed in the substrate 100 below the gate structure 102 and between the source region 104 and the drain region 106. The gate structure 102 is composed of a tunneling oxide layer 108, a floating gate 110, an inter-gate dielectric layer 112, and a control gate 114. The control gate 114 is provided on the substrate 100. The floating gate 110 is provided between the control gate 114 and the substrate. The μ-electric layer 11 2 is provided between the control gate 1 and the floating gate 110. The inter-gate dielectric layer 112 is, for example, oxygen cut. A layer, an oxide of arsenic / nitride is placed between the gate 110 and the substrate 100. An area 116 is provided in the floating gate electrode 10, and this isolation area Π6 separates the floating gate electrode 11 into a plurality of conductive blocks to form a multi-bit structure. These conductive blocks are arranged in a direction from a pole region 104 to a drain region 106, which is a column. 廿 丄 In this power block array, each column includes two conductors. Here are the conductive blocks. And ... multi-bit flashing quickly: = ::: Then in the state enclosed by J, below the conductive block in the same row: _ has the same start in the unwritten data channel area 09945twf.ptd Page 9 5835753 V. Invention Note (6) Voltage, the channel areas under the conductive blocks in different columns have different starting voltages. In this embodiment, an example of dividing (2 × 2 array) into four conductive blocks (110a, 110b, 110c, 110d) is described. Therefore, in the state where no data is written, the conductive block 1 10a in the first column has the same starting voltage as the channel region 107a below the conductive block 1110a. The conductive block 110c in the second column has the same starting voltage as the channel region ion below the conductive block iiod. The conductive block 110 & in the first column and the channel region 107a below the conductive block 110b are different from the conductive block 110 (3 and the conductive block 110 (1) in the second column have a difference Start voltage.

In the above structure, the isolation region 116 in the floating gate 110 separates the floating gate 110 into four conductive blocks (110a, nob, 110c, nod) to form a four-bit structure, In addition, the channel area 107a under the conductive block 丨 丨 a and the conductive block 丨 10b has different starting voltages from the conductive block ii〇c and the channel area 107b under the conductive block nod. Therefore, the amount of data of four bits can be stored in a single memory cell, and the degree of component accumulation can be improved. Moreover, since the isolation region 116 separates the floating gate electrode 11 into four independent conductive blocks (that is, the four bits of the memory cell are separated from each other), the problem of so-called secondary electron injection can also be avoided. , Which can improve component reliability.

In the above structure, 'the floating gate electrode is separated into four conductive blocks 11 0 a to 11 0 d as an example for illustration. Of course, the floating gate electrode 11 can also be separated into more than four conductive blocks (for example, the six conductive blocks 11 0a ~ 11 Of shown in Figure 2), and then the conductive blocks in different columns can be placed below. The channel regions have different starting voltages, and can form a multi-bit structure. The above describes the structure of the multi-bit flash memory of the present invention, and then,

583753 V. Description of the invention (7) The method for manufacturing the multi-bit flash memory of the present invention. 3A to 3F are top views of the manufacturing process of the flash memory of the present invention. Figures 4A to 4F are cross-sectional views showing the manufacturing processes along lines B-B 'in Figures 3A to 3F, respectively. First, referring to FIGS. 3A and 4A, a substrate 200 is provided. The substrate 200 is, for example, a silicon substrate. Then, an oxide layer 2 02 'is formed on the substrate 200 as a tunneling oxide layer. The method for forming the oxide layer 02 is, for example, a thermal oxidation method. Next, a conductive layer 204 is formed on the oxide layer 202. The material of the conductive layer 204 is, for example, polycrystalline germanium silicide. The method for forming the conductor layer 204 is, for example, a method using a chemical vapor deposition method using silane, germane, and hydrogen as reaction gases. Next, referring to FIGS. 3B and 4B, a patterned photoresist layer 206 is formed on the conductor layer 204. The patterned photoresist layer 206 exposes a region of the conductive layer 204 that is intended to form an isolation region. Then, an ion implantation step 20 8 is performed, and the patterned photoresist layer 206 is used as a mask to implant a dopant such as an oxygen ion into the conductor layer 208 exposed by the patterned photoresist layer 206. An oxygen ion doped region 210 is formed in the conductive layer 204. The implantation dose of oxygen ions is about i10i8 atoms / cm2 to about 1018 atoms / cm2, and the implantation energy is about 20 仟 electron volts to about 80 仟 electron volts. Of course, the dopant of the implanted conductor layer 204 is not limited to oxygen ions, as long as it can react with silicon to form an insulating material, the invention can be applied. Therefore, the dopant of the implanted conductor layer 204 may also be a nitrogen ion. ^ 4 ^

583753 5. Description of the invention (8) Next, please refer to FIG. 3C and FIG. 4C. After removing the patterned photoresist layer 206, a tempering process is performed to make the oxygen ions (or nitrogen ions) and the conductor layer 2 The silicon in 04 reacts to silicon oxide (silicon nitride) to form an isolation region 2 丨 2. The temperature of this tempering process is, for example, about 950 t: to about 1150 t. The isolation region 212 separates the conductive layer 204 into a plurality of isolated conductive blocks. In the apricot embodiment, the isolation region 212 is used to explain the conductive layer of a single memory cell and two conductive blocks. The M is divided into four. Then, an inter-gate dielectric layer 214 is formed on the substrate 200. This = layer = is, for example, an oxygen-cutting layer, an oxygen-cutting / nitride stone layer. The thickness of the inter-gate dielectric layer 214 is, for example, a method for forming the inter-gate dielectric layer 214. For example, the formation method is S-picture: 3D, 4D, on the inter-gate dielectric 214 D6 formation of floating i open pole. The patterned photoresist layer 216 covers a predetermined area. Then, the patterned photoresist layer 21 / is used as a road cover to determine the area of the bit line. 214, conductor layer 204 "! Mountain 16 is a mask, and a part of the inter-gate dielectric layer is removed for ion implantation to form a region where a bit line is formed. Then, the patterned photoresist layer 216 = Λ patterned photoresist layer 216 is a veil. In 15 substrates 200, dopants are implanted in the substrates 200 on both sides forming a f-burst, and in the area of ions and arsenic ions 22θ〇 (bit lines). It is 5 arsenic atoms per square centimeter = the dosage is set to 2 x 1015 atoms per square centimeter to 4 X 10. Next, please implant energy of about 50 仟 electron volts. After 21 6, perform a "E system" Figure and Figure 4E, remove the patterned photoresist layer ... I pass to form a field on the surface of the doped region 220 (bit line) ϋϋ 09945twf.ptd Page 12 583753 V. Description of the invention (9) ----- -The oxide layer 222 is oxidized, and the dopant of the doped region 22 is activated. The field oxide layer is used to isolate the doped region 22 (bit lines) from the control diode lines formed later. When the% oxide layer 22 is formed, it will also be on the side wall of the conductor layer 204. Form a gap wall 224. The partition wall 224 can isolate the control gates (word lines) formed by the conductive layer 204 in a subsequent period. /, ^ Then, a conductive layer 226 is formed on the substrate 200, and the material of the conductive layer 226 is, for example, doped polycrystalline silicon. The method for forming the conductive layer 226 is, for example, implanting dopants in situ, and using chemical vapor deposition to form Of it. Next, please refer to Figures 3F and 4F. A mask (not shown) is used to pattern the body layer 226 to define a control gate 228 (word line). While defining the conductor layer 2 2 6, continue to define the inter-gate dielectric layer 214, the conductor layer 204 and the dielectric layer 202 with the same mask to form a gate structure. The conductive layer 204 serves as the floating gate 230. That is, the gate structure of the flash memory of the present invention is composed of a stacked structure of the control gate 2 2, the inter-gate dielectric layer 2 4, the floating gate 230 and the oxide layer 202 shown in the figure. In this embodiment, the 'floating gate 230 of each memory cell includes at least four separate conductive blocks 204a, 204b, 204c, and 204d separated by the isolation region 212, of which the conductive blocks 204a, 204b , 204c, and 204d form a 2x2 array. Then, an initial voltage adjustment process is performed. First, a patterned photoresist layer 232 is formed on the substrate 2000, and the patterned photoresist layer 232 at least exposes the control gates 228 above the conductive blocks 204c and 204d. Then, using the patterned photoresist layer 232 as a mask, an ion implantation step is performed, and a dopant is implanted in the channel region 234b under the conductive block 204c and 204d to adjust the conductive block 204B under 204d. The starting voltage of the channel region 234b. Then, conductive

09945twf.ptd Page 13 583753 V. Description of the invention (10) The channel region 234b under the blocks 204c and 204d and the channel region 234a under the conductive blocks 204a and 204b have different starting voltages. Therefore, one memory cell can store four bits of data. The subsequent process of completing the flash memory is well known to those skilled in the art, and will not be repeated here. In the above embodiment, the present invention forms the isolation region 212 by implanting oxygen ions into the conductor layer 204. The isolation region 212 separates the conductive layer 204 into a plurality of conductive regions to form a multi-bit structure. Therefore, without increasing the volume of the memory cell, the number of bits of stored data can be increased and the element integration can be improved. Moreover, since the isolation region 212 separates the conductor layer 204 into four independent regions (that is, the four bits of the 'memory cell are separated from each other), the problem of so-called secondary electron injection can also be avoided. Moreover, the dopant of the implanted conductor layer 204 is not limited to oxygen ions, and anyone who can react with silicon to form an insulating material can apply the present invention. Therefore, the dopant of the implanted conductor layer 204 may be nitrogen ions or other ions. “Ί 二”: The Λ separation region 212 can also separate the conductor layer 204 into more than four (such as eight or eight), and then make the channel U under different rows of conductive blocks different starting voltages 1 can Forming a multi-bit junction Although the present invention has been disclosed as above with a preferred embodiment, and is it limited? The present invention is not suitable for anyone skilled in the art, and can be changed and retouched without departing from the spirit of the present invention. Therefore, the protection scope of this issue shall be subject to the definition in the appended patent application scope. $ ”09945twf.ptd Page 14 583753 Brief description of the diagram 204, 226: Conductor layer 206, 216, 232: Patterned photoresist layer 208, 218: ion implantation steps 210, 220: doped region 2 2 2: field oxide layer 2 2 4: spacer wall 1 · 09945twf.ptd page 16

Claims (1)

583753 6. Scope of patent application1. A multi-bit flash memory, the multi-bit flash memory includes: a substrate; a control gate, the control gate is disposed on the substrate; a floating gate The floating gate is disposed between the control gate and the substrate; an inter-gate dielectric layer is disposed between the control gate and the floating gate; a tunnel oxidation Layer, the tunneling oxide layer is disposed between the floating gate and the substrate; a source region and a drain region, the source region and the drain region are disposed on both sides of the floating gate In the substrate; an isolation region is provided in the floating gate, and the isolation region separates the floating gate into a plurality of conductive blocks to form a conductive block array, the conductive block array The direction from the source region to the drain region is the direction of a column. 'Each column includes two conductive blocks, and each row includes n (n is a positive integer) conductive blocks; and a channel region, the channel The base region is disposed below the floating gate and between the source region and the drain region. In the state where the multi-bit flash memory is not written, the channel areas under the conductive blocks in the same row have the same starting voltage, and the channels under the conductive blocks in different rows have the same starting voltage. Zones have different starting voltages. 2. The multi-bit flash memory as described in item 1 of the patent application scope, wherein the inter-gate dielectric layer includes a silicon oxide layer. 〇9945twf.ptd Page 17 583753 6. Scope of patent application-___ 3. As described in the scope of patent application item 1, wherein the inter-gate dielectric layer includes silicon oxide / Xiongyuan flash memory, 4. As described in item 1 of the scope of the patent application, the second interlayer dielectric layer includes silicon oxide / 70-bit flash memory. 5. Emulsified silicon layer escaped as described in the first scope of the patent application. Wherein the material of the floating gate includes polycrystalline H multi-bit flash memory, ^ IC * 〇 6 · As described in item 1 of the scope of patent application-wherein the material of the isolation region includes silicon oxide. Xi Li 70 flash memory, multi-bit flash memory 7 · As described in item 1 of the patent application range, wherein the material of the isolation area includes nitride nitride. The method includes the following steps of manufacturing a multi-bit flash memory: providing a substrate; forming a tunneling oxide layer on the substrate; forming a conductor layer on the tunneling oxide layer; An isolation region is formed in the conductor layer, and the isolation region separates the conductor layer into a plurality of conductive blocks. The conductive blocks form an array of conductive blocks. The conductive block array runs from one bit line to another. The direction of the element line is the direction of a column. Each column includes two conductive blocks, and each row includes n conductive blocks (η is a positive integer). A dielectric gate layer is formed on the conductor layer. Patterning The inter-gate dielectric layer and the conductor layer to form a floating gate; forming the bit lines in the substrate on both sides of the floating gate; forming a control gate on the floating gate; and 09945twf.ptd Page 18 6. The manufacturing methods of the conductive blocks listed below the scope of the patent application, wherein the method of manufacturing the conductor to form I in the conductor includes: Wu Chengercheng—patterned photoresist layer, the The patterned photoresist layer bursts in advance to form the region of the isolation region; ί an ion implantation step, implanting a dopant in the region scheduled to form the isolation region; and performing a tempering process to make the dopant and the The silicon in the conductive layer reacts to form the isolation region. lj · The method for manufacturing a multi-bit flash memory as described in the scope of the patent application, wherein the ion implantation step implants the dopant of the conductor layer including oxygen ions. 1 2 · The method for manufacturing a multi-bit flash memory as described in item 丨 丨 of the patent application range, wherein the implantation dose of oxygen ions includes 1 X 1 0 18 atoms / cm 2 to 2 × 10 18 atoms / square Around cm. 1 3. The method for manufacturing a multi-bit flash memory as described in item 11 of the scope of patent application, wherein the implantation energy of oxygen ions is about 20 仟 electron volts to about 80 仟 electron volts. 14. The method for manufacturing a multi-bit flash memory as described in item 丨 丨 of the patent application scope, wherein the dopant implanted into the conductor layer by the ion implantation step includes nitrogen ions. 09945twf.ptd Page 19 583753 VI. Scope of patent application 15 · The method for manufacturing multi-bit flash memory as described in item 10 of the scope of patent application, wherein the temperature of the tempering process includes 950 ° C to 1150 ° C or so. 16 · The method for manufacturing a multi-bit flash memory as described in item 8 of the scope of the patent application, wherein the steps of forming the bit lines in the substrate on the rain side of the floating gate and the floating The step of forming the control gate on the placing gate further includes forming an emulsifying layer on the 5H bit line and forming a gap wall on the side wall of the floating gate. 17. A method for manufacturing a multi-bit flash memory, the method includes the following steps: providing a substrate; forming a tunneling oxide layer on the substrate; forming a polycrystalline germanium silicide layer on the tunneling oxide layer Forming a patterned photoresist layer on the polycrystalline germanium silicide layer, the patterned photoresist layer exposing the surface of the polycrystalline germanium silicide layer that is intended to form an isolation region, and performing an ion implantation step to form the isolation region at a predetermined interval; A dopant is implanted in the polysilicon chemistry layer; and a tempering process is performed to form the isolation zone, which isolates several conductive blocks, and forms a conductor from a bit line to The other bit line includes two conductive blocks; each row is a block; the dopant and anti-segment regions of the polycrystalline silicon germanium layer separate the polycrystalline silicon germanium layer into a complex electric block array. The direction of the conductive block array is the direction of a column. Each column includes η (11 is a positive integer) conductive regions formed on the polycrystalline siliconization layer—a gate-to-gate dielectric layer. 09945twf.ptd Page 20 583753 In order to form a floating six, the scope of the patent application patterned the inter-gate dielectric layer and the polycrystalline silicon germanium layer gate; forming the bits and lines in the substrate on both sides of the floating gate. Forming a control gate on the floating gate; and performing an initial voltage adjustment step, so that the channel areas under the walls of the φ wide two guard% area in different columns have different initial voltages. 18 · The method for manufacturing a multi-bit flash memory as described in item 17 of the scope of the patent application, wherein the ion implantation step implants the conductor layer with a "substance including oxygen ion." 19 The method for manufacturing a multi-bit flash memory as described in item 17 of the patent scope, wherein the dopant implanted in the conductor layer by the ion implantation step includes nitrogen ions. The method for manufacturing a multi-bit flash memory, wherein the step of forming the bit lines in the substrate on both sides of the floating gate and the step of forming the control gate on the floating gate The method further includes forming a field oxide layer on the bit line and forming a gap wall on the sidewall of the floating gate. 09945twf.ptd Page 21