TW574755B - Nitride read only memory and the manufacturing method thereof - Google Patents

Abstract

A nitride read only memory is consisted of: a control gate is set on the substrate, a source region and a drain region is set in the substrate set at the two side of the control gate, an electron trapping layer is set between control gate and substrate, and a channel region is set below the electron trapping layer between the source region and the drain region. Wherein an isolated region is set in the electron trapping layer for separating the electron trapping layer into source side electron trapping block and drain side electron trapping block to form a binary bit structure.

Description

574755 V. Description of the invention (1) The method of the invention 4 ^ The present invention relates to a non-volatile memory (Non-v〇iati u), and in particular to a method for making nitride nitride Electrxcally Erasable Programmable Read Only Memory (EEPROM) in previously non-volatile memory has data that can be stored, read, erased and stored multiple times The advantage that it will not disappear even after the power is cut off. It has become a kind of memory element silicon widely used in personal computers and electronic devices. 电 Ϊ Polycrystalline garments that can be electrically erased and programmable read-only memory system. Floating Gate and control gate (Ion of C0ntr〇1) ^ ^ ^ memory body is programmed (Pr0gram), the floating gate is injected, said: evenly distributed throughout the polycrystalline silicon floating In the gate layer, however, when the defect under the plutonium layer has defects in the oxide layer, the leakage current of the component is easily combined, which affects the reliability of the component. The current = t is I, which can be electrically erased and programmed. Leakage of read-only memory components: a kind known to Jing Erxiang before Jin Er The method is to use a charge trapping layer instead of a kind of nitridation: ί: The material of this charge trapping layer is, for example, nitride stone. This person 4: He trapping layer usually has a layer of silicon oxide above and below, forming a ^ tacked) ^ ί ^ 〇βΝ〇) ^ ^ ^ ^ is called _π 甲 才. , ", Mouth structure," EEPR0M pass with this pile-type gate structure ", lice silicon read-only memory (NROM). When a voltage is applied to the control of this component

V. Description of the invention (2) When the gate and source / drain regions are marked with " " ^-When the region is programmed, the channel has the property of capturing electrons, and the load is trapped in the layer. Since ^ is not evenly distributed in the whole g of the main charge trapping layer ^ trapped in the local layer into the upper layer, but is concentrated in the local π region, so the electric charge / injection charge trapping layer has a small '= leakage Said electricity ::: 'Like = easy: sensitive products of defects in the oxide layer: car: when stacked, you can make the stack: ;;] the other advantage of memory is in approaching-= two: pole / drain The polar region has a relatively high V electron and can also store a relatively high voltage in the silicon nitride layer of the reactor and the polar region, while the source / drain on the other side of the transistor is an electron. ^ Nitrogen in the near source / drain region; the current applied to the pole / drain region is controlled by the / culture change gate and its sources on both sides in two groups of electrons, and the single group of electricity is nitrided earlier. There can be only read-only memory in the silicon layer, or there can be no electrons. Therefore, the silicon nitride type single memory cell has two states (four states are written into the memory cell as a whole. ^ Ts / ce 11) Stored non-volatile memory However, the conventional two- & injected electrons are trapped in the layer 7 nitride nitride read-only memory curve when programming. However, 7 is the same as j The electrons will form an electron component according to the injected energy to produce the so-called electron two, Ji Yi cell's two bits will affect each other (Effect), and make electricity ': main, input effect (Electron Secondary when erasing' to electricity The distribution curves are broadened and connected together. Therefore, the distribution curve formed by the injection of thermal holes into the layer will be 9947t.wf.ptd Page 6 574755 V. Description of the invention (3) —— = sub-knife cloth curve coincides in Together, the problems of inability to completely erase and the longer erasing time are required. When erasing is performed using the thermal hole injection effect, the electric system is caused by the f-side, the drain side (or the source side). ) The charge is injected into the layer, and the number of holes injected into the layer is difficult to control. Therefore, during the erasing process, possible holes are injected into the charge into the layer, causing the so-called 1 degree erasure of the body. Over Erase) or the situation that cannot be erased. When this situation is over erased or cannot be erased, the reliability of the memory element (RellabUity) is reduced. The invention will be made in view of this. One of the objects of the present invention is to Provide a note The memory body and the manufacturing method thereof can avoid the tube, the phenomenon of "reading and removing siliceous silicon, and improve the availability of memory elements. Coughing the memory excessively, another object of the present invention is to provide-its manufacturing method Can be in a single memory cell; silicon read-only memory and can increase the degree of accumulation of components. Zixi bit data, so the present invention provides a silicon nitride read-only memory is provided on the substrate Control gate; the source region and the drain region of the base of the silicon nitride read-only substrate, which are set at ° and placed on the charge trapping layer on both sides of the control gate and under the charge trapping layer The structure of the channel region in the base between the two points and the source region and the drain region, and this isolation region separates the charge trapping layer from the charge trapping block in the drain region, and becomes The charge trapped in the polar region is in the above structure. The isolation zone in the layer causes the charge to trap the layer (page 7) 74755 5. Description of the invention (4) The problem of the two insertions of the charge trapping layer into the two layers of the charge trapping zone The charge trapped block array formed by the power source between the polar region and the polar region and between the polar regions is trapped into the block from the two charges in the source. Then, the same column is pressed and different columns are started. Between these layers, an electrically oxidized layer is formed. In the above separation into multiple t charge traps

9947twf.ptd Charge trapping block (source-side charge trapping block and non-polar-side block) to form a two-bit structure, and because the isolation zone will be separated into two independent charge trapping blocks (ie, memory cells Separate from each other), so the so-called secondary electron injection can be avoided, and component reliability can be improved. Provided is a nitride-only read-only memory. This nitride-only read-only memory is a control gate disposed on a substrate, a gate disposed on a control gate and a base charge trapping layer, and a pole disposed on a substrate on both sides of a charge trapping layer. A region, a channel region disposed under the charge trapping layer, and a channel region disposed in the substrate between the source region and the spacer disposed in the charge trapping layer. Among them, the isolation region separates the charge trapping layer into a plurality of electric charges to form a charge trapping block array. The direction from the charge trapping block to the drain region is a column direction, and each column includes the block. Each row includes Includes η (η is a positive integer) charge traps and the channel area below the block where the charge of the nitride read-only memory is not written into the channel is the channel with the same initial charge trapped under the block In the silicon nitride read-only memory with different initiation regions, a gate dielectric layer is formed between the control gate and the charge ρ charge trapping layer and the substrate. The isolation region in the charge trapping layer makes the charge The charge is trapped in the block to form a multi-bit structure, and the channel area below the layer block has different starting and different column bonds. Therefore, 574755 V. Description of the invention (5) It can be separated and separated from each other when a single component data store is trapped, but the method of the present invention can be sequentially divided into blocks of one bit line in the complex electric street trapped area after the charge is separated in sequence. Each time, the same layer of charges are formed on the charge electrode dielectric layer and the charge input layer, and the pattern of the method region of the above-mentioned material layer of the trapped layer is formed to isolate the oxygen ions from the memory cells. The amount of data in bits can improve inventory and component accumulation. Moreover, because the isolation region traps multiple charges into the block (that is, each bit of the memory cell), it can also avoid the problem of so-called secondary electron injection and improve the reliability of the device. Provide a silicon nitride read-only memory In the manufacturing method, a square silicon oxide layer and a charge trapping layer trap layer are formed on the substrate to form an isolation region. This isolation region causes charges to trap layers of charge trapping blocks, and these charge trapping blocks form an array. The charge trapping block array runs from a bit line to the other direction as a column. Each column includes two charge trapping rows and includes η (η is a positive integer) charge trapping blocks. Then, a trap gate is formed on the trapped layer. A dielectric layer, and pattern the gate charge trapping layer to expose the area where the bit line is to be formed. A bit line is formed in the substrate on both sides of the trap layer, and an initial voltage adjustment is performed after the charge trap controls the gate Steps, so that the channel region under the block has different starting voltages. In the manufacturing method of the silicon nitride read-only memory, the charge quality is silicon nitride. And, Formation of isolation in the charge trapping layer Prior to forming a photoresist layer on the charge trapping layer that exposes a predetermined isolation region, an ion implantation step is performed to implant an oxygen ion into the pre-region and perform a tempering process. In the above-mentioned manufacturing method of the silicon nitride read-only memory, the isolation region is formed by the reaction of the charge sinking layer.

9947twf.ptd Page 9 574755 V. Description of the invention (6) Included in the bit line formation field oxide layer. In the above-mentioned manufacturing method of the silicon nitride read-only memory, the isolation region is formed by implanting milk ions in the charge trapping layer. It is recognized that the ^ region separates the% charge trapping layer into a plurality of regions ▲, and the channel region below the isolated block has different initial voltages, because the charge is trapped in a memory cell with a multi-bit junction #, and can Without increasing the ::: to make-increase the storage volume from # — + ° to the hidden cell volume and 'separate the charge trapping layer into the layer due to the isolation zone. (Second, the bits of the memory cell are separated from each other). Therefore, the problem of electron injection occurs in the area of.乂 In order to avoid the above and other objects, features, and comprehensibility of the present invention, a preferred embodiment is given below, and can be explained in more detail as follows: 1. Please refer to the drawings for detailed implementation: please refer to the attached Figure < is a structure for illustration. Figure 1a (top view) and Figure a (aerial surface η depicts the silicon nitride surface of an embodiment of the present invention), and Figure 2B shows the author ^ ;; Xi, π structure . Figure 2A Top view of the structure of the body. 『AH :: 9 Example of the nitride nitride eve read-only memory is the same as the following: Yu; Γ ;; brother figure, component and figure ia, 4 ▲ Ding Xiang" j ", and its description is omitted The pictures are shown in Figures 1 A and 1 B. The beam smoke is composed of the beauty base 1 nn 卩 u α 4 The chaotic silicon read-only memory of the present invention in the area of 07th Hibiscus, "忐 1 〇2, the source region 104, the drain region 106, and the pass gate structure 102 are located on the substrate 100. The source region 104 ″ and the pole 06 are respectively located in the substrates on both sides of the gate structure 102. Through 574755

The source region 104 and the drain region 106. V. Description of the invention (7) The forcing region 107 is disposed in the substrate 100 below the gate structure 102. The interlayer structure 102 is formed by interposing the oxide layer 108 interlayer dielectric layer m and the control interlayer 100. The gate dielectric layer 112 is a private gate 114 and the substrate 厣 1! Ημβ layer "is placed between the control gate 114 and the charge trap". The gate dielectric layer 112 is, for example, a stone oxide layer. Floor. The penetrating team 4 & layer 1 0 8 is arranged on the electric porphyrin A u η to make the production of η Λ Λ tooth steep emulsification, including immersion between 110 and 100. There is a p miscellaneous n in the layer 110, where ^^ 1 is long private, and Λ v ^ ^ y ^ away from £ 11 6 'This isolation zone 11 6 makes the electric charge fall into the 屛 # 刀 夕 固 Electric charge into the block A multi-bit structure is formed. In these two arrays, the direction from the source region 104 to the drain region 106 is a column direction. # 中 ， In this charge trapped in the block array

The column includes two charges that accompany γ, and the base y- 0,1 Λη I ^ ^ into the block mother. One includes several charge trapping areas. In addition, the unscrambled silicon read-only memory has the same starting voltage when the uncharged charges in the same column are trapped in the lower part, S, Ku Guangyue > the state of sadness and the lower part of the entry block. ^ The queued electricity has a different starting zone, and the channel area below the block has a different starting zone. In the example, it is divided into (2 p trains) four charge trapping regions: (110a, 110b, 110c, 110d). Therefore, in the state of the data, the thunder order Α π 仏 彳, π in the first column, you are not connected. 1 nu nr The channel region 10 has the same starting voltage. The electricity in the second column is trapped in block 1 10 C and the channel region 107b below the charge trapping block 丨 丨 d has the same starting voltage. In the first column The charge trapping block 11〇 ^ and the charge trapping block 丨 丨 0b under the channel area〗 〇7a and the second column of the charge trapping block 110c and the charge trapping block 11〇 (the channel area below the 1 With 574755

V. Description of the invention (8) Different starting voltages. In the above structure, the charge level λ & 4 λ & trapped layer 110 is separated into four electrically isolated p-layers in the isolation region 116 to make the charge ㈣) to form a four-bit structure. He = into the block (110a, 110b, n〇C, the channel trapped in the block nob τ side, the electricity nine traps-access to the block 11〇a and the charge charge trapped below the block 11〇d: = trapped in the block n ° c and electricity, district 丨 〇7b Have different starting voltages. ^ This can store four bits of data in the early-memory cell *, and

Increase component accumulation. Moreover, since the isolation region 116 separates the charge trapping layer 11 into four independent charge trapping blocks (that is, the four bits of the memory cell are separated from each other), it can also avoid the so-called secondary electron injection. This can increase component reliability. In the above-mentioned structure, the description is made by taking the charge trap layer 丨 丨 into four charge trap blocks 110a ~ 110d as an example. Of course, the charge trapping layer 1-10 can also be separated into two charge trapping blocks (for example, separated into two charge trapping blocks l10a and 11b shown in Figure 2A) or four or more charge trapping blocks. (For example, the six charge trapped blocks 110a ~ 1 1 Of shown in FIG. 2B are separated), and then the channel regions under different columns of charge trapped blocks have different initial value voltages, which can form multiple Bit structure.

The above describes the structure of the silicon nitride read-only memory of the present invention, and then describes the method of manufacturing the silicon nitride read-only memory of the present invention. 3A to 3e are not top views of the manufacturing process of the flash memory of the present invention. Figures 4 to 4G are cross-sectional views showing the manufacturing process along lines B-B in Figures 3A to 3G. First, please refer to Figures 3A and 4A, and provide a substrate 2 0 0, this

9947t.wf.ptd Page 12 574755 V. Description of the invention (9) The substrate 2 0 0 is, for example, a silicon substrate. Then, put it on foot 2 of the base for penetrating the oxide layer. This oxide layer: If it is a thermal oxidation method. Example of the method for forming the confusion Next, a material of the charge trapping layer 204 is formed on the oxide layer 202, and the material of the charge trapping layer 204 is, for example, nitride nitride. The charge trapping layer 204 is formed by, for example, a chemical vapor deposition method. ^ Next, referring to FIGS. 3B and 4B, a patterned photoresist layer 2 0 6 is formed at the charge trap #. An area of the patterned photoresist layer 206 in the charge trapping layer 204 is intended to form an isolation region. Then, an ion implantation step 208 is performed, using the patterned photoresistive sound 206 as a mask, and the charge trapping layer 20 exposed in the patterned photoresistive layer 20 6 is charged with oxygen ions, and the charge trapping layer An oxygen ion doped region 21 is formed in 204. The implantation dose of oxygen ions is 10 P atoms / cm 2 to 2. The implantation energy is about 18 atomic centimeters per square centimeter, and the implantation energy is about 20 to about 80 volts. Next, please refer to FIG. 3C and FIG. 4C. After removing the patterned photoresist layer 206, a tempering process is performed to react the oxygen ions with the silicon in the charge trapping layer 204 to form silicon oxide. Isolated area 212. The temperature production of this tempering process is, for example, 95 (TC to 1150t; about. Among them, the 'isolated region & separates the charge trapping layer 204 into a plurality of isolated charge trapping blocks. In this embodiment, the isolation region 2 is used. 1 2 Make a single 'a f? Reto μ t charge trapped in the block for explanation ... The trap layer 204 is isolated into four. Then, please refer to the 3D and 4D drawings'. Then, it is formed on the substrate 2000. -Layer gate dielectric layer 214. This gate dielectric layer 114 is, for example, a stone oxide

574755

Floor. The thickness of the gate dielectric layer 214 is, for example, approximately 1500 Å to 1500 Å, with a band of polar dielectric sound 2 1 4 to account for about 1500 Å. The example here is chemical vapor deposition. Then, a patterned photoresist layer 216 is formed on the light :: 2 \ 3. The patterned first-resistance layer 21 6 blasts out a region where a bit line is to be formed. The outer 6 is connected to Λ '/ see Figure 3E and ㈣. Then, using a patterned photoresist: 216 ♦ as a mask, remove part of the gate dielectric layer 214 and the charge trapping layer 204 to form a bit line. Area. Qian, perform an ion implantation = Yu Er uses the patterned photoresist layer 216 as a mask, implants a dopant in the substrate 200 on both sides exposed by the patterned photoresist layer 2Η, and forms a medium in the substrate 200. ^ Miscellaneous area 220 (bit line). | The dopant to be added is, for example, Shishen ion. Shishen :: Implantation dose is about 2-5 atoms / cm 2 to 4.15 atoms / square or about 7 knives. 9 1 Next, referring to FIG. 3F and FIG. 4F, after removing the patterned photoresist layer, a thermal process is performed to form a field = chemical layer 222 on the surface of the doped region 22 (bit line). The dopant of the doped region 22 is activated. The field oxide layer 22 is used to isolate the doped region 22 (bit line) from subsequent control (word line). Then, a conductive layer 224 is formed on the substrate 200, and the material of the conductive layer 224 is, for example, doped polycrystalline silicon. The method for forming the conductive layer 224 is, for example, a field implantation method and a chemical vapor deposition method. * Next ': Refer to FIGS. 3G and 4G. A mask (not shown) is used to pattern the body layer 2 2 4 to define the control gate 2 2 6 (word line). While defining the conductor layer 2 2 4, continue to define the gate dielectric layer 214, the charge trapping layer 204 and the dielectric layer 202 with the same mask to form a gate structure. : 574755

V. Explanation of the invention (11) I7 The gate structure of the memory of the present invention is the control gate 2 28, the gate dielectric layer 214, the charge trapping layer 2 04, and the oxide layer 2 0 2 Stacked structure. In this embodiment, the charge trapping layer 204 of each memory cell includes at least four separate charge trapping blocks 204a, 20 4b, 204c, and 204d separated by the isolation region 2 12, where the charge traps Blocks 204a, 204b, 20 4c, and 20 4d are tied into a 2 array. Then, an initial voltage adjustment process is performed. First, a patterned photoresist layer 228 is formed on the substrate 2000. The patterned photoresist layer 228 at least exposes the control gate electrode 22 6 above the blocks 20 4c and 2 04d. Then, the patterned photoresist layer 22 8 is used as a mask to perform an ion implantation step, and a dopant is implanted in the channel region 23Ob under the charge trapping blocks 204c and 204d to adjust the charge trapping blocks 204c and 204d. The starting voltage of the channel region 230b below: Therefore, the channel region 230b below the charge trapping blocks 20 4c, 204d and the channel region 230a below the charge trapping blocks 20 4a, 204b have different starting voltages. Therefore, a memory cell can be used to store four bits of data. The subsequent process of completing the silicon nitride read-only memory is well known to those skilled in the art, and will not be repeated here.

In the above embodiment, the present invention forms the isolation region 212 by implanting oxygen ions in the charge trapping layer 204. This isolation region 212 separates the charge trapping layer 204 into a plurality of charge trapping blocks to form a multi-bit structure. Therefore, without increasing the volume of the memory cell, #the number of bits of stored data can be increased and the component can be improved. Accumulation degree. The jade, ^, and 卞 are anti-positive and 'due to the isolation region 212 that separates the charge trapping layer 204 into four independent regions-+ eight Mm ^ domains (that is, the four positions of the memory cell are separated from each other), So shopping can avoid the problem of Tian-Xiang's electron injection

9947twf.ptd

574755 V. Description of the invention (12) Produced. In addition, this isolation region 2 1 2 can also separate the charge trapping layer 204 into more than four regions (for example, six or eight), and then make the charge trapping regions under different columns have different channel regions. The initial value voltage can form a multi-bit structure. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

9947twf.ptd Page 16 574755 Brief description of the drawings 208, 218: Ion implantation steps 2 1 0, 2 2 0: Doped region 2 2 2: Field oxide layer 224: Conductor layer li 9947t.wf.ptd Section 18 pages

Claims (1)

574755 τ, patent application scope 1 · A silicon nitride read-only memory, the silicon nitride read-only memory includes: a substrate; a control gate, the control gate is arranged on the substrate; 'source region and A> and the pole region 5 the source region and the> and the pole region are disposed in the substrate on both sides of the control gate; a charge trapping layer is disposed between the control gate and the substrate, The charge trapping layer has an isolation region, and the isolation region separates the charge trapping layer into a source region charge trapping block and a drain region charge trapping block to form a two-bit structure; and a channel region The channel region is disposed in the substrate below the charge trapping layer and between the source region and the anode region. 2. The silicon nitride read-only memory as described in item 1 of the patent application scope, further comprising a gate dielectric layer, the gate dielectric layer being disposed between the control gate and the charge trapping layer. 3. The silicon nitride read-only memory according to item 2 of the patent application scope, wherein the gate dielectric layer includes a silicon oxide layer. 4. The silicon nitride read-only memory according to item 1 of the scope of the patent application, further comprising a tunneling oxide layer disposed between the charge trapping layer and the substrate. 5. The silicon nitride read-only memory described in item 1 of the scope of the patent application, wherein the material of the charge trapping layer includes silicon nitride. 6. The silicon nitride read-only memory as described in item 1 of the scope of patent application, wherein the material of the isolation region includes silicon oxide. 9947t.wf.ptd Page 19 574755 A silicon nitride read-only memory The silicon nitride read-only memory includes: a substrate; a control gate, the control gate is disposed on a charge trapping layer, and the charge trapping layer. ° placed between the control gate and the source region and a non-electrode region, the source charge is trapped in the substrate on both sides of the layer; and the sum electrode region is disposed in the first channel region, the channel region is disposed In the substrate between the electrode region and the drain region; and the directions of 1 2 1 ... ', the poles are the directions of columns, each column includes two charge trapping blocks, and each row includes η are positive integers) charge trapped blocks; where the silicon nitride read-only memory has no data written in it, the channel regions below the same row of charge trapped blocks have the same starting voltage, The channel regions under different columns of the charge trapping blocks have different starting voltages. "" = Ϊ́, the isolation region is provided in the charge trapping layer, and the barrier layer is separated into a plurality of charge trapping regions *, and a charge array is formed into the block array, and the charge trapping The block array runs from this source region to Page 20 1 · The silicon nitride read-only memory as described in item 7 of the scope of the patent application, which further includes a gate dielectric layer disposed on the control gate and the charge trapping layer. Between: 2 The silicon nitride read-only memory according to item 8 of the patent application park, wherein the gate dielectric layer includes a silicon oxide layer. 574755 VI. Scope of patent application 1 0. The nitride read-only memory as described in item 8 of the scope of patent application, which further includes a tunneling oxide layer disposed on the charge trapping layer and the substrate. between. 1 1 · The silicon nitride read-only memory as described in item 8 of the scope of patent application, wherein the material of the charge trapping layer includes silicon nitride. 1 2. The silicon nitride read-only memory according to item 8 of the scope of the patent application, wherein the material of the isolation region includes oxidized stone. 1 3. A method for manufacturing a silicon nitride read-only memory, the method includes the following steps: providing a substrate; forming a silicon oxide layer on the substrate; forming a charge trapping layer on the oxide layer; An isolation zone is formed in the trapping layer, which separates the charge trapping layer into a plurality of charge trapping blocks. The charge trapping blocks form a charge trapping block array. The charge trapping block array moves from a bit line. The direction to another bit line is the direction of a column, each column includes two charge trapping blocks, and each row includes n (η is a positive integer) charge trapping blocks; a gate is formed on the charge trapping layer A polar dielectric layer; patterning the gate dielectric layer and the charge trapping layer to expose regions intended to form the bit lines; forming the bit lines in the substrate on both sides of the charge trapping layer; Forming a control gate on the charge trapping layer; and performing an initial voltage adjustment step so that the channel regions under different columns of the charge trapping blocks have different initial voltages. 9947twf.ptd Page 21 574755 VI. Scope of patent application 14 · The manufacturing method of the nitride nitride read-only memory as described in item 13 of the patent application scope, wherein the material of the charge trapping layer includes silicon nitride. 1 5 · The method for manufacturing a nitride nitride read-only memory as described in item 13 of the scope of patent application, wherein the method of forming the isolation region in the conductor layer includes: forming a patterned light on the charge trapping layer A resist layer, the patterned photoresist layer exposing a region intended to form the isolation region; performing an ion implantation step, implanting a dopant in the region intended to form the isolation region; and performing a tempering process to make the dopant The isolation region is formed by reacting with the silicon of the charge trapping layer. 16. The method for manufacturing a silicon nitride read-only memory according to item 15 of the scope of the patent application, wherein the dopant implanted in the conductor layer includes oxygen ions. 1 7. The method for manufacturing a silicon nitride read-only memory as described in item 16 of the scope of patent application, wherein the implantation dose of oxygen ions includes about 1 018 atoms / cm 2 to about 2 018 atoms / cm 2. 1 8. The method for manufacturing a silicon nitride read-only memory according to item 16 of the scope of patent application, wherein the implantation energy of oxygen ions is about 20 仟 electron volts to about 80 仟 electron volts. 19. The method for manufacturing a silicon nitride read-only memory as described in item 16 of the scope of patent application, wherein the temperature of the tempering process includes about 950 ° C to about 115 ° C. 2 0. Silicon nitride read-only memory as described in item 16 of the scope of patent application 9947twf.ptd Page 22 574755 6. A manufacturing method in the scope of patent application, wherein after the step of forming the bit lines in the substrate on both sides of the charge trapping layer and forming the control gate on the charge trapping layer Before the step, a field oxide layer is formed on the bit line. 9947t.wf.ptd Page 23