KR100926688B1 - Large capacity nonvolatile memory and its manufacturing method - Google Patents

Abstract

Disclosed are a nonvolatile memory device capable of storing a plurality of bits in one cell transistor and a method of manufacturing the same. The cell transistor has four nitride films disposed independently of each other. Each nitride film may have an independent program operation. For this purpose, one cell transistor includes two gate structures separated from each other by an insulating layer. Each gate structure is provided with nitride films separated by an interlayer insulating film and provided in pairs. During a program operation for the nitride film, charge is trapped at the interface of the nitride film.

Flash Memory, SONOS, ONO, Charge Trap

Description

High Density Nonvolatile Memory and Method of manufacturing the same

The present invention relates to a nonvolatile memory, and more particularly, to a structure of a nonvolatile memory capable of storing 4 bits in one cell and a method of manufacturing the same.

Non-volatile memory is a device that can preserve stored information even when power supply is interrupted. In particular, flash memory is a representative device of nonvolatile memory, and has high integration and excellent data retention.

The operation aspect of the flash memory includes a program operation and an erase operation. The program operation is an operation of trapping charge at an interface of a floating gate or a nitride film. On the other hand, the erase operation is an operation for transferring the trapped charge to the lower substrate. The threshold voltage of the cell transistor is changed by the program operation and the erase operation. The storage operation of the information occurs by changing the threshold voltage.

In order to achieve the operation of the above-described flash memory, the gate structure uses a floating gate of a conductor or a nitride film capable of trapping charges at an interface. Structures using nitride films are referred to as ONO (Oxide / Nitride / Oxide). In such structures, a typical cell transistor can store one bit of data.

Recently, however, attempts have been made to store a plurality of bits in one cell transistor. For example, Korean Patent No. 442090 discloses a structure of a flash memory having a divided gate structure and a method of manufacturing the same. The patent focuses on the technology of having a pair of insulated gates in one active region. This configuration seeks to reduce the program voltage or maximize the program efficiency. However, even through the above-described configuration, the contents in which one cell transistor stores two bits of information are not disclosed, and the cell transistors are formed in the cell trench regions defined at a predetermined depth from the substrate. When the cell transistor is formed in the cell trench region, there is a problem that the manufacturing process is not easy. In addition, there is no specific description about a technique for storing a plurality of information in one cell transistor.

A first object of the present invention for solving the above problems is to provide a nonvolatile memory capable of storing 4-bit data in a cell transistor.

A second object of the present invention is to provide a method of manufacturing a nonvolatile memory for achieving the first object.

The present invention for achieving the first object, a substrate; Gate structures formed on the substrate and having nitride film pairs separated from each other; An insulating layer interposed between the gate structures to electrically insulate adjacent gate structures; A source region formed from the substrate and formed on one side of the gate structures; And a drain region formed from the substrate and facing the source region.

According to another aspect of the present invention, there is provided a method including: sequentially forming a tunneling dielectric layer and a nitride layer on a substrate; Patterning the nitride film in a second direction to form two separated nitride films; Filling the spaced space between the two nitride layers to form an interlayer insulating film; Forming a blocking dielectric layer on the interlayer insulating layer and on the separated nitride layer; Forming a gate electrode on the blocking dielectric layer; Patterning the gate electrode, the blocking dielectric film, the interlayer insulating film, the nitride film, and the tunneling dielectric film to form a gate pattern; And patterning the gate pattern in a first direction and forming two gate structures separated from each other by embedding an insulating layer in the patterned spaced space.

According to the present invention, the cell transistor, which is a storage unit of the nonvolatile memory, may store 4 bits of information. That is, four independent and separated nitride films provided in the cell transistor enable independent program operation for each nitride film. Therefore, much information can be stored compared to the area of the same chip, and a large capacity nonvolatile memory device can be implemented.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

When a component is referred to as being "top" or "bottom" of another component, it should be understood that other components may be present in between, although they may be formed directly on the other component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a perspective view showing a nonvolatile memory according to a preferred embodiment of the present invention.

Referring to FIG. 1, a source region 110 and a drain region 115 are defined in the substrate 100, and a channel region is defined between the source region 110 and the drain region 115. In addition, the first gate structure 101 and the second gate structure 103 are provided on the channel region. In addition, an insulating layer 170 is interposed between the first gate structure 101 and the second gate structure 103.

That is, the source region 110 and the drain region 115 are spaced apart from each other in the first direction, and the separation space is defined as a channel region. In addition, the insulating layer 170 extends in a first direction, and is provided in a manner of separating the first gate structure 101 and the second gate structure 103 in a second direction. The first and second directions are perpendicular to each other.

Each gate structure 101 and 103 includes a tunneling dielectric layer 120, a nitride layer 130, an interlayer insulating layer 140, a blocking dielectric layer 150, and a gate electrode 160. The nitride layers 130 are provided in pairs separated from each other in one gate structure 101 or 103. In addition, the interlayer insulating layer 140 is provided in the spaced space between the nitride layers 130.

First, the tunneling dielectric layer 120 is provided on the channel region. The tunneling dielectric layer 120 is preferably made of silicon oxide. In particular, the tunneling dielectric layer 120 is formed using a thermal oxidation process. In addition, the tunneling dielectric layer 120 may be formed by atomic layer deposition or chemical vapor deposition. The tunneling dielectric layer 120 described above is separated by the insulating layer 170. That is, the tunneling dielectric layer 120 is provided separately from the first gate structure 101 and the second gate structure 103.

The nitride layer 130 is provided on the tunneling dielectric layer 120. The nitride films 130 are provided in pairs in one gate structure 101 and 103, and the pair of nitride films 130 are separated from each other through the interlayer insulating layer 140. For example, the pair of nitride films 130 provided in the first gate structure 101 are provided in a state separated by the interlayer insulating layer 140. In addition, the nitride films 130 of the first gate structure 101 and the nitride films of the second gate structure 103 are provided in a separated state by the insulating layer 170.

Thus, the cell transistor, which is one nonvolatile memory device, has four separate nitride films.

A blocking dielectric layer 150 is provided on the nitride layer 130 and the interlayer insulating layer 140. The blocking dielectric layer 150 is made of silicon oxide or metal oxide. In particular, when the blocking dielectric layer 150 is formed of a metal oxide, the metal oxide may be selected from the group consisting of hafnium oxide, titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, and zirconium oxide having a high dielectric constant. At least one selected from these groups may be an additive of nitrogen or silicon, or a composite film thereof.

The blocking dielectric layer 150 is provided in an independent state for each of the gate structures 101 and 103. That is, the blocking dielectric layer 150 is provided in a state separated by the insulating layer 170.

The gate electrode 160 is provided on the blocking dielectric layer 150. The gate electrode 160 may be made of polycrystalline silicon, metal, conductive metal nitride, or conductive oxide. The gate electrode 160 is electrically connected to a word line (not shown). In addition, the gate electrode 160 is separated from each other by the insulating layer 170. That is, the gate electrode 160 is provided separately for each gate structure. In addition, one word line is connected to one gate electrode 160. That is, two word lines are connected to one cell transistor, and each word line is connected to two gate electrodes 160, respectively.

The insulating layer 170 electrically separates the two gate structures 101 and 103. The material constituting the insulating layer 170 may be any material that can electrically block the two gate structures 101 and 103.

In the nonvolatile memory described above, four nitride layers 130 are provided in one cell transistor. Each nitride film 130 can be programmed independently.

2A and 2B are cross-sectional views illustrating independent program operations for four nitride films, according to a preferred embodiment of the present invention.

2A and 2B illustrate the cell transistor illustrated in FIG. 1 cut along the first direction.

First, referring to FIG. 2A, a program voltage is applied to the gate electrode 160, and a predetermined bias is applied to the source region 110 and the drain region 115.

For example, the program voltage applied to the gate electrode 160 is 9V, the bias voltage applied to the source region 110 is 7V, and the bias voltage applied to the drain region 115 is set to 0V. The electrons in the drain region 115 move across the channel region by the bias voltage applied to the source region 110, and pass through the tunneling dielectric layer 120 by the program voltage and trap at the interface of the first nitride layer 130a. do.

2B, the program voltage applied to the gate electrode 160 is 9V, the bias voltage applied to the source region 110 is 0V, and the bias voltage applied to the drain region 115 is set to 7V. do. Electrons in the source region 110 move across the channel region by a bias applied to the drain region 115. In addition, the program voltage applied to the gate electrode 160 penetrates through the tunneling dielectric film 120 near the drain region 115 and is trapped at the interface of the second nitride film 130b.

The aforementioned program operation may be independently performed on the two gate structures 101 and 103 of FIG. 1. That is, the word lines are electrically connected to the gate electrodes 160 provided in the gate structures 101 and 103, respectively, so as to be independent of the nitride films 130a and 130b provided in pairs according to a program voltage supplied to the word lines. In program operation can be performed.

In addition, it will be apparent to those skilled in the art that the level of the program voltage and the level of the bias may be variously changed by the thickness, material, concentration of implanted ions, etc. of the elements constituting the cell transistor.

3A to 3E are perspective views illustrating a method of manufacturing the nonvolatile memory shown in FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 3A, the tunneling dielectric layer 120 and the nitride layer 130 are sequentially formed on the substrate 100.

The tunneling dielectric layer 120 formed on the substrate 100 may be formed using chemical vapor deposition, atomic layer deposition, or thermal oxidation, but preferably, thermal oxidation. That is, silicon is oxidized by charging the substrate 100 into the chamber and supplying hydrogen and oxygen. Therefore, when the tunneling dielectric layer 120 is formed by the thermal oxidation process, the tunneling dielectric layer 120 is made of silicon oxide.

Subsequently, a nitride film 130 is formed on the tunneling dielectric layer 120. The nitride film 130 is preferably made of silicon nitride.

Referring to FIG. 3B, a photoresist is coated on the nitride film 130, and a photoresist pattern extended in the second direction is formed using a conventional photolithography process. Subsequently, an etching process is performed using the formed photoresist pattern as an etching mask. Etching is performed such that the tunneling dielectric layer 120 under the nitride layer 130 is exposed. Accordingly, the nitride layers 130 extended in the second direction and separated from each other may be obtained by the etching process.

Referring to FIG. 3C, an interlayer insulating layer 140 filling a space between the nitride layers 130 is formed, and a blocking dielectric layer 150 is formed on the interlayer insulating layer 140 and the nitride layer 130. Subsequently, the gate electrode 160 is formed on the blocking dielectric layer 150.

The interlayer insulating layer 140 may be formed of the same material as the blocking dielectric layer 150. Therefore, the interlayer insulating layer 140 and the blocking dielectric layer 150 may be processed in the same process and formed at substantially the same time.

Referring to FIG. 3D, the gate pattern 105 is formed by performing an etching process on the structure on the substrate 100 illustrated in FIG. 3C, and an ion implantation process is performed using the gate pattern 105 as a mask. Therefore, the source region 110 and the drain region 115 are formed in the substrate regions on both sides of the gate pattern 105.

In FIG. 3D, after forming the gate pattern 105, sidewall spacers (not shown) may be formed on side surfaces of the gate pattern 105.

Referring to FIG. 3E, a photoresist is applied on the gate pattern, and a photoresist pattern is formed using a conventional photolithography process. In addition, the gate pattern is etched using the formed photoresist pattern as an etching mask. The gate pattern is separated into two gate structures 101 and 103 by an opening formed by etching. In addition, the etching proceeds to expose the surface of the substrate 100 across the gate pattern.

Subsequently, the insulating layer 170 is buried in the opening where the surface of the substrate 100 is exposed. The insulating layer 170 may be applied to any material having an electrical insulating property. In addition, the insulating layer 170 is formed along the first direction.

Through the above-described process, one cell transistor may form four nitride layers 130 that may trap charges independently of each other.

Accordingly, 4-bit data can be stored in one cell transistor of the nonvolatile memory. That is, one cell transistor can implement four states by performing a program operation on four independently formed nitride films, thereby allowing one cell transistor to store four bits.

1 is a perspective view showing a nonvolatile memory according to a preferred embodiment of the present invention.

2A and 2B are cross-sectional views illustrating independent program operations for four nitride films, according to a preferred embodiment of the present invention.

3A to 3E are perspective views illustrating a method of manufacturing the nonvolatile memory shown in FIG. 1 according to a preferred embodiment of the present invention.

Claims (9)

Board; Gate structures formed on the substrate and having nitride film pairs separated from each other; An insulating layer extending in a first direction, the insulating layer being formed from the substrate to electrically insulate the two gate structures in a second direction perpendicular to the first direction; A source region formed from the substrate and formed on one side of the gate structures; And And a drain region formed from said substrate and opposing said source region. The method of claim 1, wherein the gate structure, A tunneling dielectric layer formed on the substrate; The nitride layer pair formed on the tunneling dielectric layer; An interlayer insulating layer buried in the spaced space between the nitride film pairs; A blocking dielectric film formed over the interlayer insulating film and on the nitride film pair; And And a gate electrode formed on the blocking dielectric layer. The non-volatile memory according to claim 2, wherein the interlayer insulating film separates the nitride films of the nitride film pairs from each other. 3. The nonvolatile memory as claimed in claim 2, wherein the tunneling dielectric film is made of silicon oxide, and charges are trapped at an interface of the nitride film during a program operation. The nonvolatile memory as claimed in claim 4, wherein the nitride film pairs individually trap a charge by applying a program voltage to each of the gate electrodes during a program operation. Sequentially forming a tunneling dielectric film and a nitride film on the substrate; Patterning the nitride film in a second direction to form two separated nitride films; Filling the spaced space between the two nitride layers to form an interlayer insulating film; Forming a blocking dielectric layer on the interlayer insulating layer and on the separated nitride layer; Forming a gate electrode on the blocking dielectric layer; And Patterning the gate electrode, blocking dielectric film, interlayer insulating film, nitride film, insulating film, and tunneling dielectric film to form a gate pattern; And Patterning the gate pattern in a first direction and forming two gate structures separated from each other by filling an insulating layer in the patterned separation space. The method of claim 6, wherein the forming of the interlayer dielectric layer and the forming of the blocking dielectric layer are performed in the same process. The method of claim 6, wherein the patterning in the second direction with respect to the nitride film is performed to expose the lower tunneling dielectric film. The method of claim 6, wherein the patterning of the gate pattern is performed such that the surface of the substrate is exposed.

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