KR20100131718A - Junction of a non-volatile memory device and forming method of the same - Google Patents

Abstract

PURPOSE: A junction of a non-volatile memory device and a forming method of the same are provided to improve the uniformity of current flowing a bit line from a string structure by making junction areas connected to drain contact plugs unsymmetrical. CONSTITUTION: A tunnel insulating layer(104) is formed on a semiconductor substrate(102). A charge trapping layer(106) is formed on the turner insulating layer. A dielectric film(108) is formed on the charge trapping layer. The control gate film(110) is formed on the dielectric film. A hard mask pattern(112) is formed on the control gate film.

Description

Junction of a non-volatile memory device and forming method of the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a junction region of a nonvolatile memory device and a method of forming the same.

A memory cell array of a NAND flash memory device, which is advantageous for high integration and high capacity among nonvolatile memory devices, includes a string structure arranged in a matrix form. Each string structure includes a drain select transistor having a drain connected to a bit line, a source select transistor having a source connected to a common source line, and a plurality of memory cells. In each string structure, a plurality of memory cells are connected in series through the junction region between the drain select transistor and the source select transistor.

The junction region includes a source region, a drain region and a cell junction region. The source region is connected to the common source line through a source contact plug. The drain region is connected to the bit line through the drain contact plug. The cell junction region connects a plurality of memory cells in series in the string structure.

The source contact plug and the drain contact plug form an insulating film on the semiconductor substrate, and then form a source contact hole for exposing the source region by etching the insulating film and a drain contact hole for exposing the drain region, thereby forming the inside of the source contact hole and the drain contact hole. Is formed by filling with a conductive film.

The width of the source contact hole and the drain contact hole is gradually narrowed as the device is highly integrated, and since the thickness of the insulating layer is not reduced, the aspect ratio of the source contact hole and the drain contact hole is rapidly increased. In this case, the source contact hole is formed in a bar-type of a line shape to expose the source regions of a plurality of string structures at the same time, so it is not a big problem in securing a process margin. On the other hand, the drain contact holes should be separated to expose the drain regions formed in each string structure one-to-one. Therefore, it is difficult to secure a margin of the etching process for forming the drain contact hole. In order to solve this problem, a method of arranging drain contact holes in two rows is provided in a zigzag manner so that neighboring drain contact holes are arranged in different rows.

1A and 1B are photographs illustrating drain contact holes.

Referring to FIG. 1A, when the drain contact holes DCT are arranged in a line, when the drain contact holes are etched so that the drain region is sufficiently exposed, the sidewalls of the drain contact holes are excessively etched so that neighboring drain contact holes DCT are etched. The connection between the fields may occur. On the other hand, when the insulating layer is etched so that the drain contact holes DCT are not connected to each other, the insulating layer may not be etched to a sufficient depth, and thus, the drain region may not be exposed through the drain contact hole DCT.

Referring to FIG. 1B, the drain contact holes DCTs may be arranged in a zigzag to improve the problem described above with reference to FIG. 1A to secure an etching margin. That is, the drain contact holes DCT include the first drain contact holes DCT1 constituting the first row and the second drain contact holes DCT2 constituting the second row. The DCT1 and the second drain contact hole DCT2 are formed to be alternately arranged in a diagonal direction without being parallel. As a result, a gap between the drain contact holes DCTs adjacent to each other may be secured.

2A and 2B are graphs showing the amount of current flowing in a bit line according to a voltage applied to a gate.

Referring to FIG. 2A, when the drain contact plugs are formed in a line as shown in FIG. 1A, almost the same current Id flows through the bit lines BL1, BL2, and BL3 for the same gate voltage Vg. .

On the other hand, referring to FIG. 2B, when the drain contact holes are zigzagly formed as shown in FIG. 1B, between the odd bit lines BL1 and BL3 and the even bit line BL2 for the same gate voltage Vg. Remarkably different current Id flows. This is because when the drain contact holes are zigzag formed, the distance between the source contact plugs and the drain contact plugs is changed so that the resistances of the junction regions are different. Therefore, even if the drain contact holes are formed in a zigzag to secure the process margin, there is a need for a method that does not lower the operating characteristics of the nonvolatile memory device.

The present invention provides a junction region of a nonvolatile memory device and a method for forming the same, which may improve the uniformity of electrical characteristics of the nonvolatile memory device even when contact holes are zigzag to secure a process margin of the nonvolatile memory device.

A method of forming a junction region of a nonvolatile memory device according to an exemplary embodiment of the present invention includes a gate including a drain select line, a source select line, and a plurality of word lines arranged side by side between the drain select line and the source select line. Forming a pattern on top of the semiconductor substrate, a first drain contact hole exposing the semiconductor substrate adjacent to the word line between the drain select line and the word line, and a second drain contact exposing the semiconductor substrate adjacent to the drain select line Forming an insulating film including a hole, and forming a semiconductor substrate through the first and second drain contact holes to have a deeper or higher concentration of impurity ions implanted through the second drain contact hole than the first drain contact hole. Implanting the impurity ions into the.

Implanting impurity ions into the semiconductor substrate through the first and second drain contact holes simultaneously implanting impurity ions into the semiconductor substrate through the first and second drain contact holes, blocking the first drain contact hole, and Forming a photoresist pattern opening the second drain contact hole; and further implanting impurity ions into the semiconductor substrate through the second drain contact hole using the photoresist pattern as a mask.

Injecting impurity ions simultaneously into the semiconductor substrate through the first and second drain contact holes is performed by implanting impurity ions at a dose of 1E13 to 1E16 (ion / cm 2) at 1 to 20 KeV energy.

The implantation of the impurity ions into the semiconductor substrate through the second drain contact hole using the photoresist pattern as a mask is performed by implanting the impurity ions at a dose of 1E13 to 1E16 (ion / cm 2) at 1 to 30 KeV energy.

A method of forming a junction region of a nonvolatile memory device according to a second exemplary embodiment of the present invention includes a gate pattern including a drain select line, a source select line, and a plurality of word lines arranged side by side between the drain select line and the source select line. Forming an upper portion of the semiconductor substrate, a first drain contact hole exposing the semiconductor substrate adjacent to the word line between the drain select line and the word line, and a second drain contact hole exposing the semiconductor substrate adjacent to the drain select line. Forming an insulating film including an insulating film, implanting impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole, and forming a second drain contact hole than the impurity ions injected into the first drain contact hole. Increasing the activation degree of the impurity ion implanted in the.

The activation of the impurity ions injected into the second drain contact hole rather than the impurity ions injected into the first drain contact hole may be performed by heat-treating the semiconductor substrate exposed through the second drain contact hole through laser irradiation.

 It is preferable to use a green laser as the laser.

The heat treatment performed by laser irradiation targets the junction area within 200 microseconds of a target.

After implanting the impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole, the activation degree of the impurity ions implanted in the second drain contact hole higher than the impurity ions implanted in the first drain contact hole Prior to the step, the impurity ions implanted into the first and second drain contact holes are activated using an RTA or furnace method.

The step of activating the impurity ions using the RTA or furnace method is carried out at a temperature of 800 ℃ to 1000 ℃.

The step of activating impurity ions using an RTA or furnace method is carried out within 60 seconds at a ramp-up rate of 150 ° C./sec in N ₂ atmosphere.

Injecting the impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole is performed by implanting the impurity ions with 1 to 20 KeV energy at a dose of 1E13 to 1E16 (ion / cm 2).

In the first and second embodiments, the impurity ions are n-type impurity ions containing phosphorus or arsenic.

In the first and second embodiments, forming the insulating film including the first and second drain contact holes may include forming the first insulating film on the semiconductor substrate including the gate pattern, and forming the insulating film on the first insulating film. Forming a second insulating film and etching the first and second insulating films to expose the semiconductor substrate.

Forming a source contact hole by etching the first insulating film to expose the semiconductor substrate in parallel to the word line between the source select line and the word line after the forming of the first insulating film; And forming a source region in the semiconductor substrate through the source contact hole.

The junction region of the semiconductor device according to the first exemplary embodiment of the present invention may include a semiconductor substrate including a drain select line, a source select line, and an upper portion formed with a plurality of word lines arranged side by side between the drain select line and the source select line; And a first drain region formed by implanting impurity ions into the semiconductor substrate adjacent to the word line between the drain select line and the word line, and having a depth or a higher depth than the first drain region in the semiconductor substrate between the drain select line and the word line. And a second drain region formed by implanting impurity ions.

A junction region of a nonvolatile memory device according to a second embodiment of the present invention includes a semiconductor device including a drain select line, a source select line, and an upper portion formed with a plurality of word lines arranged side by side between the drain select line and the source select line. A first drain region formed by implanting impurity ions into the semiconductor substrate adjacent to the word line between the substrate, the drain select line and the word line, and formed by implanting impurity ions into the semiconductor substrate between the drain select line and the word line, The second drain region includes a higher degree of activation of ions compared to the first drain region.

In the first and second embodiments, the junction region includes a source region formed in the semiconductor substrate parallel to the word line between the source select line and the word line.

According to the present invention, asymmetrical formation of junction regions connected to zigzag drain contact plugs allows currents flowing from the respective string structures to the bit lines even if the distance between the drain contact plug and the source contact plug differs for each string structure. The uniformity of can be improved. In addition, the present invention can overcome the leakage current increase characteristic of the drain contact plug closer to the source contact plug.

As described above, in the present invention, the drain contact plugs may be zigzag to secure a process margin for forming the drain contact holes that define the region in which the drain contact plugs are to be formed. In addition, in the present invention, it is possible to secure the margin of the process of forming the drain contact holes and to improve the uniformity of the current flowing through the bit line from the string structure, thereby improving the reliability of the nonvolatile memory device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a layout diagram schematically illustrating a portion of a memory cell array of a nonvolatile memory device according to the present invention.

Referring to FIG. 3, a memory cell array of a nonvolatile memory device according to the present invention includes a drain select line DSL, word lines WL, and a source select line SSL formed side by side, and a word line WL. ) And bit lines BL formed to intersect with each other. The drain select line DSL, the word lines WL, and the source select line SSL are alternately arranged, and the active region A and the element are formed on the active region A and the device isolation region B, which are formed side by side. It is formed to intersect the separation region (B).

The device isolation region B is a region where the device isolation layer formed of an insulator is formed, and the active region A is a region separated by the device isolation layer formed in the device isolation region B. FIG.

The word lines WL are formed by connecting the gates of the memory cells, and a plurality of word lines WL are formed between the drain select line DSL and the source select line SSL. The drain select line DSL is formed by connecting gates of the drain select transistor, and the source select line SSL is formed by connecting gates of the source select transistor.

The bit lines BL include a plurality of first bit lines BL1 and second bit lines BL2 arranged alternately with each other.

A plurality of memory cells formed between the drain select transistor and the source select transistor on one active region A are connected in series with a junction region formed in the active region A interposed therebetween to form one string structure ST. do.

The string structure ST is connected to the first bit line BLa through the first drain contact plug 126a formed between the drain select line DSL and the word line WL, or is connected to the drain select line DSL and the word. It is connected to the second bit line BLb through a second drain contact plug 126a formed between the lines WL. That is, the drain contact plug 126 including the first and second drain contact plugs 126a and 126b serves to connect the string structure ST and the bit line BL.

The first and second drain contact plugs 126a and 126b are formed inside the drain contact holes, respectively, and are arranged in a zigzag to secure a process margin during the drain contact hole forming process by widening the gap between the drain contact holes. do. That is, the first and second drain contact plugs 126a and 126b are alternately arranged, not arranged in a row, but arranged in different rows.

In addition, the string structures ST may include a source contact plug 122 formed in parallel with the source select line SSL in a line-type bar-type between the source select line SSL and the word line WL. Common connections are made to common source lines not shown in the drawings.

Meanwhile, a plurality of memory cells formed between the drain select transistor and the source select transistor in the string structure ST are connected to each other, and the junction region formed in the active region A of the semiconductor substrate is the source region 116s and the drain region 116d. And cell junction region 116c. The source region 116s is connected to the source contact plug 122 and is formed in the active region A between the source select line SSL and the word line WL. The drain region 116d includes a first drain region 116d1 connected to the first drain contact plug 126a and a second drain region 116d2 connected to the second drain contact plug 126b and includes a drain select line DSL. ) And the word line WL in the active region A. The cell junction region 116c is formed in the active region A between the word lines WL.

When the first and second drain contact plugs 126a and 126b are arranged in a zigzag as described above, the distance between the first drain contact plug 126a and the source contact plug 122 may be different from that of the second drain contact plug 126b. It is formed differently from the distance between the source contact plug 122. In this case, the present invention provides a method of forming a junction region to make the resistance constant in the junction region of the string structures ST when the device is driven in the following embodiments.

4A through 4E are cross-sectional views illustrating a method of forming a junction region of a nonvolatile memory device according to a first embodiment of the present invention. In particular, FIGS. 4A to 4E are cross-sectional views taken along lines "I-I '" and lines "II-II'" shown in FIG.

Referring to FIG. 4A, a tunnel insulating layer 104 is formed on a semiconductor substrate 102 in which a bulk structure (eg, at least one of n well and p well) is formed and ions are implanted to adjust a threshold voltage. Gate patterns G are formed on the tunnel insulating layer 104.

The tunnel insulating layer 104 may be formed of an oxide film and may be formed through an oxidation process.

The gate pattern G is formed in a structure in which the charge storage film 104, the dielectric film 108, and the control gate film 110 are stacked. In addition, a gate hard mask pattern 112 used as an etching barrier may remain in the uppermost layer of the gate pattern G during the etching process for forming the gate pattern G. The control gates 110 of the gate patterns G are connected to form a source select line SSL, a drain select line DSL, and a word line WL.

Hereinafter, an example of the formation process of the above-mentioned gate pattern G is demonstrated concretely.

First, in order to form the gate pattern G, the charge storage layer 106 is formed on the tunnel insulating layer 104. The charge storage layer 106 may be formed using polysilicon as a film that stores or emits electric charges.

Then, the charge storage layer 106 and the tunnel insulating layer 104 formed on the element isolation region (B of FIG. 3) of the semiconductor substrate 102 are etched and the semiconductor substrate 102 of the element isolation region is etched to form a trench (not shown). C). An insulating material is formed in the trench (not shown) to form an isolation layer (not shown) defining an active region (A of FIG. 3).

Thereafter, the dielectric film 108 is formed on the charge storage film 106 including the device isolation film. The dielectric film 108 may be formed to have an ONO (Oxide / Nitride / Oxide) structure, which is a stacked structure of an oxide film, a nitride film, and an oxide film as an insulating film between the charge storage film 106 and the control gate conductive film 110. The dielectric layer 108 may include a gate contact hole exposing the charge storage layer 106 formed of the polysilicon layer in a region where the drain select line DSL and the source select line SSL are to be formed. The gate contact hole may electrically connect the control gate layer 110 and the charge storage layer 106 formed of the polysilicon layer.

Subsequently, the control gate layer 110 is formed on the dielectric layer 108. The control gate layer 110 may be formed as a single layer structure using a polysilicon layer, or may be formed as a laminated layer structure of a polysilicon layer and a metal layer to improve resistance. The hard mask pattern 112 used in the gate patterning process is formed on the control gate layer 110. The hard mask pattern 112 is patterned using a photoresist pattern (not shown) formed using a photolithography process including an exposure and development process. Thereafter, the gate pattern G is formed by etching the control gate layer 110, the dielectric layer 108, and the charge storage layer 106 by an etching process using the hard mask pattern 112 as an etching barrier. Thereafter, the remaining photoresist pattern is removed.

Referring to FIG. 4B, the cell junction region 116c and the first preliminary portion are formed on the semiconductor substrate 102 by an ion implantation process using the source select line SSL, the drain select line DSL, and the word lines WL as masks. The junction region 114a is formed. An ion implantation process for forming the cell junction region 116c and the first preliminary junction region 114a can be performed using n-type impurity ions.

The cell junction region 116c is formed in the semiconductor substrate 102 between the word lines WL, and the first preliminary junction region 114a is between the source select line SSL and the word line WL, and the drain select. It is formed between the line DSL and the word line WL.

Referring to FIG. 4C, an spacer layer is formed on a surface of a semiconductor substrate 102 including a drain select line DSL, a source select line SSL, and a word line WL, followed by an etch-back process. The spacer layer is etched using the etching method so that the spacer layer remains only on the sidewall of the gate pattern G. As a result, a spacer 118 is formed on the sidewall of the gate pattern G.

Subsequently, the first insulating layer 120 is formed on the semiconductor substrate 102 including the drain select line DSL, the source select line SSL, and the word line WL, and the first insulating layer 120 is etched. A source contact hole SCT exposing the semiconductor substrate 102 between the source select line SSL and the word line WL is formed. The source contact hole SCT is formed in the form of a line parallel to the source select line SSL and the word line WL between the source select line SSL and the word line WL to form an active region of the semiconductor substrate 102. It can be formed to expose the device isolation region (B of FIG. 3) as well as (A of FIG. 3).

Thereafter, after implanting n-type impurity ions into the first preliminary junction region of the semiconductor substrate 102 exposed through the source contact hole SCT, a rapid thermal process (RTP) for activating the implanted ions is performed. ). As a result, a source region 116S is formed in the semiconductor substrate 102 between the source select line SSL and the word line WL. Thereafter, the inside of the source contact hole SCT is filled with a conductive material to form a source contact plug 122 connected to the source region 116S.

Subsequently, a second insulating film 124 is formed on the first insulating film 120 including the source contact plug 122. The first and second drain contact holes DCT1, which expose the semiconductor substrate 102 between the drain select line DSL and the word line WL by etching the second insulating layer 124 and the first insulating layer 120, DCT2). The first drain contact hole DCT1 is formed to be adjacent to the word line WL among the drain select line DSL and the word line WL, and the second drain contact hole DST2 is formed with the drain select line DSL. The word line WL is formed closer to the drain select line DSL. As such, the first and second drain contact holes DST1 and DST2 adjacent to each other are not formed in a zigzag form, thereby securing an interval between the adjacent drain contact holes DST1 and DST2 to secure an etching process margin. have.

Thereafter, n-type impurity ions such as arsenic (As) or phosphorus (P) are implanted into the first preliminary junction region of the semiconductor substrate 102 exposed through the first and second drain contact holes DST1 and DST2. . At this time, impurity ions are implanted at a dose of 1E13 to 1E16 (ion / cm 2), and ion implantation energy can be used at 1 to 20 KeV. Thereafter, a rapid thermal process (RTP) is performed to activate ions implanted in the first preliminary junction region. As a result, a first drain region 116d1 and a second preliminary junction region 114b are formed in the semiconductor substrate 102 between the drain select line DSL and the word line WL. The first drain region 116d1 is formed in the semiconductor substrate 102 under the first drain contact hole DST1, and the second preliminary junction region 114b is formed in the semiconductor substrate 102 under the second drain contact hole DST2. Is formed.

Referring to FIG. 4D, the first drain region 116d1 may be blocked through the first drain contact hole DST1 and the semiconductor substrate 102 may be opened through the second drain contact hole DST1. The photoresist pattern PR is formed.

Subsequently, arsenic (As) or phosphorus (P) and phosphorus (P) are formed in the second preliminary junction region of the semiconductor substrate 102 exposed through the second drain contact hole DST2 using the photoresist pattern PR as an ion implantation mask. The same n-type impurity ions are implanted. At this time, impurity ions are implanted at a dose of 1E13 to 1E16 (ion / cm 2), and ion implantation energy can be used at 1 to 30 KeV. Thereafter, a rapid heat treatment process (RTP) is performed to activate ions implanted in the second preliminary junction region. As a result, the second preliminary junction region becomes the second drain region 116d2. Since the second drain region 116d2 is further implanted with ions compared to the first drain region 116d1, and the impurity ions can be implanted by increasing the ion implantation energy, the second drain region 116d2 is the first drain region ( Deeper than 116d1) and the concentration of impurity ions is high.

Referring to FIG. 4E, a first drain is formed in the first drain contact hole DST1 by removing the photoresist pattern (PR of FIG. 4D) and filling the first and second drain contact holes DST1 and DST2 with a conductive material. The contact plug 126a is formed, and the second drain contact plug 126b is formed in the second drain contact hole DST2.

Thereafter, first and second bit lines BLa and BLb are formed on the second insulating layer 124 and are electrically connected to the first and second drain contact plugs 126a and 126b, respectively.

Meanwhile, in the first embodiment of the present invention, the impurity ion implantation processes for forming the junction region are performed in order to avoid the shadowing effect in which the implantation of the impurity ions is blocked by the sidewall of the gate pattern G. It is preferably carried out in a zero-tilted implant process perpendicular to 102.

As described above, in the first embodiment of the present invention, ions are additionally implanted into the second drain region 116d2 where the distance to the source contact plug SCT is relatively far, so that the impurity ions may be removed from the first drain region 116d1. By increasing or increasing the content, it is possible to compensate for the increase in resistance with increasing distance. In addition, in the first embodiment of the present invention, since the distance between the first and second drain contact plugs 126a and 126b and the source contact plug 122 can compensate for an increase in resistance due to a difference, the source contact plug 122 The leakage current increasing characteristic of the first drain contact plug 126a that is further adjacent to the overhang may be overcome. Further, in the second embodiment of the present invention, since the distance between the first and second drain contact plugs 126a and 126b and the source contact plug 122 may compensate for an increase in resistance due to a difference, the first and second drains The uniformity of the current flowing through the first and second bit lines BLa and BLb connected to the contact plugs 126a and 126b may be improved.

5A through 5C are cross-sectional views illustrating a method of forming a junction region in a nonvolatile memory device according to a second embodiment of the present invention.

Referring to FIG. 5A, the tunnel insulating film 204 is formed on the semiconductor substrate 202 in the same manner as described above with reference to FIG. 4A, and the drain select line DSL and the word line are formed on the tunnel insulating film 204. WL) and the gate patterns G including the source select line SSL are formed.

Thereafter, the cell junction region 216c and the first preliminary junction region (not shown) are formed in the semiconductor substrate 102 in the same manner as described above with reference to FIG. 4B. Thereafter, the source contact hole SCT is formed in the first insulating film 220 in the same manner as described above with reference to FIG. 4C, and the source region 216s is formed through the source contact hole SCT, and then the source contact hole is formed. A source contact plug 222 connected to the source region 216s is formed in the SCT. Thereafter, the first and second drain contact holes DCT1 and DCT2 are formed in the second insulating layer 224 in the same manner as described above with reference to FIG. 4C, and the semiconductor substrate 202 under the first drain contact hole DST1 is formed. ) Is formed in the first drain region 116d1, and the second preliminary junction region 214b is formed in the semiconductor substrate 202 under the second drain contact hole DST2.

Meanwhile, a rapid thermal process (RTP) for activating ions implanted into the first preliminary junction region in the step of forming the first drain region 216d1 and the second preliminary junction region (214b in FIG. 5A). This is carried out. In the second embodiment of the present invention, in order to equally activate the ions of the first drain region 216d1 and the second preliminary junction region 214b of FIG. It is preferable to heat-treat the first preliminary junction region in an atmosphere in which N ₂ is injected at a ramp-up ratio of 150 ° C./sec or less for a time. At temperatures below 1000 ° C., the activation rate of ions is relatively low, within 40%.

Referring to FIG. 5B, in the second embodiment of the present invention, after forming the first drain region 216d1 and the second preliminary junction region 214b of FIG. 5A, an activation ratio of impurity ions implanted into the second preliminary junction region ( Activated Ratio) is higher than the first drain region 216d1. As a result, a second drain region 216d2 having a higher activation ratio of ions than the first drain region 216d1 is formed.

In order to selectively activate only the second preliminary junction region to form the second drain region 216d, it is preferable to perform a heat treatment process by irradiating a laser. The laser is straight and can generate a high temperature in a short time, as shown in FIG. 6, thus enabling the second preliminary junction region to be selectively activated within a short process time and eliminating a separate mask process such as a photoresist pattern. have. In the second embodiment of the present invention, it is preferable to use a green laser to increase the amount of activated ions in the second drain region 216d2 as compared with the first drain region 216d1. In addition, the heat treatment performed by laser irradiation is performed to target the bonding area within 200 mW for a short time within 1 second.

Referring to FIG. 5C, after the first and second drain regions 216d1 and 216d2 are formed, the first and second drain contact holes DST1 and DST2 are filled with a conductive material to form the first drain contact holes DST1. The first drain contact plug 226a is formed, and the second drain contact plug 226b is formed in the second drain contact hole DST2.

Thereafter, first and second bit lines BLa and BLb are formed on the second insulating layer 124 and are electrically connected to the first and second drain contact plugs 226a and 226b, respectively.

Meanwhile, in the second embodiment of the present invention, impurity ion implantation processes for forming the junction region are performed in order to avoid a shadowing effect in which the implantation of impurity ions is blocked by the sidewall of the gate pattern G. It is preferably carried out in a zero-tilted implant process perpendicular to 202.

As described above, in the second embodiment of the present invention, the distance to the source contact plug SCT is increased by increasing the activity of ions in the second drain region 216d2, which is relatively far, than the first drain region 216d1. This can compensate for the increase in resistance. In addition, in the second embodiment of the present invention, since the distance between the first and second drain contact plugs 226a and 226b and the source contact plug 222 may compensate for an increase in resistance due to a difference, the source contact plug 222 The leakage current increasing characteristic of the first drain contact plug 226a that is further adjacent to may be overcome. In addition, in the second embodiment of the present invention, since the distance between the first and second drain contact plugs 226a and 226b and the source contact plug 222 may compensate for an increase in resistance due to a difference, the first and second drains The uniformity of the current flowing through the first and bit lines BLa and BLb respectively connected to the contact plugs 226a and 226b can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are photographs showing drain contact holes.

2A and 2B are graphs showing the amount of current flowing in a bit line according to a voltage applied to a gate.

3 is a layout diagram schematically showing a part of a memory cell array of a nonvolatile memory device according to the present invention;

4A through 4E are cross-sectional views illustrating a method of forming a junction region in a nonvolatile memory device according to a first embodiment of the present invention.

5A through 5C are cross-sectional views illustrating a method of forming a junction region in a nonvolatile memory device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

WL: word line DSL: drain select line

SSL: Source Select Line SCT: Source Contact Hole

222, 122: source contact plug 116s: source region

102 and 202: semiconductor substrates 116c and 216c: cell junction region

116d1 and 216d1: first drain region 116d2 and 216d2: second drain region

DST1: first drain contact hole DST2: second drain contact hole

Claims (24)

Forming a gate pattern on the semiconductor substrate, the gate pattern including a drain select line, a source select line, and a plurality of word lines arranged side by side between the drain select line and the source select line; An insulating film between the drain select line and the word line, the first drain contact hole exposing the semiconductor substrate adjacent to the word line and the second drain contact hole exposing the semiconductor substrate adjacent to the drain select line; Forming; And Implanting the impurity ions into the semiconductor substrate through the first and second drain contact holes such that the depth of the impurity ions injected through the second drain contact hole is higher than the first drain contact hole or the concentration is higher. A method of forming a junction region in a nonvolatile memory device comprising the step. The method of claim 1, Implanting the impurity ions into the semiconductor substrate through the first and second drain contact holes Simultaneously implanting the impurity ions into the semiconductor substrate through the first and second drain contact holes; Forming a photoresist pattern blocking the first drain contact hole and opening the second drain contact hole; And And implanting the impurity ions into the semiconductor substrate through the second drain contact hole using the photoresist pattern as a mask. The method of claim 1, And the impurity ions are n-type impurity ions containing phosphorus or arsenic. The method of claim 1, Forming an insulating layer including the first and second drain contact holes Forming a first insulating layer on the semiconductor substrate including the gate pattern; Forming a second insulating film on the first insulating film; And Etching the first and second insulating layers to expose the semiconductor substrate. The method of claim 4, wherein After the forming of the first insulating film, before the forming of the second insulating film, Forming a source contact hole by etching the first insulating layer to expose the semiconductor substrate parallel to the word line between the source select line and the word line; And And forming a source region in the semiconductor substrate through the source contact hole. The method of claim 2, Simultaneously implanting the impurity ions into the semiconductor substrate through the first and second drain contact holes A method of forming a junction region in a nonvolatile memory device, wherein the impurity ions are implanted at a dose of 1E13 to 1E16 (ion / cm 2) at 1 to 20 KeV energy. The method of claim 2, Implanting the impurity ions into the semiconductor substrate through the second drain contact hole using the photoresist pattern as a mask; A method of forming a junction region in a nonvolatile memory device, wherein the impurity ions are implanted at 1 to 30 KeV energy at a dose of 1E13 to 1E16 (ion / cm 2). Forming a gate pattern on the semiconductor substrate, the gate pattern including a drain select line, a source select line, and a plurality of word lines arranged side by side between the drain select line and the source select line; An insulating film between the drain select line and the word line, the first drain contact hole exposing the semiconductor substrate adjacent to the word line and the second drain contact hole exposing the semiconductor substrate adjacent to the drain select line; Forming; Implanting impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole; And And increasing the activation degree of the impurity ions implanted into the second drain contact hole rather than the impurity ions implanted into the first drain contact hole. The method of claim 8, Increasing the activation degree of the impurity ions injected into the second drain contact hole rather than the impurity ions injected into the first drain contact hole And a heat treatment of the semiconductor substrate exposed through the second drain contact hole by laser irradiation. The method of claim 9, A method for forming a junction region of a nonvolatile memory device using a green laser as the laser. The method of claim 9, The method of forming a junction region of a nonvolatile memory device, wherein the heat treatment performed by the laser irradiation targets a junction region within 200 mW. The method of claim 8, Implanting impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole; Before the step of increasing the activation of ions, And activating the impurity ions implanted in the first and second drain contact holes by using an RTA or a furnace method. 13. The method of claim 12, And activating the impurity ions using an RTA or a furnace method at a temperature of 800 ° C to 1000 ° C. 13. The method of claim 12, Activating the impurity ions using an RTA or furnace method A method of forming a junction region for a nonvolatile memory device, which is performed within 60 seconds at a ramp-up rate of 150 ° C./sec in an N ₂ atmosphere. The method of claim 8, And the impurity ions are n-type impurity ions containing phosphorus or arsenic. The method of claim 8, Forming an insulating layer including the first and second drain contact holes Forming a first insulating layer on the semiconductor substrate including the gate pattern; Forming a second insulating film on the first insulating film; And Etching the first and second insulating layers to expose the semiconductor substrate. The method of claim 16, After the forming of the first insulating film, before the forming of the second insulating film, Forming a source contact hole by etching the first insulating layer to expose the semiconductor substrate parallel to the word line between the source select line and the word line; And And forming a source region in the semiconductor substrate through the source contact hole. The method of claim 8, Implanting impurity ions into the semiconductor substrate through the first drain contact hole and the second drain contact hole A method of forming a junction region in a nonvolatile memory device, wherein the impurity ions are implanted at a dose of 1E13 to 1E16 (ion / cm 2) at 1 to 20 KeV energy. A semiconductor substrate including a drain select line, a source select line, and an upper portion formed with a plurality of word lines arranged side by side between the drain select line and the source select line; A first drain region formed by implanting impurity ions into the semiconductor substrate adjacent to the word line between the drain select line and the word line; And And a second drain region formed between the drain select line and the word line by implanting the impurity ions into the semiconductor substrate at a depth deeper or higher than that of the first drain region. The method of claim 19, And the impurity ions are n-type impurity ions including phosphorous or arsenic. The method of claim 19, And a source region formed in the semiconductor substrate parallel to the word line between the source select line and the word line. A semiconductor substrate including a drain select line, a source select line, and an upper portion formed with a plurality of word lines arranged side by side between the drain select line and the source select line; A first drain region formed by implanting impurity ions into the semiconductor substrate adjacent to the word line between the drain select line and the word line; And And a second drain region formed by implanting the impurity ions into the semiconductor substrate between the drain select line and the word line, wherein the impurity ions have a higher second drain region than the first drain region. Junction area. The method of claim 22, And the impurity ions are n-type impurity ions including phosphorous or arsenic. The method of claim 22, And a source region formed in the semiconductor substrate parallel to the word line between the source select line and the word line.

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