CN105206672B

CN105206672B - Metal oxide semiconductor field effect transistor device

Info

Publication number: CN105206672B
Application number: CN201510351040.5A
Authority: CN
Inventors: 李在训; 朱绿泫; 梁亨模; 张盛壹; 李赞镐
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2014-06-20
Filing date: 2015-06-23
Publication date: 2020-05-12
Anticipated expiration: 2035-06-23
Also published as: KR20150145606A; US20150372085A1; US9595582B2; CN105206672A; KR102165263B1

Abstract

A metal oxide semiconductor field effect transistor device comprising: a first active region; a first gate electrode configured to extend in a Y direction to cross the first active region and define a first source region and a first drain region; first gate contacts disposed on the first gate electrodes to be arranged on first dummy gate passing lines extending in the Y direction; a first source contact disposed on the first source region to be arranged on a first dummy source pass-line extending in the Y direction; and first drain contacts disposed on the first drain regions to be arranged on first imaginary drain pass-lines extending in the Y-direction, wherein at least one of the first drain contacts is disposed on any one of first imaginary X-lines configured to pass between the first source contacts and to extend in parallel in an X-direction perpendicular to the Y-direction.

Description

Metal oxide semiconductor field effect transistor device

Technical Field

Embodiments of the inventive concepts relate to the layout and vertical structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.

Background

As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices decrease in size, the effects of parasitic capacitance between closely spaced contacts increase during operation of the MOSFET device.

Disclosure of Invention

Embodiments of the inventive concept provide a layout of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.

Other embodiments of the inventive concept provide vertical structures for MOSFET devices.

The technical objects of the inventive concept are not limited to the above disclosure; other objects will become apparent to those skilled in the art based on the following description.

According to an aspect of the inventive concept, a MOSFET device having a layout may include: a first active region; a first gate electrode extending in the Y direction to cross the first active region and defining a first source region and a first drain region in the first active region; a first gate contact on the first gate electrode and arranged on a first dummy gate pass-through line extending in the Y direction; a first source contact located on the first source region and arranged on a first dummy source pass-line extending in the Y direction; and a first drain contact located on the first drain region and arranged on a first dummy drain pass line extending in the Y direction. At least one of the first drain contacts is located on any one of first imaginary lines that extend in parallel in an X-direction and each pass between two adjacent ones of the first source contacts, wherein the X-direction is perpendicular to the Y-direction.

In an embodiment, the MOSFET device may further include: a second active region adjacent to the first active region; a second gate electrode extending in the Y direction to cross the second active region and define a second source region and a second drain region in the second active region; a second gate contact on the second gate electrode and arranged on a second dummy gate pass-through line extending in the Y direction; a second source contact located on the second source region and arranged on a second dummy source pass-line extending in the Y direction; and a second drain contact on the second drain region and arranged on a second dummy drain pass line extending in the Y direction. At least one of the second drain contacts may be located on any one of the second imaginary lines.

According to another aspect of the inventive concept, a MOSFET device includes: an active region; a gate electrode extending in a Y direction to cross the active region and defining a source region and a drain region in the active region; a source contact extending in a Y direction on the source region; and a drain contact extending in the Y direction on the drain region.

According to still another aspect of the inventive concept, a MOSFET device may include: an active region; a gate electrode extending in a Y direction to cross the active region and defining a source region and a drain region; a gate contact on the gate electrode; and a first drain contact on the drain region.

According to still another aspect of the inventive concept, a MOSFET device may include: an active region; first to third gate electrodes extending in the Y direction to cross the active region and define a first source region, a first drain region, a second source region, and a second drain region; a first source contact in the first source region and a second source contact in the second source region; and a first drain contact in the first drain region and a second drain contact in the second drain region.

According to still another aspect of the inventive concept, a MOSFET device may include: an active region; a gate electrode extending in a Y direction to cross the active region and defining a source region and a drain region; gate contacts on the gate electrode to be arranged in a Y direction; source contacts on the source region to be arranged in the Y direction; and a drain contact on the drain region to be arranged in a Y direction, wherein the gate contact may be aligned with any one of the source contact and the drain contact in an X direction perpendicular to the Y direction.

According to still another aspect of the inventive concept, a MOSFET device may include: a first active region; a first gate electrode extending in the Y direction to cross the first active region, the first gate electrode defining a first source region and a first drain region in the first active region; a first gate contact on the first gate electrode, the first gate contact being arranged on a first dummy gate pass-through line extending in the Y direction; a first source contact on the first source region, the first source contact being arranged on a first dummy source pass-line extending in the Y direction; and a first drain contact on the first drain region, the first drain contact being arranged on a first dummy drain pass line extending in the Y direction. The distances from one of the gate contacts to the two source contacts closest to the one of the gate contacts are substantially the same.

According to still another aspect of the inventive concept, a MOSFET device may include: a first active region; a first gate electrode extending in the Y direction to cross the first active region, the first gate electrode defining a first source region and a first drain region in the first active region; a first gate contact on the first gate electrode, the first gate contact being arranged on a first dummy gate pass-through line extending in the Y direction; a first source contact on the first source region, the first source contact being arranged on a first dummy source pass-line extending in the Y direction; and a first drain contact on the first drain region, the first drain contact being arranged on a first dummy drain pass line extending in the Y direction. At least some of the first source contacts are aligned with a respective one of the first drain contacts in an X-direction perpendicular to the Y-direction, wherein the first gate contact is not aligned with either the first source contact or the first drain contact in the X-direction.

Details of other embodiments are included in the detailed description and the accompanying drawings.

Drawings

The foregoing and other features and advantages of the inventive concept will be apparent from the following more particular description of preferred embodiments of the inventive concept as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:

fig. 1A to 1L are layout views illustrating a MOSFET device according to various embodiments of the inventive concept;

fig. 2A to 2J are layout views of a MOSFET device according to further embodiments of the inventive concept;

fig. 3A is a layout view of a MOSFET device according to another embodiment of the inventive concept, and fig. 3B to 3D are conceptual vertical sectional views taken along lines I-I ', II-II ', and III-III ' of fig. 3A, respectively;

fig. 4A to 4E are layout views of a MOSFET according to additional embodiments of the inventive concept;

fig. 5A is a conceptual view illustrating a semiconductor module according to an embodiment of the inventive concept;

fig. 5B and 5C are conceptual block diagrams illustrating an electronic system according to an embodiment of the inventive concept.

Detailed Description

In the following description, embodiments of the present invention are described mainly with reference to a "layout" which refers to a plan view of devices or, in other words, a view looking down from above towards the top surface of the substrate of the devices along an axis perpendicular to the top surface of the substrate. The device is also described by the terms "X-direction" and "Y-direction", which are directions parallel to the top surface of the substrate and perpendicular to each other. In the following description, to facilitate understanding of the inventive concept, -the Y direction means a downward direction in the drawings (i.e., toward the bottom of the drawing sheet), and the + Y direction means an upward direction. In the following description, two elements are "vertically stacked" if an axis perpendicular to the top surface of the substrate passes through the two elements.

In one aspect of the inventive concept, the MOSFET device can have a symmetrical shape, structure, and characteristics. For example, the source and the drain may be compatible with each other in embodiments of the inventive concept. Thus, the location and characteristics of the source contact may be compatible with the location and characteristics of the drain contact.

Fig. 1A to 1L are layout views illustrating MOSFET devices according to various embodiments of the inventive concept.

Referring to fig. 1A, a MOSFET device according to an embodiment of the inventive concept includes an active region 10, a gate electrode 23 extending in a Y direction to cross the active region 10, a source region 15 and a drain region 16 defined by the gate electrode 23, a plurality of gate contacts 31 vertically stacked with the gate electrode 23, a plurality of source contacts 35 vertically stacked with the source region 15, and a plurality of drain contacts 36 vertically stacked with the drain region 16. The MOSFET device can include a gate interconnect 41 vertically stacked with the gate electrode 23 and the gate contact 31, a source interconnect 45 vertically stacked with the source region 15 and the source contact 35, and a drain interconnect 46 vertically stacked with the drain region 16 and the drain contact 36. A portion of the active region 10 vertically overlapping the gate electrode 23 may be the channel region 11.

The active region 10 may have a shape of, for example, a quadrangle.

The gate electrode 23 may have a stripe shape or a line shape extending in the Y direction to cross the middle portion of the active region 10.

The source region 15 may be a portion of the active region 10 on a first side of the gate electrode 23, and the drain region 16 may be another portion of the active region 10 on a second side of the gate electrode 23 opposite the first side. The source region 15 and the drain region 16 may be symmetrically disposed about a line that bisects the gate electrode 23 in the Y direction. For example, the source region 15 and the drain region 16 may have substantially the same shape and area. The source region 15 and the drain region 16 may have a shape elongated in the Y direction.

The gate contact 31, the source contact 35, and the drain contact 36 may be disposed on a dummy gate through line Yg, a dummy source through line Ys, and a dummy drain through line Yd, which all extend in the Y direction, respectively. For example, a dummy gate through line Yg may pass through the gate electrode 23 and the channel region 11 in the Y direction, a dummy source through line Ys may pass through the source region 15 in the Y direction, and a dummy drain through line Yd may pass through the drain region 16 in the Y direction. As shown in fig. 1A, the virtual through lines Yg, Ys, and Yd may substantially cross the centers of the gate contact 31, the source contact 35, and the drain contact 36, respectively.

The source contact 35 and the drain contact 36 may be disposed on a virtual source/drain contact intersection line Xsd extending parallel to each other in the X direction. For example, one of the source contacts 35 and one of the drain contacts 36 may each be disposed on one of the dummy source/drain contact intersection lines Xsd.

The source contact 35 and the drain contact 36 may be symmetrically disposed about a line that bisects the gate electrode 23 in the Y direction. For example, the distance between each source contact 35 and the gate electrode 23 may be the same as the distance between each drain contact 36 and the gate electrode 23.

The gate contact 31 is not disposed on the dummy source/drain contact intersection line Xsd. Conversely, the gate contacts 31 may be disposed on each of the dummy gate contact intersection lines Xg extending parallel to each other in the X direction. Each dummy gate contact intersection line Xg may be offset in the-Y direction (or + Y direction) from the dummy source/drain contact intersection line Xsd. For example, each dummy gate contact intersection line Xg may pass between two adjacent ones of the source contacts 35 and/or between two adjacent ones of the drain contacts 36. Therefore, the gate contact 31 may not be aligned with the source contact 35 or the drain contact 36 in the X direction.

The gate contacts 31 may each be spaced apart from the two source contacts 35 that are closest to each other by substantially the same distance, and may be spaced apart from the two drain contacts 36 that are closest to each other by substantially the same distance.

The gate contact 31, the source contact 35, and the drain contact 36 may be substantially the same size.

The gate contact 31 and the source contact 35 may be disposed in a zigzag pattern in both the X-direction and the Y-direction. Likewise, the gate contact 31 and the drain contact 36 may be disposed in a zigzag pattern in both the X-direction and the Y-direction.

The gate interconnect 41, the source interconnect 45, and the drain interconnect 46 may extend parallel to each other along a dummy gate through line Yg, a dummy source through line Ys, and a dummy drain through line Yd, respectively. The gate interconnection 41 may extend in parallel with the gate electrode 23 and may overlap the gate electrode 23. The source interconnect 45 may extend parallel to the source region 15 and may overlap the source region 15. The drain interconnect 46 may extend parallel to the drain region 16 and may overlap the drain region 16.

Since the MOSFET device of fig. 1A includes the gate contact 31, the source contact 35, and the drain contact 36 arranged in a zigzag pattern in both the X-direction and the Y-direction, the minimum distance between the gate contact 31 and the source contact 35 and the minimum distance between the gate contact 31 and the drain contact 36 can be increased. Accordingly, parasitic capacitance between the

contacts

31, 35, and 36 may be reduced, the length of the

contacts

31, 35, and 36 in the X direction may be increased, and/or a process margin for forming the

contacts

31, 35, and 36 may be increased.

Referring to fig. 1B, in a MOSFET device according to another embodiment of the inventive concept, the drain contact 36 of the embodiment of fig. 1A disposed on a dummy inter-gate-contact line Xgi extending in the X direction and passing between two adjacent gate contacts 31 is omitted. The virtual inter-gate contact line Xgi may traverse at a midpoint between two adjacent gate contacts 31.

In the embodiment of fig. 1B, the total number of drain contacts 36 may be less than the total number of source contacts 35, which may be the total number of gaps between adjacent gate contacts 31. The number of omitted drain contacts 36 may be the number of gaps between adjacent gate contacts 31. The total number of gaps between adjacent gate contacts 31 may be one less than the total number of gate contacts 31. In the embodiment of fig. 1B, the parasitic capacitance between the gate contact 31 and the drain contact 36 may be further reduced.

Referring to fig. 1C, in a MOSFET device according to still another embodiment of the inventive concept, the drain contact 36 may be disposed only in a lower portion of the drain region 16 in the Y direction.

For example, the drain contact 36 may be provided only in a lower portion of the drain region 16 at a height lower than all of the dummy gate contact intersection lines Xg extending in the X direction to intersect the gate contact 31. In other words, the drain contact 36 may be located in the-Y direction with respect to the gate contact 31. Further, a dummy drain contact intersection line Xd extending in the X direction to intersect the drain contact 36 may be provided at a lower height than the dummy gate contact intersection line Xg, and thus may be located in the-Y direction with respect to the dummy gate contact intersection line Xg.

The total number of drain contacts 36 may be less than the total number of source contacts 35, and the less number may be the total number of gate contacts 31. The parasitic capacitance between the gate contact 31 and the drain contact 36 can be further reduced.

Referring to fig. 1D, in a MOSFET device according to still another embodiment of the inventive concept, the drain contact 36 disposed in the lower region of the drain region 16 may have a stripe shape or a rectangular shape elongated in the Y direction, compared to the drain contact 36 in the embodiment of fig. 1A to 1C.

For example, the MOSFET device of fig. 1D may include different numbers of source contacts 35 and drain contacts 36. The source contact 35 may have a square or circular shape, and the drain contact 36 may have a bar shape, a rectangular shape, or an oval shape. The strip, rectangular or oval shaped drain contact 36 may have a reduced resistance.

Referring to fig. 1E, in a MOSFET device according to still another embodiment of the inventive concept, each gate contact 31 may be disposed on a first dummy gate contact intersection line Xg1 and on a second dummy gate contact intersection line Xg2, where Xg1 extends in the X direction to pass between two adjacent source contacts 35 and between two adjacent drain contacts 36, and the second dummy gate contact intersection line Xg2 is parallel to the first dummy gate contact intersection line Xg1 and is offset in the + Y direction from at least one of the source contacts 35 and/or at least one of the drain contacts 36. Therefore, the gate contact 31 may be offset in the + Y direction so as not to be disposed on the same virtual source/drain contact intersection line Xsd in the X direction with the source contact 35 and/or the drain contact 36.

The gate contact 31 and the source contact 35 may be disposed in a zigzag pattern in the X-direction and/or the Y-direction. The gate contact 31 and the drain contact 36 may also be arranged in a zigzag pattern in the X-direction and/or the Y-direction.

Referring to fig. 1F, in a MOSFET device according to another embodiment of the inventive concept, the drain contact 36 is not disposed on a virtual inter-gate-contact line Xgi extending in the X direction to pass between two adjacent gate contacts 31.

For example, in the embodiment of fig. 1F, the drain contact 36 disposed on the virtual inter-gate-contact line Xgi extending in the X-direction to cross between two adjacent gate contacts 31 in the embodiment of fig. 1E is omitted.

Referring to fig. 1G, a MOSFET device according to still another embodiment of the inventive concept may include: a gate electrode 23 crossing the active region 10 to define a source region 15 and a drain region 16; a plurality of gate contacts 31 disposed on the gate electrode 23 to overlap the gate electrode 23; a plurality of source contacts 35 disposed on the source region 15 to overlap the source region 15; a plurality of drain contacts 36 disposed on the drain region 16 to overlap the drain region 16; a gate interconnect 41 extending in parallel with the gate electrode 23 to overlap the gate electrode 23 and the gate contact 31; a source interconnection 45 extending in parallel with the gate electrode 23 to overlap the source region 15 and the source contact 35; and a drain interconnection 46 extending in parallel with the gate electrode 23 to overlap the drain region 16 and the drain contact 36. The gate contact 31 may be aligned with a virtual gate/source contact intersection line Xgs extending in the X direction to intersect the source contact 35 and disposed on a virtual gate/source contact intersection line Xgs, and the drain contact 36 may be disposed on a virtual drain contact intersection line Xd extending in the X direction to cross between two adjacent source contacts 35.

For example, the drain contacts 36 may each be offset in the-Y direction relative to the self source contact 35 such that the drain contact 36 is not disposed on the virtual gate/source contact intersection Xgs and/or the virtual source contact intersection Xs. Thus, the drain contact 36 is not aligned in the X-direction with the source contact 35 and/or the gate contact 31. The drain contacts 36 may be aligned in the X-direction with spaces between the gate contacts 31 and/or spaces between the source contacts 35.

Each gate contact 31 may be disposed on a virtual gate/source contact intersection line Xgs in the X-direction and a virtual gate crossing line Yg in the Y-direction. The source contact 35 may be disposed on a virtual gate/source contact intersection line Xgs and/or a virtual source contact intersection line Xs in the X direction and a virtual source crossing line Ys in the Y direction. The source contact 35 and the drain contact 36 and/or the gate contact 31 and the drain contact 36 may be arranged in a zigzag pattern in the X-direction and/or the Y-direction.

When the source contact 35 is grounded through a ground voltage, the parasitic capacitance between the gate contact 31 and the source contact 35 may be negligibly low. Therefore, when the source contact 35 is grounded by the ground voltage, only the distance between the gate contact 31 and the drain contact 36 may be adjusted.

Referring to fig. 1H, in a MOSFET device according to further embodiments of the inventive concepts, the drain contact 36 disposed on the virtual inter-gate-contact line Xgi crossing between the gate contacts 31 in the X direction in the embodiment of fig. 1G is omitted. Accordingly, the drain contact 36 may be disposed only in a lower portion of the drain region 16 that is positioned in the-Y direction with respect to the lowermost one of the gate contacts 31.

Referring to fig. 1I, in a MOSFET device according to still another additional embodiment of the inventive concept, the gate contact 31, the source contact 35, and the drain contact 36 may each be disposed on a plurality of dummy gate/source contact intersection lines Xsg and/or a plurality of dummy source/drain contact intersection lines Xsd extending in parallel in the X direction.

The drain contact 36 may not be disposed on the dummy gate/source contact intersection line Xsg extending in the X direction to intersect the gate contact 31. The gate contact 31 may not be disposed on the dummy source/drain contact intersection line Xsd extending in the X direction to intersect the source contact 35 and the drain contact 36. For example, only one of the gate contact 31 and the drain contact 36 may be disposed exclusively on the virtual gate/source contact intersection Xsg and/or the virtual source/drain contact intersection Xsd. Accordingly, the drain contact 36 may be disposed only in a lower portion of the drain region 16 that is positioned in the-Y direction with respect to the lowermost one of the gate contacts 31.

Referring to fig. 1J, in a MOSFET device according to still another embodiment of the inventive concept, the drain contact 36 disposed in a lower portion of the drain region 16 positioned in the-Y direction with respect to a lowermost gate contact 31 of the gate contacts 31 may have a bar shape, a rectangular shape, or an elliptical shape.

Referring to fig. 1K, a MOSFET device according to still another embodiment of the inventive concept may include: a gate electrode 23 crossing the active region 10 to define a source region 15 and a drain region 16; a plurality of gate contacts 31 disposed on the gate electrode 23 to overlap the gate electrode 23; a plurality of source contacts 35 disposed on the source region 15 to overlap the source region 15; a plurality of drain contacts 36 disposed on the drain region 16 to overlap the drain region 16; a gate interconnect 41 extending in parallel with the gate electrode 23 to overlap the gate electrode 23 and the gate contact 31; a source interconnection 45 extending in parallel with the gate electrode 23 to overlap the source region 15 and the source contact 35; and a drain interconnection 46 extending in parallel with the gate electrode 23 to overlap the drain region 16 and the drain contact 36. The source contact 35 and the drain contact 36 may be disposed on a virtual source/drain contact intersection line Xsd extending in the X direction.

One source contact 35 and one drain contact 36 may be commonly disposed on each of the dummy source/drain contact intersection lines Xsd.

The gate contact 31 may not be aligned in the X-direction with the source contact 35 and/or the drain contact 36.

The source contact 35 and the drain contact 36 may be disposed only in the Y direction in portions of the source region 15 and the drain region 16 that are positioned in the-Y direction with respect to the lowermost gate contact 31. For example, the gate contact 31 may be disposed in an upper portion of the active region 10, and the source contact 35 and the drain contact 36 may be disposed in a lower portion of the active region 10.

The dummy source/drain contact intersection line Xsd intersecting the source contact 35 and the drain contact 36 and the dummy gate contact intersection line Xg intersecting the gate contact 31 may be disposed parallel to each other and may extend in the X direction. The dummy source/drain contact intersection line Xsd and the dummy gate contact intersection line Xg may be separated from the adjacent dummy source/drain contact intersection line Xsd and/or the adjacent dummy gate contact intersection line Xg by the same distance in the Y direction.

The total number of source contacts 35 and the total number of drain contacts 36 may be the same.

Referring to fig. 1L, in a MOSFET device according to another embodiment of the inventive concept, the source contact 35 disposed in the lower region of the source region 15 and the drain contact 36 disposed in the lower region of the drain region 16 may have a stripe shape, a rectangular shape, or an elliptical shape.

Fig. 2A to 2J are layout views illustrating MOSFET devices according to various embodiments of the inventive concept.

Referring to fig. 2A, the MOSFET device according to an embodiment of the inventive concept may include a first MOSFET device 5a and a second MOSFET device 5 b.

The first MOSFET device 5a may include: a first active region 10 a; a first gate electrode 23a crossing the first active region 10a in the Y direction to define a first source region 15a and a first drain region 16 a; a first source contact 35a disposed on the first source region 15 a; a first drain contact 36a disposed on the first drain region 16 a; and a first gate contact 31a disposed on the first gate electrode 23 a. The first MOSFET device 5a may further include: a first gate interconnection 41a vertically overlapped with the first gate electrode 23a and the first gate contact 31 a; a first source interconnection 45a vertically overlapped with the first source region 15a and the first source contact 35 a; and a first drain interconnect 46a vertically stacked with the first drain region 16a and the first drain contact 36 a.

The second MOSFET device 5b may include: a second active region 10 b; a second gate electrode 23b crossing the second active region 10b in the Y direction to define a second source region 15b and a second drain region 16 b; a second source contact 35b disposed on the second source region 15 b; a second drain contact 36b disposed on the second drain region 16 b; and a second gate contact 31b disposed on the second gate electrode 23 b. The second MOSFET device 5b may further include: a second gate interconnection 41b vertically overlapped with the second gate electrode 23b and the second gate contact 31 b; a second source interconnection 45b vertically stacked with the second source region 15b and the second source contact 35 b; and a second drain interconnect 46b vertically stacked with the second drain region 16b and the second drain contact 36 b.

The first gate electrode 23a and the second gate electrode 23b may be disposed parallel to each other.

The first gate contact 31a may be disposed on a first dummy gate through line Yg1 extending in the Y direction. The first source contact 35a may be disposed on a first dummy source passing line Ys1 extending in the Y direction. The first drain contact 36a may be disposed on a first dummy drain passing line Yd1 extending in the Y direction. The second gate contact 31b may be disposed on a second dummy gate through line Yg2 extending in the Y direction. The second source contact 35b may be disposed on a second dummy source passing line Ys2 extending in the Y direction. The second drain contact 36b may be disposed on a second dummy drain passing line Yd2 extending in the Y direction.

The first source contact 35a and the first gate contact 31a may be both disposed on a first virtual gate/source contact intersection Xgs1 and/or a first virtual source contact intersection Xs1, each extending in the X-direction.

The first drain contact 36a may be disposed on a first virtual drain contact intersection line Xd1 that traverses between two adjacent first source contacts 35a and/or between two adjacent first gate contacts 31 a. The first dummy drain contact intersection lines Xd1 each extend in the X direction.

The second source contact 35b, the second gate contact 31b and the second drain contact 36b may be disposed on a second virtual gate/source/drain contact intersection Xgsd2 and/or a second virtual source/drain contact intersection Xsd2, each extending in the X-direction.

A first dummy gate/source contact intersection line Xgs1 extends in the X direction to intersect the first gate contact 31a, and a second dummy gate/source/drain contact intersection line Xgsd2 extends in the X direction to intersect the second gate contact 31 b. Each first virtual gate/source contact intersection Xgs1 may be substantially aligned in the X-direction (horizontally) with respect to a respective one of the second virtual gate/source/drain contact intersections Xgsd 2. For example, the uppermost (in the + Y direction) first gate contact 31a is disposed on a first virtual gate/source contact intersection line Xgs1, and the uppermost second gate contact 31b is disposed on a second virtual gate/source/drain contact intersection line Xgsd2 that is collinear with the first virtual gate/source contact intersection line Xgs 1.

The first drain contacts 36a may be disposed on first dummy drain contact intersection lines Xd1 each extending in the X direction to cross between two adjacent second source contacts 35 b. The second source contact 35b may be disposed on a second dummy gate/source/drain contact intersection line Xgsd2 and/or a second dummy source/drain contact intersection line Xsd2 each extending in the X direction to cross between two adjacent first drain contacts 36 a. The first drain contact 36a and the second source contact 35b may be disposed exclusively on the first dummy drain contact intersection line Xd1 and the second dummy source/drain contact intersection line Xsd2, respectively, each extending in the X direction. As shown in fig. 2A, the first drain contact 36a and the second source contact 35b may be disposed in a zigzag pattern in the Y-direction.

The first gate interconnect 41a, the first source interconnect 45a, the first drain interconnect 46a, the second gate interconnect 41b, the second source interconnect 45b, and the second drain interconnect 46b may extend parallel to one another along virtual straight lines Yg1, Ys1, Yd1, Yg2, Ys2, and Yd2, respectively, each extending in the Y-direction. The first gate interconnect 41a may be parallel to the first gate electrode 23a and may vertically overlap the first gate electrode 23 a. The second gate interconnection 41b may be parallel to the second gate electrode 23b and may vertically overlap the second gate electrode 23 b. The first source interconnect 45a may be parallel to the first source region 15a and may vertically overlap the first source region 15 a. The second source interconnect 45b may be parallel to the second source region 15b and may vertically overlap the second source region 15 b. The first drain interconnect 46a may be parallel to the first drain region 16a and may vertically overlap the first drain region 16 a. The second drain interconnect 46b may be parallel to the second drain region 16b and may vertically overlap the second drain region 16 b.

Referring to fig. 2B, in a MOSFET device according to another embodiment of the inventive concept, the MOSFET device of fig. 2A is modified such that the first drain contacts 36a are each positioned at a lower height in the first drain region 16a than the lowermost first gate contact 31a among the first gate contacts 31 a.

For example, the first drain contact 36a is not provided on the first virtual inter-gate-contact line Xgi1 that extends in the X direction to cross between two adjacent first gate contacts 31 a.

Referring to fig. 2C, in a MOSFET device according to another embodiment of the inventive concept, the first drain contact 36a may be positioned at a lower height than the lowermost first gate contact 31a among the first gate contacts 31a, and may have a bar shape, a rectangular shape, or an elliptical shape.

Referring to fig. 2D, in a MOSFET device according to still another embodiment of the inventive concept, unlike the embodiment of fig. 2B, the second drain contact 36B may be disposed at a lower height in the second drain region 16B than the lowermost second gate contact 31B among the second gate contacts 31B. Specifically, in the embodiment of fig. 2D, the second drain contacts 36b are not disposed on the second dummy source/gate contact intersection lines Xsg2 extending in the X direction to intersect the respective second source contacts 35b and the respective second gate contacts 31 b.

Referring to fig. 2E, in a MOSFET device according to still another embodiment of the inventive concept, the second drain contacts 36b may be positioned at a lower height than the lowermost second gate contact 31b among the second gate contacts 31b as in the embodiment of fig. 2D, and may also have a bar shape, a rectangular shape, or an oval shape.

Referring to fig. 2F, in a MOSFET device according to still another embodiment of the inventive concept, the MOSFET device of fig. 2B may be modified such that the second gate contact 31B is not disposed on a second dummy source/drain contact intersection line Xsd2 each extending in the X direction to intersect the respective second source contact 35B and second drain contact 36B. In contrast, the second gate contact 31b may be disposed on a second virtual gate contact intersection line Xg2 extending in the X direction to cross between two adjacent second source contacts 35b and/or between two adjacent second drain contacts 36 b. In other words, the second gate contact 31b may be offset in the-Y direction compared to the first gate contact 31a, the second source contact 35b, or the second drain contact 36 b.

Referring to fig. 2G, in a MOSFET device according to another embodiment of the inventive concept, the first drain contact 36a may be disposed at a lower height in the first drain region 16a than the lowermost first gate contact 31a among the first gate contacts 31 a. For example, the first drain contact 36a may not be disposed on the first virtual inter-gate-contact line Xgi1 extending in the X direction to cross between two adjacent first source contacts 35a and two adjacent first gate contacts 31 a.

Referring to fig. 2H, in a MOSFET device according to still another embodiment of the inventive concept, the first drain contact 36a of the embodiment of fig. 2G may be replaced with a drain contact 36a having a bar shape, a rectangular shape, or an elliptical shape.

Referring to fig. 2I, a MOSFET device according to another embodiment of the inventive concept may include a first MOSFET device 5a, wherein the first MOSFET device 5a includes: a first active region 10 a; a first gate electrode 23a crossing the first active region 10a in the Y direction to define a first source region 15a and a first drain region 16 a; a first source contact 35a disposed on the first source region 15 a; a first drain contact 36a disposed on the first drain region 16 a; a first gate contact 31a disposed on the first gate electrode 23 a; a first gate interconnect 41a extending in the Y direction in parallel with the first gate electrode 23a to vertically overlap the first gate electrode 23a and the first gate contact 31 a; a first source interconnection 45a extending in the Y direction in parallel with the first gate electrode 23a to vertically overlap the first source region 15a and the first source contact 35 a; and a first drain interconnection 46a extending in the Y direction in parallel with the first gate electrode 23a to vertically overlap the first drain region 16a and the first drain contact 36 a. The MOSFET device further comprises a second MOSFET device 5b, wherein said second MOSFET device 5b comprises: a second active region 10 b; a second gate electrode 23b crossing the second active region 10b in the Y direction to define a second source region 15b and a second drain region 16 b; a second source contact 35b disposed on the second source region 15 b; a second drain contact 36b disposed on the second drain region 16 b; a second gate contact 31b disposed on the second gate electrode 23 b; a second gate interconnection 41b extending in the Y direction in parallel with the second gate electrode 23b to vertically overlap the second gate electrode 23b and the second gate contact 31 b; a second source interconnection 45b extending in the Y direction in parallel with the second gate electrode 23b to vertically overlap the second source region 15b and the second source contact 35 b; and a second drain interconnection 46b extending in the Y direction in parallel with the second gate electrode 23b to vertically overlap the second drain region 16b and the second drain contact 36 b.

For example, the first source contact 35a and the first gate contact 31a may be arranged in a zigzag pattern in the X-direction and/or the Y-direction.

The first drain contact 36a may be disposed in the first drain region 16a at a lower height than the lowermost first gate contact 31a among the first gate contacts 31 a. The first drain contact 36a may be disposed on a first imaginary upper drain contact intersection line Xd1a extending in the X direction to cross between two adjacent first source contacts 35a, or on a first imaginary lower drain contact intersection line Xd1b offset in the-Y direction from a first imaginary source contact intersection line Xs 1.

The second gate contacts 31b may be disposed on second dummy gate contact intersection lines Xg2 each extending in the X direction to cross between two adjacent second source contacts 35 b. Accordingly, the second source contact 35b and the second gate contact 31b may be disposed in a zigzag pattern in the X-direction and/or the Y-direction.

The second drain contact 36b may be disposed at a lower height in the second drain region 16b than the lowermost second gate contact 31b among the second gate contacts 31 b. The second drain contact 36b may be disposed on a second imaginary upper drain contact intersection line Xd2a crossing between two adjacent second source contacts 35b, or on a second imaginary lower drain contact intersection line Xd2b shifted in the-Y direction from the second imaginary source contact intersection line Xs 2. The second dummy source contact intersection line Xs2 extends in the X direction to cross the lowermost second source contact 35b among the second source contacts 35 b.

Referring to fig. 2J, in a MOSFET device according to still another embodiment of the inventive concept, the MOSFET device of fig. 2I may be modified such that the first and

second drain contacts

36a and 36b may have a bar shape, a rectangular shape, or an elliptical shape.

Fig. 3A is a schematic layout illustrating a MOSFET device according to an embodiment of the inventive concept, and fig. 3B to 3D are conceptual vertical sectional views taken along lines I-I ', II-II ', and III-III ' of fig. 3A, respectively.

Referring to fig. 3A, the semiconductor device according to the present embodiment of the inventive concept may include a cell area CA and a peripheral area PA.

The vertical channels 160, the lower line contacts 171, the bit line pads 173, the upper line contacts 175, and the bit lines 177 may be formed in the cell area CA. The vertical channels 160 and the lower line contacts 171 may have a rectangular shape or a circular shape. The bit line pad 173 may have an elongated bar shape, a rectangular shape, or an oval shape. The bit lines 177 may have a straight line shape and may extend in two directions.

The MOSFET device 5 and the logic circuit 7 may be formed in the peripheral area PA.

The MOSFET device 5 may include: an active region 110; a gate electrode 123 crossing the active region 110 to define a source region 115 and a drain region 116; a gate contact 131 disposed on the gate electrode 123; a source contact 135 disposed on the source region 115; a drain contact 136 disposed on the drain region 116; a gate interconnection 141 vertically overlapped with the gate contact 131 and the gate electrode 123; a source interconnect 145 vertically overlapping the source contact 135 and the source region 115; and a drain interconnect 146 vertically stacked with the drain contact 136 and the drain region 116. The MOSFET device 5 may be one of the MOSFET devices described in fig. 1A to 1L. To simplify the discussion, MOSFET device 5 is described for simplicity as including one gate contact 131, one source contact 135, and one drain contact 136.

The logic circuit 7 may include: a gate input/output contact 181 disposed on the gate interconnect 141, a gate input/output interconnect 191 vertically overlapping the gate input/output contact 181, a source input/output contact 185 disposed on the source interconnect 145, a source input/output interconnect 195 vertically overlapping the source input/output contact 185, a drain input/output contact 186 disposed on the drain interconnect 146, and a drain input/output interconnect 196 vertically overlapping the drain input/output contact 186.

Although the bit lines 177 are shown in fig. 3A as being parallel to the gate interconnects 141, the source interconnects 145, the drain interconnects 146, the gate input/output interconnects 191, the source input/output interconnects 195, and the drain input/output interconnects 196, this is not a limitation.

Referring to fig. 3B, the MOSFET device 5 may include: a lower insulating layer 151 formed on the substrate 100; word line electrodes 153 and interlayer insulating layers 155 alternately stacked on the lower insulating layers 151; a cover insulating layer 157 covering the word line electrode 153 and the interlayer insulating layer 155; and a vertical channel 160 penetrating the capping insulating layer 157, the word line electrode 153, the interlayer insulating layer 155, and the lower insulating layer 151 to contact the substrate 100. The MOSFET device 5 further includes a lower bit line contact 171, a bit line pad 173, an upper bit line contact 175, and a bit line 177 formed on the vertical channel 160.

The substrate 100 may include a semiconductor wafer. For example, the substrate 100 may include a single crystal silicon wafer or a compound semiconductor wafer such as silicon germanium (SiGe).

The lower insulating layer 151 may be relatively thickly formed on the surface of the substrate 100. The lower insulating layer 151 may include an insulating material such as silicon oxide.

The word line electrodes 153 and the interlayer insulating layers 155 may be alternately stacked. The word line electrode 153 may include a conductor such as tungsten. A conductive barrier layer (not shown) such as titanium nitride (TiN) or tantalum nitride (TaN) may also be disposed between each word line electrode 153 and the adjacent interlayer insulating layer 155. The interlayer insulating layer 155 may include an insulating material such as silicon oxide.

A cover insulating layer 157 may be formed on the uppermost word line electrode 153 of the word line electrodes 153. The cover insulating layer 157 may be formed relatively thick.

The vertical channel 160 may include a lower pad layer 161, a charge storage layer 163, a channel layer 165, a core layer 167, and an upper pad layer 169. The lower pad layer 161 may include silicon that can be formed by, for example, an epitaxial growth process. The lower insulating layer 151 may have a sufficient thickness such that the lower pad layer 161 has a suitable thickness. The lower pad layer 161 may be thinner than the lower insulating layer 151. The charge storage layer 163 may include a plurality of layers such as a silicon oxide layer, a silicon nitride layer, and a metal oxide layer. The channel layer 165 may include a conductive layer such as silicon. The core layer 167 may include an insulating material such as silicon oxide. The upper pad layer 169 may include a conductive layer such as silicon. The capping insulating layer 157 may have a sufficient thickness such that the upper pad layer 169 has a suitable thickness.

The lower line contacts 171 may be vertically aligned on the upper pad layer 169 of the vertical channel layer 160 and may vertically extend from the upper pad layer 169 of the vertical channel layer 160. The lower line contacts 171 may include silicide and/or metal to electrically connect the upper pad layer 169 of the vertical channel layer 160 to the bit line pads 173.

The bit line pad 173 may extend horizontally to vertically overlap and contact the lower line contact 171. The bit line pad 173 may include a conductor such as a metal.

The upper line contact 175 may extend horizontally to vertically overlap and contact the bit line pad 173. The upper line contact 175 may include a metal.

Referring to fig. 3C, the MOSFET device 5 may include: a Shallow Trench Isolation (STI)105 defining an active region 110 in the substrate 100; a gate pattern 120 formed on the active region 110; a source region 115, a drain region 116, and a channel region 111 in the active region 110; a lower gate contact 131L and an upper gate contact 131U formed on the gate pattern 120; a lower source contact 135L and an upper source contact 135U formed on the source region 115; a lower drain contact 136L and an upper drain contact 136U formed on the drain region 116; a gate interconnection 141 formed on the upper gate contact 131U; a source interconnect 145 formed on the upper source contact 135U; and a drain interconnect 146 formed on the upper drain contact 136U.

The gate pattern 120 may include a gate insulating layer 121, a gate electrode 123, a gate capping layer 125, and a gate spacer 127. The gate insulating layer 121 may include silicon oxide or metal oxide. The gate electrode 123 may include a silicide or a metal such as tungsten. The gate capping layer 125 and the gate spacers 127 may include a relatively rigid insulating material such as silicon nitride.

The active region 110 may include a source region 115 located on one side of the gate electrode 123, a drain region 116 located on the other side of the gate electrode 123 opposite to the one side, and a channel region 111 under the gate electrode 123.

The lower gate contact 131L may be arranged on the gate pattern 120, and may vertically penetrate the gate capping layer 125 to contact the gate electrode 123. The upper gate contact 131U may be arranged on the lower gate contact 131L.

The lower source contact 135L may be arranged on the source region 115 and may contact the source region 115. Upper source contact 135U may be arranged on lower source contact 135L.

The lower drain contact 136L may be arranged on the drain region 116, and may contact the drain region 116. The upper drain contact 136U may be arranged on the lower drain contact 136L.

The lower gate contact 131L, the upper gate contact 131U, the lower source contact 135L, the upper source contact 135U, the lower drain contact 136L, and the upper drain contact 136U may include silicide and/or metal.

Lower and

upper gate contacts

131L and 131U, lower and

upper source contacts

135L and 135U, and lower and

upper drain contacts

136L and 136U may each be formed as a single body that is physically continuous.

The gate interconnect 141, the source interconnect 145, and the drain interconnect 146 can be vertically aligned with the upper gate contact 131U, the upper source contact 135U, and the upper drain contact 136U, respectively.

Referring to fig. 3D, the MOSFET device 5 may further include a gate input/output contact 181 and a gate input/output interconnect 191. The gate input/output contact 181 may be formed on an end of the gate interconnect 141 or near an end of the gate interconnect 141. The gate input/output interconnection 191 may vertically overlap and contact the gate input/output contact 181 and extend in one direction.

Referring to fig. 3A through 3D, the lower gate contact 131L, the lower source contact 135L, and the lower drain contact 136L may each have a height higher than that of the vertical channel 160.

The height of the lower line contact 171 may be higher than that of the upper gate contact 131U.

The bit line pad 173, the gate interconnect 141, the source interconnect 145, and the drain interconnect 146 may be located at the same height. Accordingly, the bit line pad 173, the gate interconnect 141, the source interconnect 145, and the drain interconnect 146 may all be formed in the same process.

The upper line contact 175, the gate input/output contact 181, the source input/output contact 185, and the drain input/output contact 186 may be located at the same height. Accordingly, the upper line contact 175, the gate input/output contact 181, the source input/output contact 185, and the drain input/output contact 186 may all be formed in the same process.

The bit lines 177, gate input/output interconnects 191, source input/output interconnects 195, and drain input/output interconnects 196 can be located at the same height. Thus, the bit line 177, the gate input/output interconnect 191, the source input/output interconnect 195, and the drain input/output interconnect 196 can all be formed in the same process.

Fig. 4A to 4E are layout views illustrating MOSFET devices according to further embodiments of the inventive concept.

Referring to fig. 4A, a MOSFET device according to another embodiment of the inventive concept may include: an active region 210; a plurality of gate electrodes 223 extending in the Y direction to cross the active regions 210 to define source and drain

regions

215 and 216; a plurality of gate contacts 231 disposed on the plurality of gate electrodes 223; a source contact 235 disposed on the source region 215; and a drain contact 236 disposed on the drain region 216. The plurality of gate electrodes 223 may be electrically and physically connected.

The source contact 235 and the drain contact 236 may be disposed on a virtual source/drain contact intersection line Xsd extending in parallel in the X direction.

The gate contacts 231 may be disposed on virtual gate contact intersection lines Xg each extending in the X direction to cross between two adjacent source contacts 235 or between two adjacent drain contacts 236. For example, the gate contact 231 may be offset in the-Y direction from the virtual source/drain contact intersection line Xsd.

The gate and

source contacts

231 and 235 and the gate and

drain contacts

231 and 236 may be arranged in a zigzag pattern in the Y-direction.

Referring to fig. 4B, a MOSFET device according to a further embodiment of the inventive concept may include: an active region 210; a plurality of gate electrodes 223 extending in the Y direction to cross the active region to define a source region 215 and a drain region 216; a plurality of gate contacts 231 disposed on the plurality of gate electrodes 223; a source contact 235 disposed on the source region 215; and a drain contact 236 disposed on the drain region 216. The source contact 235 and/or the drain contact 236 may not be disposed on the virtual inter-gate-contact line Xgi that extends in the X direction to cross between two adjacent gate contacts 231. Thus, in contrast to the embodiment of fig. 4A, the embodiment of fig. 4B may not include any source contact 235 or drain contact 236 located on a virtual inter-gate contact line Xgi, wherein the virtual inter-gate contact line Xgi extends in the X-direction to traverse between two adjacent gate contacts 231. In addition, in the embodiment of fig. 4B, some of the gate contacts 231 located in the lower region of the active region 210 in the embodiment of fig. 4A may be omitted. For example, some of the gate contacts 231 disposed in the-Y direction may be omitted.

Referring to fig. 4C, a MOSFET device according to still another embodiment of the inventive concept may include: an active region 210; a plurality of gate electrodes 223 extending in the Y direction to cross the active regions 210 to define source and drain

regions

215 and 216; a plurality of gate contacts 231 disposed on the plurality of gate electrodes 223; a source contact 235 disposed on the source region 215; and a drain contact 236 disposed on the drain region 216. The gate contact 231 may be disposed on an upper region of the active region 210 or an upper region of the gate electrode 223 in the Y direction, and the source contact 235 and the drain contact 236 may be disposed in lower regions of the source region 215 and the drain region 216 in the-Y direction.

For example, the gate contact 231 and the source contact 235 or the gate contact 231 and the drain contact 236 may be exclusively disposed on a virtual gate contact intersection line Xg and/or a virtual source/drain contact intersection line Xsd extending in the X direction.

Referring to fig. 4D, in a MOSFET device according to further embodiments of the inventive concept, the source contact 235 and/or the drain contact 236 may have a bar shape elongated in the Y direction, a rectangular shape, or an elliptical shape.

Referring to fig. 4E, in a MOSFET device according to still another additional embodiment of the inventive concept, the gate contact 231 may have a bar shape elongated in the Y direction, a rectangular shape, or an elliptical shape.

Fig. 5A is a conceptual view illustrating a semiconductor module 2200 according to an embodiment of the inventive concept. Referring to fig. 5A, the semiconductor module 2200 may include a processor 2220 and a memory device 2230 mounted on a semiconductor module substrate 2210. The processor 2220 or the storage 2230 may include at least one of MOSFET devices according to various embodiments of the inventive concept. The input/output terminal 2240 may be disposed on at least one side of the module substrate 2210.

Fig. 5B is a conceptual block diagram illustrating an electronic system 2300, according to an embodiment of the inventive concept. Referring to fig. 5B, the electronic system 2300 may include a body 2310, a display unit 2360, and an external device 2370. The body 2310 may include a microprocessor unit 2320, a power supply 2330, a function unit 2340, and/or a display controller unit 2350. The body 2310 may include a system board or motherboard and/or a case with a PCB or the like. The microprocessor unit 2320, the power supply 2330, the function unit 2340 and the display controller unit 2350 may be mounted or disposed on the upper surface of the main body 2310 or inside the main body 2310. The display unit 2360 may be disposed on an upper surface of the body 2310 or inside/outside the body 2310. The display unit 2360 may display the image processed by the display controller unit 2350. For example, the display unit 2360 may include a Liquid Crystal Display (LCD), an Active Matrix Organic Light Emitting Diode (AMOLED), or various display panels. The display unit 2360 may include a touch screen. Accordingly, the display unit 2360 may have an input/output function. The power supply 2330 may supply current or voltage to the microprocessor unit 2320, the function unit 2340, the display controller unit 2350, and the like. The power supply 2330 may include rechargeable batteries, a receptacle for a dry cell battery, or a voltage/current converter. Microprocessor unit 2320 may receive voltage from power supply 2330 to control functional unit 2340 and display unit 2360. For example, the microprocessor unit 2320 may include a CPU or an Application Processor (AP). Functional unit 2340 may include: a touch panel, volatile/nonvolatile memory, a memory card controller, a camera, a lamp, a processor that records audio and moving pictures, a radio wave antenna, a speaker, a microphone, a USB interface, or a unit having other various functions. The microprocessor unit 2320 or the functional unit 2340 may include at least one of the MOSFET devices according to an embodiment of the inventive concept.

Referring to fig. 5C, an electronic system 2400 according to a further embodiment of the inventive concept may include: a microprocessor 2414 configured to perform data communications using a bus 2420, a memory system 2412, and a user interface 2418. Microprocessor 2414 may include a CPU or an AP. The electronic system 2400 may also include RAM 2416 configured to communicate directly with the microprocessor 2414. Microprocessor 2414 and/or RAM 2416 can be housed in a single package. The user interface 2418 may be used to input data to the electronic system 2400 or to output data from the electronic system 2400. For example, the user interface 2418 may include a touch panel, a touch screen, a keyboard, a mouse, a sound detector, a Cathode Ray Tube (CRT) monitor, an LCD, an AMOLED, a Plasma Display Panel (PDP), a printer, a lamp, or various input/output devices. The storage system 2412 may store an operation code of the microprocessor 2414, data processed by the microprocessor 2414, or data received from the outside. The storage system 2412 may include a storage controller, hard disk, or Solid State Disk (SSD). The microprocessor 2414, RAM 2416, and/or memory system 2412 may include at least one of the MOSFET devices according to embodiments of the inventive concepts.

According to the MOSFET device according to various embodiments of the inventive concept, since a distance between the drain contact and the gate contact or a distance between the source contact and the gate contact is increased, a parasitic capacitance formed between the contacts can be reduced. Therefore, the operating speed of the MOSFET device can be improved, power consumption and malfunction can be reduced, and the MOSFET device can be electrically stabilized.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages. It is therefore intended to include all such modifications within the scope of the inventive concept as defined by the appended claims.

Claims

1. A metal oxide semiconductor field effect transistor device, the metal oxide semiconductor field effect transistor device comprising:

a first active region;

a first gate electrode extending in the Y direction to cross the first active region, the first gate electrode defining a first source region and a first drain region in the first active region;

a first gate contact on the first gate electrode, the first gate contact being arranged on a first dummy gate pass-through line extending in the Y direction;

a first source contact on the first source region, the first source contact being arranged on a first dummy source pass-line extending in the Y direction; and

a first drain contact on the first drain region, the first drain contact being arranged on a first dummy drain pass line extending in the Y direction,

wherein at least one of the first drain contacts is located on any one of first imaginary lines that extend in parallel along an X-direction and that each pass between two adjacent ones of the first source contacts, wherein the X-direction is perpendicular to the Y-direction,

wherein the first gate contact is disposed on a second dummy line extending in parallel in the X direction to cross the first source contact.

2. The mosfet device of claim 1, wherein the first drain contacts are not disposed on a virtual inter-gate contact line extending in the X-direction to pass between the two adjacent first gate contacts.

3. The mosfet device of claim 2, wherein a virtual inter-gate contact line crosses a midpoint of a virtual line extending between the two adjacent first gate contacts.

4. The metal oxide semiconductor field effect transistor device of claim 1, wherein the first source contact and the first drain contact are arranged in a zigzag pattern in the Y-direction.

5. The metal oxide semiconductor field effect transistor device of claim 1, wherein the first gate contact and the first drain contact are arranged in a zigzag pattern in the Y-direction.

6. The metal oxide semiconductor field effect transistor device of claim 1, wherein a distance between one of the first drain contacts and the two first source contacts closest to the one of the first drain contacts is substantially the same.

7. The metal oxide semiconductor field effect transistor device of claim 1, wherein the first drain contact is located at a height in the Y-direction that is lower than a height of the first gate contact.

8. The metal oxide semiconductor field effect transistor device of claim 7, wherein the first drain contact has a stripe shape or an oval shape in a top view.

9. The metal oxide semiconductor field effect transistor device of claim 8, wherein the first drain contact has a rectangular shape in a top view.

10. The metal oxide semiconductor field effect transistor device of claim 1, further comprising:

a second active region adjacent to the first active region;

a second gate electrode extending in the Y direction to cross the second active region, the second gate electrode defining a second source region and a second drain region in the second active region;

a second gate contact on the second gate electrode, the second gate contact being arranged on a second dummy gate passing line extending in the Y direction;

a second source contact on the second source region, the second source contact being arranged on a second dummy source pass-line extending in the Y direction; and

a second drain contact on the second drain region, the second drain contact being arranged on a second dummy drain pass line extending in the Y direction,

wherein at least one of the second drain contacts is located on any one of the second imaginary lines.

11. The metal oxide semiconductor field effect transistor device of claim 10, wherein the first drain region is adjacent to the second source region.

12. The mosfet device of claim 10, wherein the first drain contact and the second source contact are arranged in a zigzag pattern in the Y-direction.

13. The metal oxide semiconductor field effect transistor device of claim 10, wherein the first source region, the first drain region, the second source region, and the second drain region are substantially the same size.

14. The metal oxide semiconductor field effect transistor device of claim 10, wherein a distance between the first source contact and the first gate electrode, a distance between the first drain contact and the first gate electrode, a distance between the second source contact and the second gate electrode, and a distance between the second drain contact and the second gate electrode are substantially the same.

15. A metal oxide semiconductor field effect transistor device, the metal oxide semiconductor field effect transistor device comprising:

a first active region;

wherein at least some of the first source contacts are aligned with a respective one of the first drain contacts in an X-direction perpendicular to the Y-direction, and the first gate contact is not aligned with either the first source contact or the first drain contact in the X-direction.

16. The metal oxide semiconductor field effect transistor device of claim 15, wherein at least one of the first gate contacts is located on any one of first imaginary lines that extend parallel along the X-direction and each pass between two adjacent ones of the first source contacts.

17. The mosfet device of claim 15, wherein all of the first drain contacts are located on a first side of a virtual line extending in the X-direction, and all of the first gate contacts are located on an opposite side of the virtual line.

18. The metal oxide semiconductor field effect transistor device of claim 17, wherein the first drain contact has a bar shape or an oval shape.

19. The metal oxide semiconductor field effect transistor device of claim 18, wherein the first drain contact has a rectangular shape.

20. The mosfet device of claim 15, wherein all of the first source contacts are located on a first side of a virtual line extending in the X-direction, and all of the first gate contacts are located on an opposite side of the virtual line.

21. The metal oxide semiconductor field effect transistor device of claim 20, wherein the first source contact has a bar shape or an oval shape.

22. The metal oxide semiconductor field effect transistor device of claim 21,

the first drain contact has a rectangular shape.