KR20040009251A - Method of transistor in semiconductor device - Google Patents

Method of transistor in semiconductor device Download PDF

Info

Publication number
KR20040009251A
KR20040009251A KR1020020043125A KR20020043125A KR20040009251A KR 20040009251 A KR20040009251 A KR 20040009251A KR 1020020043125 A KR1020020043125 A KR 1020020043125A KR 20020043125 A KR20020043125 A KR 20020043125A KR 20040009251 A KR20040009251 A KR 20040009251A
Authority
KR
South Korea
Prior art keywords
transistor
region
layer
forming
isolation
Prior art date
Application number
KR1020020043125A
Other languages
Korean (ko)
Inventor
김석규
장형순
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020020043125A priority Critical patent/KR20040009251A/en
Publication of KR20040009251A publication Critical patent/KR20040009251A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for fabricating a transistor of a semiconductor device is provided to increase the width of a gate electrode of the transistor so that leakage current is reduced and the influence upon a current driving capability is minimized, by increasing the edge of an active region for forming a conductive layer of the transistor. CONSTITUTION: A mask layer is formed on a semiconductor substrate. A trench is formed in the substrate by using the mask layer as a pattern. An isolation layer is formed in the trench to divide the semiconductor substrate in such a way that a region having the isolation layer is defined as an isolation region(A) and a region not having the isolation layer is defined as an active region. An insulation layer is formed in the isolation region. A gate conductive layer is formed on a portion of the isolation region with no insulation layer and on the active region to form a gate electrode. A source/drain(S,D) is formed on the active region to form a transistor. Contacts are formed which expose the source/drain and the gate electrode. Contact pads(26) are formed in the respective contacts.

Description

반도체소자의 트랜지스터 형성방법{Method of transistor in semiconductor device}Method for forming transistor of semiconductor device

본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것이다.The present invention relates to a method for forming a transistor of a semiconductor device.

반도체소자가 고집적화됨에 따라 소자간의 분리기술이 핵심기술이 되었으며, 최근에는 반도체기판에 트렌치를 형성하고 이를 절연물질로 매립하는 STI 공정이 주목을 받고 있다. 최근에 사용되는 일반적인 STI 공정은 트렌치 형성을 위한 건식 식각 후 측벽산화막을 형성하여 상기 건식식각시 발생된 플라즈마 손상을 제거한 다음, 트렌치 매립용 절연막을 전면증착하고 화학적 물리적연마를 진행하여 활성영역의 노출과 트렌치 매립절연막의 평탄화를 행함으로써 소자분리구조를 형성하고 있다.As semiconductor devices have been highly integrated, separation technology between devices has become a core technology. Recently, the STI process that forms trenches in semiconductor substrates and fills them with insulating materials has attracted attention. In general, the STI process used in recent years forms a sidewall oxide layer after dry etching to form a trench to remove plasma damage generated during the dry etching, and then deposits a trench insulating insulating film and performs chemical physical polishing to expose the active region. And the trench filling insulating film are planarized to form an element isolation structure.

그러나 종래의 STI 공정은 소자분리영역의 가장자리가 활성영역의 표면보다 낮아지는, 이른바 STI 에지 리세스(Edge recess)현상이 있어, 이후에 형성되는 트랜지스터의 성능에 악영향을 주게 된다.However, in the conventional STI process, there is a so-called STI edge recess phenomenon in which the edge of the isolation region is lower than the surface of the active region, which adversely affects the performance of the transistor to be formed later.

즉, 트랜지스터를 형성하는 도전층은 상기 STI 에지 리세스 현상으로 인해 소자 분리막이 리세스된 영역에 매립되고, 매립된 영역은 상기 트랜지스터의 소스/드레인과 연결되어 기생트랜지스터를 형성하게 된다. 이와 같이 형성된 기생트랜지스터는 상기 트랜지스터의 전류구동능력을 저하시키고, 트랜지스터의 누설전류를 발생시키게 되는 원인이 된다.That is, the conductive layer forming the transistor is buried in the region where the device isolation layer is recessed due to the STI edge recess phenomenon, and the buried region is connected to the source / drain of the transistor to form a parasitic transistor. The parasitic transistor formed as described above causes a decrease in the current driving capability of the transistor and causes a leakage current of the transistor.

따라서, 상기와 같은 원인이 발생되는 기생트랜지스터의 생성을 억제하기에는 다소 많은 문제점이 유발하게 되므로, 형성된 기생 트랜지스터를 이용하여 상기트랜지스터의 전류구동능력의 저하 및 누설전류를 해결하기 위한 해결책들이 제시되었는데 이는 기생트랜지스터의 도전층을 증가시키는 도전층 탭을 기생트랜지스터에 형성하는 방법이 사용되었다.Therefore, some problems are caused to suppress the generation of parasitic transistors that cause the above causes. Therefore, solutions for reducing the current driving capability and leakage current of the transistors using parasitic transistors formed have been proposed. A method of forming a conductive layer tab in the parasitic transistor to increase the conductive layer of the parasitic transistor has been used.

그러나 기생트랜지스터의 도전층 탭은 상기 트랜지스터에 생성된 소스를 노출하는 콘택 및 드레인을 노출하는 콘택들간의 스페이스 마진이 감소하게 되어 상기 도전층 탭과 상기 콘택들간에 브릿지 가능성이 높아지게 되는 문제점이 발생한다.However, the conductive layer tap of the parasitic transistor has a problem that the space margin between the contact exposing the source generated in the transistor and the contact exposing the drain is reduced, thereby increasing the possibility of bridging between the conductive layer tap and the contacts. .

상술한 문제점을 해결하기 위한 본 발명은 상기 트랜지스터에 발생하는 전류구동능력의 저하 및 증가하는 누설전류를 해결할 수 있도록 하는 반도체소자의 트랜지스터 형성방법을 제공함에 있다.The present invention for solving the above problems is to provide a method of forming a transistor of a semiconductor device that can solve the degradation of the current driving capability and the increased leakage current generated in the transistor.

도 1 내지 도 6은 본 발명에 따른 반도체소자의 트랜지스터 형성방법을 도시한 공정순서도 및 레이아웃이다.1 to 6 are process flowcharts and layouts showing a method of forming a transistor of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 상세한 설명** Detailed description of the main parts of the drawings *

10 : 반도체기판A : 소자분리영역10: semiconductor substrate A: device isolation region

12 : 마스크 층B : 소자활성영역12: mask layer B: device active region

14 : 소자분리막22a : 트랜지스터14 device isolation layer 22a transistor

22b : 기생트랜지스터S : 소스22b: Parasitic Transistor S: Source

D : 드레인 26 : 콘택패드D: Drain 26: Contact pad

상기 목적을 달성하기 위하여 본 발명에서는, 반도체 기판에 마스크층을 형성하는 단계; 마스크층을 패턴으로 하여 상기 반도체기판에 트렌치를 형성하고, 상기 트랜치에 소자분리막을 형성하여 소자분리막이 형성된 영역을 소자분리영역으로 하고, 소자분리막이 형성되지 않은 영역을 소자활성영역으로 상기 반도체기판을 구분하는 단계; 상기 소자분리영역에 절연층을 형성하는 단계; 상기 소자분리영역의 절연층이 형성되지 않은 부분 및 상기 소자활성영역 상에 게이트 도전층을 형성하여 게이트전극을 형성하는 단계; 상기 소자활성영역 상에 소스/드레인을 형성하여 트랜지스터를 형성하는 단계; 상기 소스 , 드레인 및 게이트 전극을 노출하는 콘택을 각각 형성하는 단계; 및 상기 각각의 콘택에 콘택 패드를 형성하는 단계로 이루어진다.In order to achieve the above object, in the present invention, forming a mask layer on a semiconductor substrate; A trench is formed in the semiconductor substrate using a mask layer as a pattern, an isolation layer is formed in the trench, and a region in which the isolation layer is formed is a device isolation region, and the region in which the isolation layer is not formed is an active region of the semiconductor substrate. Classifying; Forming an insulating layer in the device isolation region; Forming a gate electrode by forming a gate conductive layer on a portion where the insulating layer of the device isolation region is not formed and on the device active region; Forming a transistor by forming a source / drain on the device active region; Forming contacts that expose the source, drain, and gate electrodes, respectively; And forming contact pads in the respective contacts.

또, 상기 절연층은 게이트 도전층이 형성될 수 있는 소자활성영역이 증가되도록 소자분리영역에 형성한다.In addition, the insulating layer is formed in the device isolation region to increase the device active region in which the gate conductive layer can be formed.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1 내지 도 6은 본 발명에 따른 트랜지스터 형성방법을 도시한 공정순서도 및 레이아웃이고, 이를 참조하여 설명하면, 다음과 같다.1 to 6 are process flowcharts and layouts showing a method of forming a transistor according to the present invention, which will be described with reference to the following.

도 1을 참조하면, 반도체기판(10) 상에 후속의 트렌치 형성을 위한 기판 식각시 마스크로 사용될 물질로서, 상기 반도체기판과의 식각 선택비가 우수한 물질을 소정의 두께로 증착하여 마스크 층(12)을 형성한다. 다음으로, 상기 마스크 층(12)상에 비활성영역을 노출시키는 패턴을 형성하고, 이를 식각마스크로 사용하여 상기 마스크 층(12)을 식각하여 트렌치를 형성한다. 상기 형성된 트렌치에 산화막을 형성 매립하여 이를 평탄화함으로써 소자분리막(14)을 형성한다.Referring to FIG. 1, a mask layer 12 is formed by depositing a material having a high etching selectivity with respect to the semiconductor substrate to a predetermined thickness as a material to be used as a mask for etching a substrate for subsequent trench formation on the semiconductor substrate 10. To form. Next, a pattern is formed on the mask layer 12 to expose the inactive region, and the trench is formed by etching the mask layer 12 using the pattern as an etching mask. An isolation layer 14 is formed by forming an oxide layer in the formed trench and planarizing the oxide layer.

도 2를 참조하면, 식각액을 사용하여 상기 마스크층(12)을 제거함으로써 소자활성영역(A)과 소자분리영역(B)을 정의한다. 이 때, 상기 마스크층(14)을 식각하는 과정에서 트렌치영역이 매립된 소자분리막(14)이 리세스되는 현상(미도시)이 발생하는데, 이후에 트랜지스터 형성공정에서 이 리세스현상이 발생된 영역에는 기생트랜지스터를 형성한다.Referring to FIG. 2, the device active region A and the device isolation region B are defined by removing the mask layer 12 using an etchant. At this time, a phenomenon (not shown) in which the device isolation layer 14 having the trench region embedded therein is recessed in the process of etching the mask layer 14 is performed. Parasitic transistors are formed in the region.

도 3은 도 2에 절연층(18)이 형성된 레이아웃을 도시하고 있다.3 shows a layout in which the insulating layer 18 is formed in FIG. 2.

도 3을 참조하면, 상기 정의된 반도체기판의 소자분리영역(B)상에절연층(18)을 형성한다. 이와 같이 형성된 절연층(18)은 이후에 트랜지스터의 도전층이 형성되는 소자활성영역(A)의 가장자리 부분을 증가시키고, 이 증가된 소자활성영역(A)에 트랜지스터의 도전층이 형성되면, 게이트전극 폭이 증가되면서 트랜지스터의 누설전류의 감소 및 전류구동능력의 영향을 최소화할 수 있도록 하기 위함이다.Referring to FIG. 3, an insulating layer 18 is formed on the isolation region B of the semiconductor substrate as defined above. The insulating layer 18 thus formed increases the edge portion of the device active region A in which the conductive layer of the transistor is subsequently formed, and when the conductive layer of the transistor is formed in the increased device active region A, the gate This is to reduce the leakage current and minimize the influence of the current driving capability of the transistor as the electrode width is increased.

도 4를 참조하면, 다음으로, 상기 소자분리영역 상의 절연층이 형성되지 않은 영역 및 상기 소자활성영역(A) 상에 게이트 도전층을 형성한다. 이 게이트 도전층을 사진/식각으로 패터닝하여 게이트 전극을 형성한다.Referring to FIG. 4, a gate conductive layer is formed on a region where an insulating layer is not formed on the device isolation region and on the device active region A. Referring to FIG. The gate conductive layer is patterned by photo / etch to form a gate electrode.

그리고 이 게이트 전극을 패턴으로 하여 이온주입공정을 수행하여 소스/드레인 영역을 형성함으로써 트랜지스터(22a)를 형성한다.The transistor 22a is formed by forming an source / drain region by performing an ion implantation process using the gate electrode as a pattern.

또, 상기 리세스된 소자분리막(14)에는 트랜지스터(22a) 형성공정을 거치는 동안 게이트 도전층(22)이 형성됨으로써 기생트랜지스터(22b)가 형성된다.In addition, a parasitic transistor 22b is formed in the recessed device isolation layer 14 by forming the gate conductive layer 22 during the transistor 22a forming process.

도 5를 참조하면, (기생트랜지스터를 포함한)트랜지스터에 형성된 게이트 전극(22), 소스(S) 및 드레인(D)에 이 게이트전극을 노출하는 콘택(C1)과, 소스를 노출하는 콘택(C2) 및 드레인을 노출하는 콘택(C3)을 형성한다.Referring to FIG. 5, the contact C1 exposing the gate electrode to the gate electrode 22, the source S and the drain D formed in the transistor (including the parasitic transistor), and the contact C2 exposing the source. ) And a contact C3 exposing the drain.

도 6을 참조하면, 상기 콘택들(C1, C2, C3)을 포함한 트랜지스터에 패드용 도전층을 형성하여 사진/식각함으로써 콘택 패드(26)를 형성한다. 이 콘택 패드(26)는 상기 콘택들(C1, C2, C3)과 다른 소자와의 상호 연결을 위해 형성한다.Referring to FIG. 6, a contact pad 26 is formed by forming a photoconductive layer for forming a pad conductive layer in a transistor including the contacts C1, C2, and C3. The contact pads 26 are formed for interconnection of the contacts C1, C2, C3 with other devices.

이상에서 살펴본 바와 같이 트랜지스터의 도전층이 형성되는 소자활성영역의 가장자리 부분을 증가시키게 되면, 트랜지스터의 게이트전극 폭이 증가되고, 이로인해 트랜지스터의 누설전류의 감소 및 전류구동능력의 영향을 최소화할 수 있도록 하는 효과가 있다.As described above, when the edge portion of the device active region in which the conductive layer of the transistor is formed is increased, the gate electrode width of the transistor is increased, thereby minimizing the leakage current and the influence of the current driving capability of the transistor. It is effective.

이상에서 살펴본 바와 같이 트랜지스터의 도전층이 형성되는 소자활성영역의 가장자리 부분을 증가시켜 트랜지스터의 게이트전극 폭이 증가됨으로써 트랜지스터의 누설전류의 감소 및 전류구동능력의 영향을 최소화할 수 있도록 하는 효과가 있다.As described above, the width of the gate electrode of the transistor is increased by increasing the edge portion of the device active region in which the conductive layer of the transistor is formed, thereby reducing the leakage current of the transistor and minimizing the influence of the current driving capability. .

Claims (2)

반도체 기판에 마스크층을 형성하는 단계;Forming a mask layer on the semiconductor substrate; 마스크층을 패턴으로 하여 상기 반도체기판에 트렌치를 형성하고, 상기 트랜치에 소자분리막을 형성하여 소자분리막이 형성된 영역을 소자분리영역으로 하고, 소자분리막이 형성되지 않은 영역을 소자활성영역으로 상기 반도체기판을 구분하는 단계;A trench is formed in the semiconductor substrate using a mask layer as a pattern, an isolation layer is formed in the trench, and a region in which the isolation layer is formed is a device isolation region, and the region in which the isolation layer is not formed is an active region of the semiconductor substrate. Classifying; 상기 소자분리영역에 절연층을 형성하는 단계;Forming an insulating layer in the device isolation region; 상기 소자분리영역의 절연층이 형성되지 않은 부분 및 상기 소자활성영역 상에 게이트 도전층을 형성하여 게이트전극을 형성하는 단계;Forming a gate electrode by forming a gate conductive layer on a portion where the insulating layer of the device isolation region is not formed and on the device active region; 상기 소자활성영역 상에 소스/드레인을 형성하여 트랜지스터를 형성하는 단계;Forming a transistor by forming a source / drain on the device active region; 상기 소스 , 드레인 및 게이트 전극을 노출하는 콘택을 각각 형성하는 단계; 및Forming contacts that expose the source, drain, and gate electrodes, respectively; And 상기 각각의 콘택에 콘택 패드를 형성하는 단계로 이루어진 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.Forming contact pads in the respective contacts. 제 1 항에 있어서, 상기 절연층은The method of claim 1, wherein the insulating layer 게이트 도전층이 형성될 수 있는 소자활성영역이 증가되도록 소자분리영역에형성하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.A method of forming a transistor in a semiconductor device, characterized in that formed in the device isolation region to increase the device active region in which the gate conductive layer can be formed.
KR1020020043125A 2002-07-23 2002-07-23 Method of transistor in semiconductor device KR20040009251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020043125A KR20040009251A (en) 2002-07-23 2002-07-23 Method of transistor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020043125A KR20040009251A (en) 2002-07-23 2002-07-23 Method of transistor in semiconductor device

Publications (1)

Publication Number Publication Date
KR20040009251A true KR20040009251A (en) 2004-01-31

Family

ID=37318189

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020043125A KR20040009251A (en) 2002-07-23 2002-07-23 Method of transistor in semiconductor device

Country Status (1)

Country Link
KR (1) KR20040009251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150145606A (en) * 2014-06-20 2015-12-30 삼성전자주식회사 Layouts and Vertical Structures of MOSFET Devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150145606A (en) * 2014-06-20 2015-12-30 삼성전자주식회사 Layouts and Vertical Structures of MOSFET Devices

Similar Documents

Publication Publication Date Title
JP2008028357A (en) Semiconductor device and method for manufacturing the same
JP2005526399A (en) Method for forming a transistor with a plurality of gate insulating layers of different thickness
KR20070069405A (en) Method of fabricating the semiconductor device
KR100374227B1 (en) Manufacturing method for semiconductor device
KR20040009251A (en) Method of transistor in semiconductor device
KR100510772B1 (en) Formation method of silicon on insulator substrate for semiconductor
KR20050027381A (en) Method of forming recess channel of transistor
KR20030049783A (en) Method of forming an isolation film in semiconductor device
KR100504948B1 (en) Method of forming contact plug in semiconductor devices
KR100477786B1 (en) Method for forming contact in semiconductor device
KR100713905B1 (en) Method for fabricating semiconductor device
KR100290912B1 (en) Method for fabricating isolation region of semiconductor device
KR100451512B1 (en) method for forming isolation layer
KR19990069451A (en) Trench element isolation
KR100314800B1 (en) method of fabricating thin film transistor in semiconductor device
KR101022672B1 (en) Semiconductor device with trench type isolation and method for making the same
KR20030001965A (en) Method for fabricating semiconductor device
KR20030001972A (en) Method of manufacturing semiconductor device
KR20030095038A (en) Method of manufacture semiconductor device
KR20060128152A (en) Method for manufacturing semiconductor device
KR20080029268A (en) Isolation layer of semiconductor device and method forming the same
KR20020096684A (en) Gate line structure of transistor
KR20070036979A (en) Method for forming landing plug of semiconductor
KR20050069585A (en) Isolation method for semiconductor device
KR20040002275A (en) Forming method for field oxide of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination